coreboot January 2009

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320 discussions

r3850 - trunk/util/flashrom
by svn＠coreboot.org 07 Jan '09

07 Jan '09

Author: uwe Date: 2009-01-07 13:35:09 +0100 (Wed, 07 Jan 2009) New Revision: 3850 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Add SST49LF020 support. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2009-01-07 12:15:46 UTC (rev 3849) +++ trunk/util/flashrom/flash.h 2009-01-07 12:35:09 UTC (rev 3850) @@ -356,6 +356,7 @@ #define SST_39VF040 0xD7 #define SST_49LF040B 0x50 #define SST_49LF040 0x51 +#define SST_49LF020 0x61 #define SST_49LF020A 0x52 #define SST_49LF080A 0x5B #define SST_49LF002A 0x57 Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2009-01-07 12:15:46 UTC (rev 3849) +++ trunk/util/flashrom/flashchips.c 2009-01-07 12:35:09 UTC (rev 3850) @@ -626,6 +626,12 @@ probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc }, + {"SST", "SST49LF020", SST_ID, SST_49LF020, + 256, 16 * 1024, + TEST_OK_PR, + probe_jedec, erase_49lf040, write_49lf040 + }, + {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, TEST_UNTESTED,

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[PATCH] flashrom: add AMD-768 chipset support
by Sven Schnelle 07 Jan '09

07 Jan '09

Hi List, the patch attached adds support for the AMD-768 chipset. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3845) +++ chipset_enable.c (working copy) @@ -114,6 +114,19 @@ return 0; } +static int enable_flash_amd768(struct pci_dev *dev, const char *name) +{ + /* enable address decoding for LPC */ + pci_write_byte(dev, 0x40, pci_read_byte(dev, 0x40) | 0x01); + pci_write_byte(dev, 0x43, 0xbf); + + return 0; +} + /* Datasheet: * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -937,6 +950,7 @@ {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520}, + {0x1022, 0x7440, "AMD AMD-768", enable_flash_amd768}, }; void print_supported_chipsets(void)

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r3849 - trunk/util/flashrom
by svn＠coreboot.org 07 Jan '09

07 Jan '09

Author: uwe Date: 2009-01-07 13:15:46 +0100 (Wed, 07 Jan 2009) New Revision: 3849 Modified: trunk/util/flashrom/chipset_enable.c Log: Add AMD-768 chipset support. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2009-01-07 12:11:13 UTC (rev 3848) +++ trunk/util/flashrom/chipset_enable.c 2009-01-07 12:15:46 UTC (rev 3849) @@ -938,6 +938,7 @@ {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520}, + {0x1022, 0x7440, "AMD AMD-768", enable_flash_amd8111}, }; void print_supported_chipsets(void)

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[PATCH] flashrom: add i631x LPC support
by Sven Schnelle 07 Jan '09

07 Jan '09

Hi List, this patch adds support for the Intel i631x Chipset. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3845) +++ chipset_enable.c (working copy) @@ -804,6 +804,12 @@ return 0; } +static int enable_flash_i631x(struct pci_dev *dev, const char *name) +{ + pci_write_byte(dev, 0xdc, pci_read_byte(dev, 0xdc) | 0x01); + return 0; +} + /** * Usually on the x86 architectures (and on other PC-like platforms like some * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD @@ -937,4 +943,5 @@ {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520}, + {0x8086, 0x2670, "Intel 631xESB/632xESB/3100", enable_flash_i631x}, }; void print_supported_chipsets(void)

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r3848 - trunk/util/flashrom
by svn＠coreboot.org 07 Jan '09

07 Jan '09

Author: uwe Date: 2009-01-07 13:11:13 +0100 (Wed, 07 Jan 2009) New Revision: 3848 Modified: trunk/util/flashrom/chipset_enable.c Log: Add i631x LPC support. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2009-01-06 16:45:42 UTC (rev 3847) +++ trunk/util/flashrom/chipset_enable.c 2009-01-07 12:11:13 UTC (rev 3848) @@ -880,6 +880,7 @@ {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e}, {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, + {0x8086, 0x2670, "Intel 631xESB/632xESB/3100", enable_flash_ich_dc}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7},

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[PATCH] YABEL: add license to pmm files
by Pattrick Hueper 07 Jan '09

07 Jan '09

Hi, i just saw, that i forgot to add a BSD license header to the PMM files, this patch fixes that. Patty Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> --- util/x86emu/yabel/pmm.c | 5 +++++ util/x86emu/yabel/pmm.h | 5 +++++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/util/x86emu/yabel/pmm.c b/util/x86emu/yabel/pmm.c index b6ec49f..d909931 100644 --- a/util/x86emu/yabel/pmm.c +++ b/util/x86emu/yabel/pmm.c @@ -1,6 +1,11 @@ /**************************************************************************** * YABEL BIOS Emulator * + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> ****************************************************************************/ diff --git a/util/x86emu/yabel/pmm.h b/util/x86emu/yabel/pmm.h index 56298ad..e1d0566 100644 --- a/util/x86emu/yabel/pmm.h +++ b/util/x86emu/yabel/pmm.h @@ -1,6 +1,11 @@ /**************************************************************************** * YABEL BIOS Emulator * + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> ****************************************************************************/ -- 1.6.0.4

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[RFC]flashrom: improve basic design
by FENG Yu Ning 07 Jan '09

07 Jan '09

There is a defect in basic design of flashrom. It leads to problems some developers are facing or going to face. A partial solution is proposed. 1. The Defect struct flashchip { /* ... */ int (*probe) (struct flashchip *flash); int (*erase) (struct flashchip *flash); int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); /* ... */ }; The struct specifies drivers for operations. It is a good design if the drivers deal with flash chips directly and provide interfaces for upper layer program to use. However, those drivers deal with every component in the communication chain. They do not fit into a structure storing information closely related to flash chips. 2. Problems Supporting non-standard flash chips needs to write a new driver. It requires the developer to be familiar with the internals of flashrom. Probe functions and IDs are seperated. They are associated by the flashchip structure. In nature, probe functions and IDs are questions and answers, and should be associated more closely. Seperated ID fields in struct flashchip are not very meaningful. flashrom will probably have plugins in the future. Though chips are operated in the same way from the view of their host devices, there is not much useful information for plugins in struct flashchip. 3. Solution We need an abstract specification of operations in struct flashchip, not actual code. If there have to be some information not related to flash chips, the less there is, the better. Abstract operation specification for SPI flash chips: /* BEGINNING OF SPECIFICATION */ struct cycles { u8 type; /* CYCLETYPE_PREOPCODE, CYCLETYPE_OPCODE, */ /* CYCLETYPE_ADDRESS, CYCLETYPE_DUMMY, */ /* CYCLETYPE_DATA_IN, CYCLETYPE_DATA_OUT */ u8 length; /* in bytes */ u8 value_type; /* VALUETYPE_VARIABLE, VALUETYPE_FIXED */ u32 value; }; struct cycles byte_read[] = {{CYCLETYPE_OPCODE, 1, VALUETYPE_FIXED, 0x3}, {CYCLETYPE_ADDRESS, 3, VALUETYPE_VARIABLE}, {CYCLETYPE_DATA_IN, 1, VALUETYPE_VARIABLE} }; struct cycles byte_program[] = {{CYCLETYPE_PREOPCODE, 1, VALUETYPE_FIXED, 0x6}, {CYCLETYPE_OPCODE, 1, VALUETYPE_FIXED, 0x2}, {CYCLETYPE_ADDRESS, 3, VALUETYPE_VARIABLE}, {CYCLETYPE_DATA_OUT, 1, VALUETYPE_VARIABLE} }; struct cycles SST25VF040B_probe_rdid[] = {{CYCLETYPE_OPCODE, 1, VALUETYPE_FIXED, 0x90}, {CYCLETYPE_ADDRESS, 3, VALUETYPE_FIXED, 0}, {CYCLETYPE_DATA_IN, 2, VALUETYPE_FIXED, 0xbf8d} }; struct cycles SST25VF040B_probe_jedec[] = {{CYCLETYPE_OPCODE, 1, VALUETYPE_FIXED, 0x9f}, {CYCLETYPE_DATA_IN, 3, VALUETYPE_FIXED, 0xbf258d} }; /* END OF SPECIFICATION */ Specifications for LPC and FWH flash chips will be different, but the point is abstraction. Comments are appreciated. New year's greetings, yu ning

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r1102 - coreboot-v3/util/x86emu/yabel/compat
by svn＠coreboot.org 07 Jan '09

07 Jan '09

Author: phueper Date: 2009-01-07 10:14:03 +0100 (Wed, 07 Jan 2009) New Revision: 1102 Modified: coreboot-v3/util/x86emu/yabel/compat/functions.c coreboot-v3/util/x86emu/yabel/compat/time.h Log: YABEL: (trivial) add BSD license header to files missing a license header Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Acked-by: Pattrick Hueper <phueper(a)hueper.net> Modified: coreboot-v3/util/x86emu/yabel/compat/functions.c =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-01-06 00:05:45 UTC (rev 1101) +++ coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-01-07 09:14:03 UTC (rev 1102) @@ -1,3 +1,13 @@ +/**************************************************************************** + * YABEL BIOS Emulator + * + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> + ****************************************************************************/ /* this file contains functions provided by SLOF, that the current biosemu implementation needs * they should go away inthe future... Modified: coreboot-v3/util/x86emu/yabel/compat/time.h =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/time.h 2009-01-06 00:05:45 UTC (rev 1101) +++ coreboot-v3/util/x86emu/yabel/compat/time.h 2009-01-07 09:14:03 UTC (rev 1102) @@ -1,3 +1,13 @@ +/**************************************************************************** + * YABEL BIOS Emulator + * + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> + ****************************************************************************/ #ifndef _BIOSEMU_COMPAT_TIME_H #define _BIOSEMU_COMPAT_TIME_H

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r3847 - in trunk/coreboot-v2/src/mainboard/amd: dbm690t pistachio
by svn＠coreboot.org 06 Jan '09

06 Jan '09

Author: mjones Date: 2009-01-06 17:45:42 +0100 (Tue, 06 Jan 2009) New Revision: 3847 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c Log: The ACPI PSS CPU Pstate table was calculating the frequency incorrectly for revF CPUs. The 100MHz/200MHz stepping is already handled in the FID setting and doesn't need to be checked to set the fid_multiplier. The multiplier is always 100. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: zheng bao <zheng.bao(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-01-06 00:33:30 UTC (rev 3846) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-01-06 16:45:42 UTC (rev 3847) @@ -258,12 +258,11 @@ return 0; } - /*get the multipier of the fid frequency */ + /* Get the multipier of the fid frequency */ /* - * In RevG, 100MHz step is added + * Fid multiplier is always 100 revF and revG. */ - cpuid1 = cpuid(0x80000007); - fid_multiplier = ((cpuid1.edx & 0x40) >> 6) * 100; + fid_multiplier = 100; /* * Formula1: CPUFreq = FID * fid_multiplier + 800 Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-01-06 00:33:30 UTC (rev 3846) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-01-06 16:45:42 UTC (rev 3847) @@ -258,12 +258,11 @@ return 0; } - /*get the multipier of the fid frequency */ + /* Get the multipier of the fid frequency */ /* - * In RevG, 100MHz step is added + * Fid multiplier is always 100 revF and revG. */ - cpuid1 = cpuid(0x80000007); - fid_multiplier = ((cpuid1.edx & 0x40) >> 6) * 100; + fid_multiplier = 100; /* * Formula1: CPUFreq = FID * fid_multiplier + 800

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[PATCH] Update PCI dev_root struct definition generation explanation comment to v3 reality
by Mart Raudsepp 06 Jan '09

06 Jan '09

Update PCI dev_root struct definition generation explanation comment to v3 reality v3 uses dtc to create $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c not the config.py tool as in v2. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- device/root_device.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/device/root_device.c b/device/root_device.c index 8d809bc..34b74d3 100644 --- a/device/root_device.c +++ b/device/root_device.c @@ -200,6 +200,7 @@ struct device_operations default_dev_ops_root = { * The root of device tree. * * This is the root of the device tree. The device tree is defined in the - * static.c file and is generated by config tool during compile time. + * build/mainboard/<board>/statictree.c file and is generated by the dtc util + * during build time. */ extern struct device dev_root; -- 1.6.0.4

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coreboot January 2009