coreboot January 2009

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[patch] update the readme of flashrom
by Idwer Vollering 11 Jan '09

11 Jan '09

Mimicked from flashrom.c, see patch. Signed-off-by: Idwer <vidwer(a)gmail.com>

2 1

r3855 - trunk/util/flashrom
by svn＠coreboot.org 11 Jan '09

11 Jan '09

Author: stuge Date: 2009-01-11 04:31:02 +0100 (Sun, 11 Jan 2009) New Revision: 3855 Modified: trunk/util/flashrom/README Log: flashrom: Update usage in README Mimicked from flashrom.c Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/README =================================================================== --- trunk/util/flashrom/README 2009-01-11 00:35:30 UTC (rev 3854) +++ trunk/util/flashrom/README 2009-01-11 03:31:02 UTC (rev 3855) @@ -21,7 +21,7 @@ Usage ----- - $ flashrom [-rwvEVfh] [-c chipname] [-s exclude_start] [-e exclude_end] + $ flashrom [-rwvEVfLhR] [-c chipname] [-s exclude_start] [-e exclude_end] [-m [vendor:]part] [-l file.layout] [-i imagename] [file] -r | --read: read flash and save into file -w | --write: write file into flash (default when @@ -36,6 +36,9 @@ -f | --force: force write without checking image -l | --layout <file.layout>: read rom layout from file -i | --image <name>: only flash image name from flash layout + -L | --list-supported: print supported devices + -h | --help: print this help text + -R | --version: print the version (release) If no file is specified, then all that happens is that flash info is dumped and the flash chip is set to writable.

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r3854 - trunk/coreboot-v2/src/arch/i386/init
by svn＠coreboot.org 11 Jan '09

11 Jan '09

Author: oxygene Date: 2009-01-11 01:35:30 +0100 (Sun, 11 Jan 2009) New Revision: 3854 Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript.lb trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb Log: Ignore some more sections, created by newer toolchains Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript.lb 2009-01-08 16:53:13 UTC (rev 3853) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript.lb 2009-01-11 00:35:30 UTC (rev 3854) @@ -62,6 +62,8 @@ /DISCARD/ : { *(.comment) + *(.comment.*) *(.note) + *(.note.*) } } Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb 2009-01-08 16:53:13 UTC (rev 3853) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb 2009-01-11 00:35:30 UTC (rev 3854) @@ -52,5 +52,7 @@ /DISCARD/ : { *(.comment) *(.note) + *(.comment.*) + *(.note.*) } } Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb 2009-01-08 16:53:13 UTC (rev 3853) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb 2009-01-11 00:35:30 UTC (rev 3854) @@ -67,5 +67,7 @@ /DISCARD/ : { *(.comment) *(.note) + *(.comment.*) + *(.note.*) } }

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[PATCH]coreboot-v2: ignore some more sections
by Patrick Georgi 10 Jan '09

10 Jan '09

Hi, after I updated my SuSE system, coreboot.strip grew to 4GB. Seems like they introduced some new notes sections that got in the way. Attached patch ignores them, too. It should be trivial, but I'd rather have some confirmation. Regards, Patrick Georgi

2 1

SeaBIOS and Windows 7
by Carl-Daniel Hailfinger 10 Jan '09

10 Jan '09

Hi, Microsoft is offering free _beta_ downloads of Windows 7 and Windows Server 2008 R2 while supplies last (2.5 million downloads is the total limit for Windows 7). Windows 7 is available at http://www.microsoft.com/germany/windows/windows-7/beta-download.aspx (that server has load problems, but some useful information can be found at http://www.heise.de/newsticker/foren/S-Direkt-Download-Eng-Updatetd/forum-1… ) Windows Server 2008 R2 is available at http://www.microsoft.com/downloads/details.aspx?FamilyId=85CFE4C9-34DE-477C… Has anybody downloaded this and tested it with SeaBIOS? If it works, we have a real marketing opportunity. I'd download it myself, but my hd doesn't have enough space for an abuild run and these isos. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH 1/2] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
by Mart Raudsepp 09 Jan '09

09 Jan '09

cs5536: Add a NAND device and do the IDE PCI header disabling on time. This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form. Also corrected the documentation of ide_init() to match current reality. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/dts | 3 ++ mainboard/artecgroup/dbe62/dts | 3 ++ southbridge/amd/cs5536/cs5536.c | 47 ++++++++++++++++++++++++-------------- southbridge/amd/cs5536/nand | 23 +++++++++++++++++++ 4 files changed, 59 insertions(+), 17 deletions(-) create mode 100644 southbridge/amd/cs5536/nand diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index b443533..48df288 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,6 +109,9 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 213c397..3cbe0ff 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 89d64d6..0c5adb1 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -98,6 +98,21 @@ static void hide_vpci(u32 vpci_devid) } /** + * Enables the FLASH PCI header when NAND device existing in mainboard device + * tree. Used when the mainboard has a FLASH part instead of an IDE drive and + * that fact is expressed in the mainboard device tree. + * Must be called after VSA init but before PCI scans to enable the flash + * PCI device header early enough - that is .phase2_fixup of the device. + * + * @param dev The device. + */ +static void nand_phase2(struct device *dev) +{ + /* Tell VSA to use FLASH PCI header. Not IDE header. */ + hide_vpci(0x800079C4); +} + +/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -170,16 +185,6 @@ static void chipset_flash_setup(struct southbridge_amd_cs5536_dts_config *sb) printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); } -/** - * Use this in the event that you have a FLASH part instead of an IDE drive. - * Run after VSA init to enable the flash PCI device header. - */ -static void enable_ide_nand_flash_header(void) -{ - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - hide_vpci(0x800079C4); -} - #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E @@ -601,8 +606,8 @@ void chipsetinit(void) #define IDE_ETC 0x50 /** - * Enabled the IDE. This is code that is optionally run if the ide_enable is set - * in the mainboard dts. + * Enables the IDE. This is code that is run if there is an ide device in the mainboard + * device tree and it has set non-zero "enable_ide". * * @param dev The device */ @@ -658,11 +663,6 @@ static void southbridge_init(struct device *dev) printk(BIOS_SPEW, "cs5536: done second call vr_write\n"); } - printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", - __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash != 0) - enable_ide_nand_flash_header(); - enable_USB_port4(sb); /* disable unwanted virtual PCI devices */ @@ -733,3 +733,16 @@ struct device_operations cs5536_ide = { .ops_pci = &pci_dev_ops_pci, }; +struct device_operations cs5536_nand = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_FLASH}}}, + .constructor = default_device_constructor, + .phase2_fixup = nand_phase2, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = 0, /* No Option ROMs */ + .ops_pci = &pci_dev_ops_pci, +}; diff --git a/southbridge/amd/cs5536/nand b/southbridge/amd/cs5536/nand new file mode 100644 index 0000000..69f4fa4 --- /dev/null +++ b/southbridge/amd/cs5536/nand @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_nand"; +}; -- 1.6.0.4

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r1114 - in coreboot-v3: mainboard/adl/msm800sev mainboard/amd/db800 mainboard/amd/norwich mainboard/amp/tinygx mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3 southbridge/amd/cs5536
by svn＠coreboot.org 09 Jan '09

09 Jan '09

Author: mraudsepp Date: 2009-01-09 19:12:08 +0100 (Fri, 09 Jan 2009) New Revision: 1114 Modified: coreboot-v3/mainboard/adl/msm800sev/dts coreboot-v3/mainboard/amd/db800/dts coreboot-v3/mainboard/amd/norwich/dts coreboot-v3/mainboard/amp/tinygx/dts coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/mainboard/pcengines/alix2c3/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/ide Log: cs5536: Remove redundant enable_ide variable from ide device. The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form. cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not necessary. Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole IDE device removed, which results in the ide_init() code not being ran as before (before it was called but early return from enable_ide == 0, now it won't be called in the first place). Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/adl/msm800sev/dts =================================================================== --- coreboot-v3/mainboard/adl/msm800sev/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/adl/msm800sev/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -39,7 +39,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/winbond/w83627hf/dts"); Modified: coreboot-v3/mainboard/amd/db800/dts =================================================================== --- coreboot-v3/mainboard/amd/db800/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/amd/db800/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -54,7 +54,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/winbond/w83627hf/dts"); Modified: coreboot-v3/mainboard/amd/norwich/dts =================================================================== --- coreboot-v3/mainboard/amd/norwich/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/amd/norwich/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -57,7 +57,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; }; }; Modified: coreboot-v3/mainboard/amp/tinygx/dts =================================================================== --- coreboot-v3/mainboard/amp/tinygx/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/amp/tinygx/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -54,7 +54,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/ite/it8716f/dts"); Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -112,8 +112,5 @@ pci@f,1 { /config/("southbridge/amd/cs5536/nand"); }; - pci@f,2 { - /config/("southbridge/amd/cs5536/ide"); - }; }; }; Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -66,8 +66,5 @@ pci@f,1 { /config/("southbridge/amd/cs5536/nand"); }; - pci@f,2 { - /config/("southbridge/amd/cs5536/ide"); - }; }; }; Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -51,7 +51,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/winbond/w83627hf/dts"); Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/dts 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2009-01-09 18:12:08 UTC (rev 1114) @@ -51,7 +51,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; }; }; Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-01-09 18:12:08 UTC (rev 1114) @@ -609,7 +609,7 @@ /** * Enables the IDE. This is code that is run if there is an ide device in the mainboard - * device tree and it has set non-zero "enable_ide". + * device tree. * * @param dev The device */ @@ -617,11 +617,6 @@ { u32 ide_cfg; - struct southbridge_amd_cs5536_ide_config *ide = - (struct southbridge_amd_cs5536_ide_config *)dev->device_configuration; - if (!ide->enable_ide) - return; - printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ Modified: coreboot-v3/southbridge/amd/cs5536/ide =================================================================== --- coreboot-v3/southbridge/amd/cs5536/ide 2009-01-09 18:12:05 UTC (rev 1113) +++ coreboot-v3/southbridge/amd/cs5536/ide 2009-01-09 18:12:08 UTC (rev 1114) @@ -20,7 +20,4 @@ { device_operations = "cs5536_ide"; - - /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ - enable_ide = "0"; };

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r1113 - in coreboot-v3: mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 southbridge/amd/cs5536
by svn＠coreboot.org 09 Jan '09

09 Jan '09

Author: mraudsepp Date: 2009-01-09 19:12:05 +0100 (Fri, 09 Jan 2009) New Revision: 1113 Added: coreboot-v3/southbridge/amd/cs5536/nand Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: cs5536: Add a NAND device and do the IDE PCI header disabling on time. This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form. Also corrected the documentation of ide_init() to match current reality. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2009-01-09 14:17:06 UTC (rev 1112) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2009-01-09 18:12:05 UTC (rev 1113) @@ -109,6 +109,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2009-01-09 14:17:06 UTC (rev 1112) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2009-01-09 18:12:05 UTC (rev 1113) @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-01-09 14:17:06 UTC (rev 1112) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-01-09 18:12:05 UTC (rev 1113) @@ -98,6 +98,23 @@ } /** + * Enables the FLASH PCI header when NAND device existing in mainboard device + * tree. Used when the mainboard has a FLASH part instead of an IDE drive and + * that fact is expressed in the mainboard device tree. + * Must be called after VSA init but before PCI scans to enable the flash + * PCI device header early enough - that is .phase2_fixup of the device. + * + * @param dev The device. + */ +static void nand_phase2(struct device *dev) +{ + if (dev->enabled) { + /* Tell VSA to use FLASH PCI header. Not IDE header. */ + hide_vpci(0x800079C4); + } +} + +/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -170,16 +187,6 @@ printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); } -/** - * Use this in the event that you have a FLASH part instead of an IDE drive. - * Run after VSA init to enable the flash PCI device header. - */ -static void enable_ide_nand_flash_header(void) -{ - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - hide_vpci(0x800079C4); -} - #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E @@ -601,8 +608,8 @@ #define IDE_ETC 0x50 /** - * Enabled the IDE. This is code that is optionally run if the ide_enable is set - * in the mainboard dts. + * Enables the IDE. This is code that is run if there is an ide device in the mainboard + * device tree and it has set non-zero "enable_ide". * * @param dev The device */ @@ -658,11 +665,6 @@ printk(BIOS_SPEW, "cs5536: done second call vr_write\n"); } - printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", - __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash != 0) - enable_ide_nand_flash_header(); - enable_USB_port4(sb); /* disable unwanted virtual PCI devices */ @@ -733,3 +735,16 @@ .ops_pci = &pci_dev_ops_pci, }; +struct device_operations cs5536_nand = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_FLASH}}}, + .constructor = default_device_constructor, + .phase2_fixup = nand_phase2, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = 0, /* No Option ROMs */ + .ops_pci = &pci_dev_ops_pci, +}; Added: coreboot-v3/southbridge/amd/cs5536/nand =================================================================== --- coreboot-v3/southbridge/amd/cs5536/nand (rev 0) +++ coreboot-v3/southbridge/amd/cs5536/nand 2009-01-09 18:12:05 UTC (rev 1113) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_nand"; +};

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[PATCH 2/2] cs5536: Remove redundant enable_ide variable from ide device.
by Mart Raudsepp 09 Jan '09

09 Jan '09

cs5536: Remove redundant enable_ide variable from ide device. The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form. cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not necessary. Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole IDE device removed, which results in the ide_init() code not being ran as before (before it was called but early return from enable_ide == 0, now it won't be called in the first place). Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/adl/msm800sev/dts | 1 - mainboard/amd/db800/dts | 1 - mainboard/amd/norwich/dts | 1 - mainboard/amp/tinygx/dts | 1 - mainboard/artecgroup/dbe61/dts | 3 --- mainboard/artecgroup/dbe62/dts | 3 --- mainboard/pcengines/alix1c/dts | 1 - mainboard/pcengines/alix2c3/dts | 1 - southbridge/amd/cs5536/cs5536.c | 7 +------ southbridge/amd/cs5536/ide | 3 --- 10 files changed, 1 insertions(+), 21 deletions(-) diff --git a/mainboard/adl/msm800sev/dts b/mainboard/adl/msm800sev/dts index 46a2169..12e27a5 100644 --- a/mainboard/adl/msm800sev/dts +++ b/mainboard/adl/msm800sev/dts @@ -39,7 +39,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/winbond/w83627hf/dts"); diff --git a/mainboard/amd/db800/dts b/mainboard/amd/db800/dts index dd44487..75da7de 100644 --- a/mainboard/amd/db800/dts +++ b/mainboard/amd/db800/dts @@ -54,7 +54,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/winbond/w83627hf/dts"); diff --git a/mainboard/amd/norwich/dts b/mainboard/amd/norwich/dts index 6444e9d..ea7f9c0 100644 --- a/mainboard/amd/norwich/dts +++ b/mainboard/amd/norwich/dts @@ -57,7 +57,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; }; }; diff --git a/mainboard/amp/tinygx/dts b/mainboard/amp/tinygx/dts index 95f3722..75a93b0 100644 --- a/mainboard/amp/tinygx/dts +++ b/mainboard/amp/tinygx/dts @@ -54,7 +54,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/ite/it8716f/dts"); diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index 48df288..a6995ce 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -112,8 +112,5 @@ end pci@f,1 { /config/("southbridge/amd/cs5536/nand"); }; - pci@f,2 { - /config/("southbridge/amd/cs5536/ide"); - }; }; }; diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 3cbe0ff..8089e79 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -66,8 +66,5 @@ pci@f,1 { /config/("southbridge/amd/cs5536/nand"); }; - pci@f,2 { - /config/("southbridge/amd/cs5536/ide"); - }; }; }; diff --git a/mainboard/pcengines/alix1c/dts b/mainboard/pcengines/alix1c/dts index 724a74f..2f3d767 100644 --- a/mainboard/pcengines/alix1c/dts +++ b/mainboard/pcengines/alix1c/dts @@ -51,7 +51,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; ioport@2e { /config/("superio/winbond/w83627hf/dts"); diff --git a/mainboard/pcengines/alix2c3/dts b/mainboard/pcengines/alix2c3/dts index c1b4d31..30390b5 100644 --- a/mainboard/pcengines/alix2c3/dts +++ b/mainboard/pcengines/alix2c3/dts @@ -51,7 +51,6 @@ }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); - enable_ide = "1"; }; }; }; diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 0c5adb1..4374a0a 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -607,7 +607,7 @@ void chipsetinit(void) /** * Enables the IDE. This is code that is run if there is an ide device in the mainboard - * device tree and it has set non-zero "enable_ide". + * device tree. * * @param dev The device */ @@ -615,11 +615,6 @@ static void ide_init(struct device *dev) { u32 ide_cfg; - struct southbridge_amd_cs5536_ide_config *ide = - (struct southbridge_amd_cs5536_ide_config *)dev->device_configuration; - if (!ide->enable_ide) - return; - printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ diff --git a/southbridge/amd/cs5536/ide b/southbridge/amd/cs5536/ide index 42c9d5f..6cc8e2e 100644 --- a/southbridge/amd/cs5536/ide +++ b/southbridge/amd/cs5536/ide @@ -20,7 +20,4 @@ { device_operations = "cs5536_ide"; - - /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ - enable_ide = "0"; }; -- 1.6.0.4

3 3

domain vs device statictree order
by Marc Jones 09 Jan '09

09 Jan '09

Myles, Should the domain functions run before the device functions? It looks like the device functions run before the domain but I would expect it to be the other way. This is a problem for Geode LX. It has the VSA and graphics memory init in the domain phase2_fixup but it is running after the 5536 devices run phase2_fixup and is a problem. statictree: http://pastebin.ca/1301081 .next = &dev_domain_0 - is the link from the last pci device in the domain to the domain device. serial output: http://pastebin.ca/1301072 Marc

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coreboot January 2009