coreboot January 2009

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r3863 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 15 Jan '09

15 Jan '09

Author: stuge Date: 2009-01-15 03:21:27 +0100 (Thu, 15 Jan 2009) New Revision: 3863 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c Log: amdk8: This patch fixes ram init problems when using the 9W Sempron part. Trying to read the FIDVID register when the processor does not support FIDVID control causes a GP Fault. This patch reads the startup FID from a different MSR. I have verified this patch to work on the dbm690t platform. Signed-off-by: Dan Lykowski <lykowdk(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-01-15 02:13:18 UTC (rev 3862) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-01-15 02:21:27 UTC (rev 3863) @@ -1656,15 +1656,29 @@ /*15*/ 200, 160, 120, 100, }; - unsigned fid_cur; + int index; - msr_t msr; - msr = rdmsr(0xc0010042); - fid_cur = msr.lo & 0x3f; - index = fid_cur>>1; + /* Check for FID control support */ + struct cpuid_result cpuid1; + cpuid1 = cpuid(0x8000007); + if( cpuid1.edx & 0x02 ) { + /* Use current FID */ + unsigned fid_cur; + msr = rdmsr(0xc0010042); + fid_cur = msr.lo & 0x3f; + index = fid_cur>>1; + } else { + /* Use startup FID */ + unsigned fid_start; + msr = rdmsr(0xc0010015); + fid_start = (msr.lo & (0x3f << 24)); + + index = fid_start>>25; + } + if (index>12) return divisor; if (i>3) return divisor; Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2009-01-15 02:13:18 UTC (rev 3862) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2009-01-15 02:21:27 UTC (rev 3863) @@ -432,15 +432,28 @@ /*15*/ 5000, 4000, 3000, 2500, }; - unsigned fid_cur; int index; - msr_t msr; - msr = rdmsr(0xc0010042); - fid_cur = msr.lo & 0x3f; - index = fid_cur>>1; + /* Check for FID control support */ + struct cpuid_result cpuid1; + cpuid1 = cpuid(0x8000007); + if( cpuid1.edx & 0x02 ) { + /* Use current FID */ + unsigned fid_cur; + msr = rdmsr(0xc0010042); + fid_cur = msr.lo & 0x3f; + index = fid_cur>>1; + } else { + /* Use startup FID */ + unsigned fid_start; + msr = rdmsr(0xc0010015); + fid_start = (msr.lo & (0x3f << 24)); + + index = fid_start>>25; + } + if(index>12) return T1000_a[i]; return TT_a[index * 4+i];

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r3862 - trunk/util/flashrom
by svn＠coreboot.org 15 Jan '09

15 Jan '09

Author: stuge Date: 2009-01-15 03:13:18 +0100 (Thu, 15 Jan 2009) New Revision: 3862 Modified: trunk/util/flashrom/ichspi.c Log: flashrom: Add ICH opcode debugging. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2009-01-15 00:48:24 UTC (rev 3861) +++ trunk/util/flashrom/ichspi.c 2009-01-15 02:13:18 UTC (rev 3862) @@ -313,6 +313,7 @@ opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); } + printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); switch (flashbus) { case BUS_TYPE_ICH7_SPI: case BUS_TYPE_VIA_SPI:

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r3861 - trunk/util/flashrom
by svn＠coreboot.org 15 Jan '09

15 Jan '09

Author: hailfinger Date: 2009-01-15 01:48:24 +0100 (Thu, 15 Jan 2009) New Revision: 3861 Modified: trunk/util/flashrom/board_enable.c Log: Similarly to flashchips array, this patch intends to make the table board_pciid_enables more readable. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> > What real problem does this solve? 1. Next time someone adds a new struct member, we avoid mistakes of ordering of initializers 2. we avoid mistakes in the first place. The .x = y stuff was added for a (good) reason, I think this is an improvement. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2009-01-13 14:32:27 UTC (rev 3860) +++ trunk/util/flashrom/board_enable.c 2009-01-15 00:48:24 UTC (rev 3861) @@ -626,58 +626,369 @@ }; struct board_pciid_enable board_pciid_enables[] = { - {0x1106, 0x0571, 0x1462, 0x7120, 0x0000, 0x0000, 0x0000, 0x0000, - "msi", "kt4v", "MSI KT4V", board_msi_kt4v}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, - NULL, NULL, "ASUS P4B266", ich2_gpio22_raise}, - {0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash}, - {0x10de, 0x03e0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash}, - {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4385, 0x1458, 0x4385, - NULL, NULL, "GIGABYTE GA-MA78G-DS3H", it87xx_probe_spi_flash}, - {0x1039, 0x0761, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK", it87xx_probe_spi_flash}, - {0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e}, - {0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e}, - {0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000, - "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, - NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, - NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx}, - {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, - NULL, NULL, "VIA EPIA SP", board_via_epia_sp}, - {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, - NULL, NULL, "VIA EPIA-CN", board_via_epia_sp}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, - NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx}, - {0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000, - "asus", "p5a", "ASUS P5A", board_asus_p5a}, - {0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000, - "ibm", "x3455", "IBM x3455", board_ibm_x3455}, - {0x8086, 0x7110, 0x0000, 0x0000, 0x8086, 0x7190, 0x0000, 0x0000, - "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3}, - {0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33, - "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd}, - {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000, - "artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x}, - {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000, - "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x}, + { + .first_vendor = 0x1106, + .first_device = 0x0571, + .first_card_vendor = 0x1462, + .first_card_device = 0x7120, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "msi", + .lb_part = "kt4v", + .name = "MSI KT4V", + .enable = board_msi_kt4v, + }, + { + .first_vendor = 0x8086, + .first_device = 0x1a30, + .first_card_vendor = 0x1043, + .first_card_device = 0x8070, + .second_vendor = 0x8086, + .second_device = 0x244b, + .second_card_vendor = 0x1043, + .second_card_device = 0x8028, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "ASUS P4B266", + .enable = ich2_gpio22_raise, + }, + { + .first_vendor = 0x10de, + .first_device = 0x0360, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "gigabyte", + .lb_part = "m57sli", + .name = "GIGABYTE GA-M57SLI-S4", + .enable = it87xx_probe_spi_flash, + }, + { + .first_vendor = 0x10de, + .first_device = 0x03e0, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "gigabyte", + .lb_part = "m61p", + .name = "GIGABYTE GA-M61P-S3", + .enable = it87xx_probe_spi_flash, + }, + { + .first_vendor = 0x1002, + .first_device = 0x4398, + .first_card_vendor = 0x1458, + .first_card_device = 0x5004, + .second_vendor = 0x1002, + .second_device = 0x4385, + .second_card_vendor = 0x1458, + .second_card_device = 0x4385, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "GIGABYTE GA-MA78G-DS3H", + .enable = it87xx_probe_spi_flash, + }, + { + .first_vendor = 0x1039, + .first_device = 0x0761, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "gigabyte", + .lb_part = "2761gxdk", + .name = "GIGABYTE GA-2761GXDK", + .enable = it87xx_probe_spi_flash, + }, + { + .first_vendor = 0x1022, + .first_device = 0x7468, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "iwill", + .lb_part = "dk8_htx", + .name = "IWILL DK8-HTX", + .enable = w83627hf_gpio24_raise_2e, + }, + { + .first_vendor = 0x10de, + .first_device = 0x005e, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "msi", + .lb_part = "k8n-neo3", + .name = "MSI K8N Neo3", + .enable = w83627thf_gpio4_4_raise_4e, + }, + { + .first_vendor = 0x1022, + .first_device = 0x746B, + .first_card_vendor = 0x1022, + .first_card_device = 0x36C0, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "AGAMI", + .lb_part = "ARUMA", + .name = "agami Aruma", + .enable = w83627hf_gpio24_raise_2e, + }, + { + .first_vendor = 0x1106, + .first_device = 0x3177, + .first_card_vendor = 0x1106, + .first_card_device = 0xAA01, + .second_vendor = 0x1106, + .second_device = 0x3123, + .second_card_vendor = 0x1106, + .second_card_device = 0xAA01, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "VIA EPIA M/MII/...", + .enable = board_via_epia_m, + }, + { + .first_vendor = 0x1106, + .first_device = 0x3177, + .first_card_vendor = 0x1043, + .first_card_device = 0x80A1, + .second_vendor = 0x1106, + .second_device = 0x3205, + .second_card_vendor = 0x1043, + .second_card_device = 0x8118, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "ASUS A7V8-MX SE", + .enable = board_asus_a7v8x_mx, + }, + { + .first_vendor = 0x1106, + .first_device = 0x3227, + .first_card_vendor = 0x1106, + .first_card_device = 0xAA01, + .second_vendor = 0x1106, + .second_device = 0x0259, + .second_card_vendor = 0x1106, + .second_card_device = 0xAA01, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "VIA EPIA SP", + .enable = board_via_epia_sp, + }, + { + .first_vendor = 0x1106, + .first_device = 0x0314, + .first_card_vendor = 0x1106, + .first_card_device = 0xaa08, + .second_vendor = 0x1106, + .second_device = 0x3227, + .second_card_vendor = 0x1106, + .second_card_device = 0xAA08, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "VIA EPIA-CN", + .enable = board_via_epia_sp, + }, + { + .first_vendor = 0x8086, + .first_device = 0x1076, + .first_card_vendor = 0x8086, + .first_card_device = 0x1176, + .second_vendor = 0x1106, + .second_device = 0x3059, + .second_card_vendor = 0x10f1, + .second_card_device = 0x2498, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "Tyan Tomcat K7M", + .enable = board_asus_a7v8x_mx, + }, + { + .first_vendor = 0x10B9, + .first_device = 0x1541, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x10B9, + .second_device = 0x1533, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "asus", + .lb_part = "p5a", + .name = "ASUS P5A", + .enable = board_asus_p5a, + }, + { + .first_vendor = 0x1166, + .first_device = 0x0205, + .first_card_vendor = 0x1014, + .first_card_device = 0x0347, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "ibm", + .lb_part = "x3455", + .name = "IBM x3455", + .enable = board_ibm_x3455, + }, + { + .first_vendor = 0x8086, + .first_device = 0x7110, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x8086, + .second_device = 0x7190, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "epox", + .lb_part = "ep-bx3", + .name = "EPoX EP-BX3", + .enable = board_epox_ep_bx3, + }, + { + .first_vendor = 0x8086, + .first_device = 0x1130, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x105a, + .second_device = 0x0d30, + .second_card_vendor = 0x105a, + .second_card_device = 0x4d33, + .lb_vendor = "acorp", + .lb_part = "6a815epd", + .name = "Acorp 6A815EPD", + .enable = board_acorp_6a815epd, + }, + { + .first_vendor = 0x1022, + .first_device = 0x2090, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x1022, + .second_device = 0x2080, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "artecgroup", + .lb_part = "dbe61", + .name = "Artec Group DBE61", + .enable = board_artecgroup_dbe6x, + }, + { + .first_vendor = 0x1022, + .first_device = 0x2090, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x1022, + .second_device = 0x2080, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "artecgroup", + .lb_part = "dbe62", + .name = "Artec Group DBE62", + .enable = board_artecgroup_dbe6x, + }, /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */ - {0x8086, 0x27b8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m}, - {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, - "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, - NULL, NULL, "BioStar P4M80-M4", board_biostar_p4m80_m4}, - {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, - NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, - NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, - {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ + { + .first_vendor = 0x8086, + .first_device = 0x27b8, + .first_card_vendor = 0x0000, + .first_card_device = 0x0000, + .second_vendor = 0x0000, + .second_device = 0x0000, + .second_card_vendor = 0x0000, + .second_card_device = 0x0000, + .lb_vendor = "kontron", + .lb_part = "986lcd-m", + .name = "Kontron 986LCD-M", + .enable = board_kontron_986lcd_m, + }, + { + .first_vendor = 0x10ec, + .first_device = 0x8168, + .first_card_vendor = 0x10ec, + .first_card_device = 0x8168, + .second_vendor = 0x104c, + .second_device = 0x8023, + .second_card_vendor = 0x104c, + .second_card_device = 0x8019, + .lb_vendor = "kontron", + .lb_part = "986lcd-m", + .name = "Kontron 986LCD-M", + .enable = board_kontron_986lcd_m, + }, + { + .first_vendor = 0x1106, + .first_device = 0x3149, + .first_card_vendor = 0x1565, + .first_card_device = 0x3206, + .second_vendor = 0x1106, + .second_device = 0x3344, + .second_card_vendor = 0x1565, + .second_card_device = 0x1202, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "BioStar P4M80-M4", + .enable = board_biostar_p4m80_m4, + }, + { + .first_vendor = 0x1106, + .first_device = 0x3227, + .first_card_vendor = 0x1458, + .first_card_device = 0x5001, + .second_vendor = 0x10ec, + .second_device = 0x8139, + .second_card_vendor = 0x1458, + .second_card_device = 0xe000, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "GIGABYTE GA-7VT600", + .enable = board_biostar_p4m80_m4, + }, + { + .first_vendor = 0x1106, + .first_device = 0x3149, + .first_card_vendor = 0x1462, + .first_card_device = 0x7094, + .second_vendor = 0x10ec, + .second_device = 0x8167, + .second_card_vendor = 0x1462, + .second_card_device = 0x094c, + .lb_vendor = NULL, + .lb_part = NULL, + .name = "MSI K8T Neo2", + .enable = w83627thf_gpio4_4_raise_2e, + }, + { + .first_vendor = 0, + .first_device = 0, + .first_card_vendor = 0, + .first_card_device = 0, + .second_vendor = 0, + .second_device = 0, + .second_card_vendor = 0, + .second_card_device = 0, + .lb_vendor = NULL, + .lb_part = NULL, + } /* Keep this */ }; void print_supported_boards(void)

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r1115 - in coreboot-v3/mainboard/artecgroup: dbe61 dbe62
by svn＠coreboot.org 14 Jan '09

14 Jan '09

Author: mraudsepp Date: 2009-01-14 12:22:32 +0100 (Wed, 14 Jan 2009) New Revision: 1115 Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe62/initram.c Log: Remove redundant unused tRCD entries from dbe61/dbe62 SPD value list. SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative constant tRCD in the end has no effect in the memory algorithm - remove them. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2009-01-09 18:12:08 UTC (rev 1114) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2009-01-14 11:22:32 UTC (rev 1115) @@ -66,7 +66,6 @@ {SPD_REFRESH, 0x82}, {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, - {SPD_tRCD, 15}, }; /* Fake SPD for DBE61A - 128MB */ @@ -89,7 +88,6 @@ {SPD_REFRESH, 0x82}, {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, - {SPD_tRCD, 15}, }; /** Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2009-01-09 18:12:08 UTC (rev 1114) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2009-01-14 11:22:32 UTC (rev 1115) @@ -70,7 +70,6 @@ {SPD_REFRESH, 0x82}, {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, - {SPD_tRCD, 15}, }; /**

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[PATCH] Remove redundant unused tRCD entries from dbe61/dbe62 SPD value list.
by Mart Raudsepp 13 Jan '09

13 Jan '09

SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative constant tRCD in the end has no effect in the memory algorithm - remove them. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/initram.c | 2 -- mainboard/artecgroup/dbe62/initram.c | 1 - 2 files changed, 0 insertions(+), 3 deletions(-) diff --git a/mainboard/artecgroup/dbe61/initram.c b/mainboard/artecgroup/dbe61/initram.c index d8612de..4c16bdb 100644 --- a/mainboard/artecgroup/dbe61/initram.c +++ b/mainboard/artecgroup/dbe61/initram.c @@ -66,7 +66,6 @@ static const struct spd_entry spd_table_dbe61c[] = { {SPD_REFRESH, 0x82}, {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, - {SPD_tRCD, 15}, }; /* Fake SPD for DBE61A - 128MB */ @@ -89,7 +88,6 @@ static const struct spd_entry spd_table_dbe61a[] = { {SPD_REFRESH, 0x82}, {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, - {SPD_tRCD, 15}, }; /** diff --git a/mainboard/artecgroup/dbe62/initram.c b/mainboard/artecgroup/dbe62/initram.c index d3940fc..35e5b3f 100644 --- a/mainboard/artecgroup/dbe62/initram.c +++ b/mainboard/artecgroup/dbe62/initram.c @@ -70,7 +70,6 @@ static const struct spd_entry spd_table[] = { {SPD_REFRESH, 0x82}, {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, - {SPD_tRCD, 15}, }; /** -- 1.6.0.4

2 1

r3860 - trunk/util/flashrom
by svn＠coreboot.org 13 Jan '09

13 Jan '09

Author: stuge Date: 2009-01-13 15:32:27 +0100 (Tue, 13 Jan 2009) New Revision: 3860 Modified: trunk/util/flashrom/flashrom.c Log: flashrom: Always print address when verification fails, not only with -V. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2009-01-12 21:31:14 UTC (rev 3859) +++ trunk/util/flashrom/flashrom.c 2009-01-13 14:32:27 UTC (rev 3860) @@ -186,10 +186,11 @@ printf("0x%08x", idx); if (*(buf2 + idx) != *(buf + idx)) { - if (verbose) { - printf("0x%08x ", idx); - } - printf("FAILED! Expected=0x%02x, Read=0x%02x\n", + if (verbose) + printf("0x%08x FAILED!", idx); + else + printf("FAILED at 0x%08x!", idx); + printf(" Expected=0x%02x, Read=0x%02x\n", *(buf + idx), *(buf2 + idx)); return 1; }

1 0

v3 bug report: Error base address register of UART in vt1211
by JasonZhao＠viatech.com.cn 13 Jan '09

13 Jan '09

Hi Carl, I find a bug need to fix in superior/via/vt1211/Stage1.c rawpnp_set_iobase(dev, 2, (iobase >> 2) & 0xff); should be rawpnp_set_iobase(dev, 0x60, ((iobase >> 2) & 0xff)<<8); according the spec of VT1211. It seems that vt1211 only define the Rx60 for LOW address of UART base,and Rx61 is not used at all. However -jasonzhao

2 3

ASUS A7M-266D infos
by Uwe Hermann 12 Jan '09

12 Jan '09

Here's a dump provided by Sven Schnelle <svens(a)stackframe.org> for the ASUS A7M-266D (dual CPU) board with AMD-76x/AMD-780 chipset, for reference and archival purposes. There's some support in v1 for this, but as soon as the license patches I sent are committed, I'll probably have a try at porting all of this to v2 and adding support for the board. -[0000:00]-+-00.0 Advanced Micro Devices [AMD] AMD-760 MP [IGD4-2P] System Controller [1022:700c] +-01.0-[0000:01]-- +-07.0 Advanced Micro Devices [AMD] AMD-768 [Opus] ISA [1022:7440] +-07.1 Advanced Micro Devices [AMD] AMD-768 [Opus] IDE [1022:7441] +-07.3 Advanced Micro Devices [AMD] AMD-768 [Opus] ACPI [1022:7443] \-10.0-[0000:02]--+-00.0 Advanced Micro Devices [AMD] AMD-768 [Opus] USB [1022:7449] +-04.0 C-Media Electronics Inc CM8738 [13f6:0111] +-05.0 nVidia Corporation NV4 [RIVA TNT] [10de:0020] \-06.0 3Com Corporation 3c905 100BaseTX [Boomerang] [10b7:9050] ----------------------------------------------------------------------------------------------------- superiotool r3828 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x3f3f, rev=0x3f Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x80fe, id=0x5359 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x5953, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x3f3f, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x2222, rev=0x2 Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0x00, port+1=0x00 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0x22, rev=0x22 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0x22, rev=0x22 Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627SF (id=0x59, rev=0x53) at 0x2e No dump available for this Super I/O Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0x22/0x02, rev=0x22 Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0x22/0x02, rev=0x22 Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0x22/0x02, rev=0x22 Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0x22/0x02, rev=0x22 Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff ----------------------------------------------------------------------------------- /* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * * Contains the IRQ Routing Table dumped directly from your * memory, which BIOS sets up. * * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx */ #ifdef GETPIR #include "pirq_routing.h" #else #include <arch/pirq_routing.h> #endif const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*9, /* There can be total 9 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x1022, /* Vendor */ 0x7440, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x17, /* u8 checksum. This has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x07<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0}, {0x00,(0x08<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x00, 0x1eb8}}, 0x2, 0x0}, {0x02,(0x06<<3)|0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x00, 0x1eb8}}, 0x3, 0x0}, {0x02,(0x05<<3)|0x0, {{0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x00, 0x1eb8}, {0x01, 0x1eb8}}, 0x4, 0x0}, {0x02,(0x08<<3)|0x0, {{0x03, 0x1eb8}, {0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}}, 0x5, 0x0}, {0x01,(0x05<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0}, {0x02,(0x04<<3)|0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x00, 0x1eb8}}, 0x0, 0x0}, {0x02,(0x00<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); } -------------------------------------------------------------------------------------------- /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); /*Bus: Bus ID Type*/ smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "PCI "); smp_write_bus(mc, 3, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x3, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x14, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x2, 0x11); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x0, 0x2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x3, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x4, 0x2, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x5, 0x2, 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x6, 0x2, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x7, 0x2, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x8, 0x2, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x9, 0x2, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0xd, 0x2, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0xe, 0x2, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0xf, 0x2, 0xf); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); MP Config Extended Table Entries: -- System Address Space bus ID: 0 address type: I/O address address base: 0x0 address range: 0x10000 -- System Address Space bus ID: 0 address type: memory address address base: 0x10000000 address range: 0xe9f00000 -- System Address Space bus ID: 0 address type: prefetch address address base: 0xf9f00000 address range: 0x4d00000 -- System Address Space bus ID: 0 address type: memory address address base: 0xfec00000 address range: 0x1400000 -- System Address Space bus ID: 0 address type: memory address address base: 0xa0000 address range: 0x20000 -- Bus Heirarchy bus ID: 3 bus info: 0x01 parent bus ID: 0-- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x00000000-- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x00000001 /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

Re: [coreboot] SCALE
by Dan Lykowski 12 Jan '09

12 Jan '09

The manufacturer makes them in a number of form factors. In the form I have on hand, it plugs right in to a standard motherboard SATA slot without a cable. I have to connect an external +5V supply from the power supply. Dan Lykowski --- On Mon, 1/12/09, Tom Sylla <tsylla(a)gmail.com> wrote: From: Tom Sylla <tsylla(a)gmail.com> Subject: Re: [coreboot] SCALE To: "Dan Lykowski" <engineerguy3737(a)yahoo.com> Cc: "Peter Stuge" <peter(a)stuge.se>, coreboot(a)coreboot.org Date: Monday, January 12, 2009, 4:45 PM -----Inline Attachment Follows----- Do most normal motherboards supply +5V on pin 7 of their SATA connectors to make this work? Are you using them on an off-the-shelf motherboard? This looks like something intended for an embedded design, where you make your connector a non-standard pinout to support it. On Mon, Jan 12, 2009 at 4:03 PM, Dan Lykowski <engineerguy3737(a)yahoo.com> wrote: > I would suggest this part: > http://www.innodisk.com/flashstorage_specification.jsp?flashid=29 > They plug right in to the SATA port. > They have a minor quirk where you have to 'force.libata=1:1.5g' to get them > to work under Linux but that is the only negative I have run across so far. > > Dan Lykowski > > --- On Mon, 1/12/09, Peter Stuge <peter(a)stuge.se> wrote: > > From: Peter Stuge <peter(a)stuge.se> > Subject: Re: [coreboot] SCALE > To: coreboot(a)coreboot.org > Date: Monday, January 12, 2009, 2:55 PM > > > -----Inline Attachment Follows----- > > ron minnich wrote: >> I'd like to have the 5 second "boot to X" demo at the table. If >> somebody can help direct me to getting that set up, I'd appreciate >> it. > > If you don't want to cram everything into a 16Mbit flash chip, which > could be tight, you need some ATA flash to store apps on. > > Since the dbm690 has an LPC PLCC socket you can use the dongle and my > adapter plug though, that way you have 32Mbit which is already more > roomy. > > Maybe the dongle occupied for the ALIX already? > > > //Peter > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

1 0

We boot Windows XP, Windows Vista and Windows 7 (build 7000)
by Rudolf Marek 12 Jan '09

12 Jan '09

Hello, I'm pleased to announce that SeaBIOS and Coreboot can boot (and install) Windows 7 build 7000, which was released as public beta yesterday. There is also some video taken by mine Cannon G7 camera. http://media.avc-cvut.cz/avc_vlastni_tvorba/2009/ruik/w7-coreboot/ Test platform: Asus M2V-MX SE, 512MB RAM, AMD Sempron on 2GHz. Moreover I was able to boot/install there Windows Vista (Bussines, 64bit) and Windows XP. Most patches are in, there is just one missing which I indicated in the previous email, http://www.coreboot.org/pipermail/coreboot/2008-December/043493.html Kevin, can we sort this out? Rudolf

6 7

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coreboot January 2009