coreboot January 2009

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[PATCH] Refactor K8 rev F DDR2 CL timing retrieval
by Carl-Daniel Hailfinger 16 Jan '09

16 Jan '09

Refactor K8 rev F DDR2 CL timing retrieval. This will allow usage of compatible DIMMS in a dual channel setup instead of requiring the DIMMS to be identical. Code impact is minimal because a large chunk of code has been moved into a separate function with almost no changes. Tested, yields identical results and identical logs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Revision 3865) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Arbeitskopie) @@ -1702,6 +1702,93 @@ return value; } +static const uint8_t latency_indicies[] = { 25, 23, 9 }; + +int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) +{ + int new_cycle_time, new_latency; + int index; + int latencies; + int latency; + + /* First find the supported CAS latencies + * Byte 18 for DDR SDRAM is interpreted: + * bit 3 == CAS Latency = 3 + * bit 4 == CAS Latency = 4 + * bit 5 == CAS Latency = 5 + * bit 6 == CAS Latency = 6 + */ + new_cycle_time = 0x500; + new_latency = 6; + + latencies = spd_read_byte(spd_device, SPD_CAS_LAT); + if (latencies <= 0) + return 1; + + printk_raminit("\tlatencies: %08x\n", latencies); + /* Compute the lowest cas latency which can be expressed in this + * particular SPD EEPROM. You can store at most settings for 3 + * contiguous CAS latencies, so by taking the highest CAS + * latency maked as supported in the SPD and subtracting 2 you + * get the lowest expressable CAS latency. That latency is not + * necessarily supported, but a (maybe invalid) entry exists + * for it. + */ + latency = log2(latencies) - 2; + + /* Loop through and find a fast clock with a low latency */ + for (index = 0; index < 3; index++, latency++) { + int value; + if ((latency < 3) || (latency > 6) || + (!(latencies & (1 << latency)))) { + continue; + } + value = spd_read_byte(spd_device, latency_indicies[index]); + if (value < 0) { + return -1; + } + + printk_raminit("\tindex: %08x\n", index); + printk_raminit("\t\tlatency: %08x\n", latency); + printk_raminit("\t\tvalue1: %08x\n", value); + + value = convert_to_linear(value); + + printk_raminit("\t\tvalue2: %08x\n", value); + + /* Only increase the latency if we decrease the clock */ + if (value >= *min_cycle_time ) { + if (value < new_cycle_time) { + new_cycle_time = value; + new_latency = latency; + } else if (value == new_cycle_time) { + if (new_latency > latency) { + new_latency = latency; + } + } + } + printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); + printk_raminit("\t\tnew_latency: %08x\n", new_latency); + + } + + if (new_latency > 6){ + return 1; + } + + /* Does min_latency need to be increased? */ + if (new_cycle_time > *min_cycle_time) { + *min_cycle_time = new_cycle_time; + } + + /* Does min_cycle_time need to be increased? */ + if (new_latency > *min_latency) { + *min_latency = new_latency; + } + + return 0; +} + static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo) { /* Compute the minimum cycle time for these dimms */ @@ -1710,8 +1797,6 @@ int i; uint32_t value; - static const uint8_t latency_indicies[] = { 25, 23, 9 }; - static const uint16_t min_cycle_times[] = { // use full speed to compare [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */ [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */ @@ -1735,10 +1820,6 @@ * by both the memory controller and the dimms. */ for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; u32 spd_device = ctrl->channel0[i]; printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask); @@ -1750,81 +1831,16 @@ } } - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 3 == CAS Latency = 3 - * bit 4 == CAS Latency = 4 - * bit 5 == CAS Latency = 5 - * bit 6 == CAS Latency = 6 - */ - new_cycle_time = 0x500; - new_latency = 6; - - latencies = spd_read_byte(spd_device, SPD_CAS_LAT); - if (latencies <= 0) continue; - printk_raminit("i: %08x\n",i); - printk_raminit("\tlatencies: %08x\n", latencies); - /* Compute the lowest cas latency which can be expressed in this - * particular SPD EEPROM. You can store at most settings for 3 - * contiguous CAS latencies, so by taking the highest CAS - * latency maked as supported in the SPD and subtracting 2 you - * get the lowest expressable CAS latency. That latency is not - * necessarily supported, but a (maybe invalid) entry exists - * for it. - */ - latency = log2(latencies) - 2; - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int value; - if ((latency < 3) || (latency > 6) || - (!(latencies & (1 << latency)))) { - continue; - } - value = spd_read_byte(spd_device, latency_indicies[index]); - if (value < 0) { - goto hw_error; - } - - printk_raminit("\tindex: %08x\n", index); - printk_raminit("\t\tlatency: %08x\n", latency); - printk_raminit("\t\tvalue1: %08x\n", value); - - value = convert_to_linear(value); - - printk_raminit("\t\tvalue2: %08x\n", value); - - /* Only increase the latency if we decrease the clock */ - if (value >= min_cycle_time ) { - if (value < new_cycle_time) { - new_cycle_time = value; - new_latency = latency; - } else if (value == new_cycle_time) { - if (new_latency > latency) { - new_latency = latency; - } - } - } - printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); - printk_raminit("\t\tnew_latency: %08x\n", new_latency); - - } - - if (new_latency > 6){ + switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) { + case -1: + goto hw_error; + break; + case 1: continue; } - - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - + printk_raminit("2 min_cycle_time: %08x\n", min_cycle_time); printk_raminit("2 min_latency: %08x\n", min_latency); } -- http://www.hailfinger.org/ Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Revision 3865) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Arbeitskopie) @@ -1702,6 +1702,93 @@ return value; } +static const uint8_t latency_indicies[] = { 25, 23, 9 }; + +int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) +{ + int new_cycle_time, new_latency; + int index; + int latencies; + int latency; + + /* First find the supported CAS latencies + * Byte 18 for DDR SDRAM is interpreted: + * bit 3 == CAS Latency = 3 + * bit 4 == CAS Latency = 4 + * bit 5 == CAS Latency = 5 + * bit 6 == CAS Latency = 6 + */ + new_cycle_time = 0x500; + new_latency = 6; + + latencies = spd_read_byte(spd_device, SPD_CAS_LAT); + if (latencies <= 0) + return 1; + + printk_raminit("\tlatencies: %08x\n", latencies); + /* Compute the lowest cas latency which can be expressed in this + * particular SPD EEPROM. You can store at most settings for 3 + * contiguous CAS latencies, so by taking the highest CAS + * latency maked as supported in the SPD and subtracting 2 you + * get the lowest expressable CAS latency. That latency is not + * necessarily supported, but a (maybe invalid) entry exists + * for it. + */ + latency = log2(latencies) - 2; + + /* Loop through and find a fast clock with a low latency */ + for (index = 0; index < 3; index++, latency++) { + int value; + if ((latency < 3) || (latency > 6) || + (!(latencies & (1 << latency)))) { + continue; + } + value = spd_read_byte(spd_device, latency_indicies[index]); + if (value < 0) { + return -1; + } + + printk_raminit("\tindex: %08x\n", index); + printk_raminit("\t\tlatency: %08x\n", latency); + printk_raminit("\t\tvalue1: %08x\n", value); + + value = convert_to_linear(value); + + printk_raminit("\t\tvalue2: %08x\n", value); + + /* Only increase the latency if we decrease the clock */ + if (value >= *min_cycle_time ) { + if (value < new_cycle_time) { + new_cycle_time = value; + new_latency = latency; + } else if (value == new_cycle_time) { + if (new_latency > latency) { + new_latency = latency; + } + } + } + printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); + printk_raminit("\t\tnew_latency: %08x\n", new_latency); + + } + + if (new_latency > 6){ + return 1; + } + + /* Does min_latency need to be increased? */ + if (new_cycle_time > *min_cycle_time) { + *min_cycle_time = new_cycle_time; + } + + /* Does min_cycle_time need to be increased? */ + if (new_latency > *min_latency) { + *min_latency = new_latency; + } + + return 0; +} + static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo) { /* Compute the minimum cycle time for these dimms */ @@ -1710,8 +1797,6 @@ int i; uint32_t value; - static const uint8_t latency_indicies[] = { 25, 23, 9 }; - static const uint16_t min_cycle_times[] = { // use full speed to compare [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */ [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */ @@ -1735,10 +1820,6 @@ * by both the memory controller and the dimms. */ for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; u32 spd_device = ctrl->channel0[i]; printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask); @@ -1750,81 +1831,16 @@ } } - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 3 == CAS Latency = 3 - * bit 4 == CAS Latency = 4 - * bit 5 == CAS Latency = 5 - * bit 6 == CAS Latency = 6 - */ - new_cycle_time = 0x500; - new_latency = 6; - - latencies = spd_read_byte(spd_device, SPD_CAS_LAT); - if (latencies <= 0) continue; - printk_raminit("i: %08x\n",i); - printk_raminit("\tlatencies: %08x\n", latencies); - /* Compute the lowest cas latency which can be expressed in this - * particular SPD EEPROM. You can store at most settings for 3 - * contiguous CAS latencies, so by taking the highest CAS - * latency maked as supported in the SPD and subtracting 2 you - * get the lowest expressable CAS latency. That latency is not - * necessarily supported, but a (maybe invalid) entry exists - * for it. - */ - latency = log2(latencies) - 2; - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int value; - if ((latency < 3) || (latency > 6) || - (!(latencies & (1 << latency)))) { - continue; - } - value = spd_read_byte(spd_device, latency_indicies[index]); - if (value < 0) { - goto hw_error; - } - - printk_raminit("\tindex: %08x\n", index); - printk_raminit("\t\tlatency: %08x\n", latency); - printk_raminit("\t\tvalue1: %08x\n", value); - - value = convert_to_linear(value); - - printk_raminit("\t\tvalue2: %08x\n", value); - - /* Only increase the latency if we decrease the clock */ - if (value >= min_cycle_time ) { - if (value < new_cycle_time) { - new_cycle_time = value; - new_latency = latency; - } else if (value == new_cycle_time) { - if (new_latency > latency) { - new_latency = latency; - } - } - } - printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); - printk_raminit("\t\tnew_latency: %08x\n", new_latency); - - } - - if (new_latency > 6){ + switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) { + case -1: + goto hw_error; + break; + case 1: continue; } - - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - + printk_raminit("2 min_cycle_time: %08x\n", min_cycle_time); printk_raminit("2 min_latency: %08x\n", min_latency); }

2 2

r3866 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 16 Jan '09

16 Jan '09

Author: hailfinger Date: 2009-01-16 04:03:40 +0100 (Fri, 16 Jan 2009) New Revision: 3866 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c Log: Refactor K8 rev F DDR2 CL timing retrieval. This will allow usage of compatible DIMMS in a dual channel setup instead of requiring the DIMMS to be identical. Code impact is minimal because a large chunk of code has been moved into a separate function with almost no changes. Tested, yields identical results and identical logs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-01-16 00:19:17 UTC (rev 3865) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-01-16 03:03:40 UTC (rev 3866) @@ -1702,6 +1702,96 @@ return value; } +static const uint8_t latency_indicies[] = { 25, 23, 9 }; + +int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) +{ + int new_cycle_time, new_latency; + int index; + int latencies; + int latency; + + /* First find the supported CAS latencies + * Byte 18 for DDR SDRAM is interpreted: + * bit 3 == CAS Latency = 3 + * bit 4 == CAS Latency = 4 + * bit 5 == CAS Latency = 5 + * bit 6 == CAS Latency = 6 + */ + new_cycle_time = 0x500; + new_latency = 6; + + latencies = spd_read_byte(spd_device, SPD_CAS_LAT); + if (latencies <= 0) + return 1; + + printk_raminit("\tlatencies: %08x\n", latencies); + /* Compute the lowest cas latency which can be expressed in this + * particular SPD EEPROM. You can store at most settings for 3 + * contiguous CAS latencies, so by taking the highest CAS + * latency maked as supported in the SPD and subtracting 2 you + * get the lowest expressable CAS latency. That latency is not + * necessarily supported, but a (maybe invalid) entry exists + * for it. + */ + latency = log2(latencies) - 2; + + /* Loop through and find a fast clock with a low latency */ + for (index = 0; index < 3; index++, latency++) { + int value; + if ((latency < 3) || (latency > 6) || + (!(latencies & (1 << latency)))) { + continue; + } + value = spd_read_byte(spd_device, latency_indicies[index]); + if (value < 0) { + return -1; + } + + printk_raminit("\tindex: %08x\n", index); + printk_raminit("\t\tlatency: %08x\n", latency); + printk_raminit("\t\tvalue1: %08x\n", value); + + value = convert_to_linear(value); + + printk_raminit("\t\tvalue2: %08x\n", value); + + /* Only increase the latency if we decrease the clock */ + if (value >= *min_cycle_time ) { + if (value < new_cycle_time) { + new_cycle_time = value; + new_latency = latency; + } else if (value == new_cycle_time) { + if (new_latency > latency) { + new_latency = latency; + } + } + } + printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); + printk_raminit("\t\tnew_latency: %08x\n", new_latency); + + } + + if (new_latency > 6){ + return 1; + } + + /* Does min_latency need to be increased? */ + if (new_cycle_time > *min_cycle_time) { + *min_cycle_time = new_cycle_time; + } + + /* Does min_cycle_time need to be increased? */ + if (new_latency > *min_latency) { + *min_latency = new_latency; + } + + printk_raminit("2 min_cycle_time: %08x\n", *min_cycle_time); + printk_raminit("2 min_latency: %08x\n", *min_latency); + + return 0; +} + static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo) { /* Compute the minimum cycle time for these dimms */ @@ -1710,8 +1800,6 @@ int i; uint32_t value; - static const uint8_t latency_indicies[] = { 25, 23, 9 }; - static const uint16_t min_cycle_times[] = { // use full speed to compare [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */ [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */ @@ -1735,10 +1823,6 @@ * by both the memory controller and the dimms. */ for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; u32 spd_device = ctrl->channel0[i]; printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask); @@ -1750,83 +1834,15 @@ } } - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 3 == CAS Latency = 3 - * bit 4 == CAS Latency = 4 - * bit 5 == CAS Latency = 5 - * bit 6 == CAS Latency = 6 - */ - new_cycle_time = 0x500; - new_latency = 6; - - latencies = spd_read_byte(spd_device, SPD_CAS_LAT); - if (latencies <= 0) continue; - printk_raminit("i: %08x\n",i); - printk_raminit("\tlatencies: %08x\n", latencies); - /* Compute the lowest cas latency which can be expressed in this - * particular SPD EEPROM. You can store at most settings for 3 - * contiguous CAS latencies, so by taking the highest CAS - * latency maked as supported in the SPD and subtracting 2 you - * get the lowest expressable CAS latency. That latency is not - * necessarily supported, but a (maybe invalid) entry exists - * for it. - */ - latency = log2(latencies) - 2; - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int value; - if ((latency < 3) || (latency > 6) || - (!(latencies & (1 << latency)))) { - continue; - } - value = spd_read_byte(spd_device, latency_indicies[index]); - if (value < 0) { - goto hw_error; - } - - printk_raminit("\tindex: %08x\n", index); - printk_raminit("\t\tlatency: %08x\n", latency); - printk_raminit("\t\tvalue1: %08x\n", value); - - value = convert_to_linear(value); - - printk_raminit("\t\tvalue2: %08x\n", value); - - /* Only increase the latency if we decrease the clock */ - if (value >= min_cycle_time ) { - if (value < new_cycle_time) { - new_cycle_time = value; - new_latency = latency; - } else if (value == new_cycle_time) { - if (new_latency > latency) { - new_latency = latency; - } - } - } - printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); - printk_raminit("\t\tnew_latency: %08x\n", new_latency); - - } - - if (new_latency > 6){ + switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) { + case -1: + goto hw_error; + break; + case 1: continue; - } - - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - - printk_raminit("2 min_cycle_time: %08x\n", min_cycle_time); - printk_raminit("2 min_latency: %08x\n", min_latency); + } } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency.

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[PATCH] Convert print_* to printk_* in K8 RAM init
by Carl-Daniel Hailfinger 16 Jan '09

16 Jan '09

Since all K8 targets now have CONFIG_USE_PRINTK_IN_CAR enabled, using print_* in K8 RAM init does not make sense anymore. Convert almost all print_* to printk_*. This improves readability a lot and makes the code shorter. Add a warning about false negatives in the DIMM dual channel compatibility check. This needs to be implemented correctly. Fix a few typos. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Revision 3850) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Arbeitskopie) @@ -34,34 +34,20 @@ #define QRANK_DIMM_SUPPORT 0 #endif -static inline void print_raminit(const char *strval, uint32_t val) -{ #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%08x\r\n", strval, val); #else - print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); +#error This file needs CONFIG_USE_PRINTK_IN_CAR #endif -} -#define RAM_TIMING_DEBUG 0 +#define RAM_TIMING_DEBUG 1 -static inline void print_tx(const char *strval, uint32_t val) -{ #if RAM_TIMING_DEBUG == 1 - print_raminit(strval, val); +#define printk_raminit printk_debug +#else +#define printk_raminit(fmt, arg...) do {} while(0) #endif -} -static inline void print_t(const char *strval) -{ -#if RAM_TIMING_DEBUG == 1 - print_debug(strval); -#endif -} - - - #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 # error "CONFIG_LB_MEM_TOPK must be a power of 2" #endif @@ -713,9 +699,7 @@ } sysinfo->ctrl_present[ctrl->node_id] = 1; - print_spew("setting up CPU"); - print_spew_hex8(ctrl->node_id); - print_spew(" northbridge registers\r\n"); + printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { device_t dev; @@ -729,7 +713,7 @@ pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + printk_spew("done.\n"); } @@ -829,14 +813,14 @@ if (value <=4 ) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines if ( value != (sz->per_rank)) { - print_err("Bad RANK Size --\r\n"); + printk_err("Bad RANK Size --\n"); goto val_err; } goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz->per_rank = 0; @@ -1070,9 +1054,7 @@ } /* Report the amount of memory. */ - print_debug("RAM: 0x"); - print_debug_hex32(tom_k); - print_debug(" KB\r\n"); + printk_debug("RAM: 0x%08x kB\n", tom_k); msr_t msr; if (tom_k > (4*1024*1024)) { @@ -1202,7 +1184,7 @@ csbase += csbase_inc; } - print_debug("Interleaved\r\n"); + printk_debug("Interleaved\n"); /* Return the memory size in K */ return common_size << ((27-10) + bits); @@ -1306,7 +1288,7 @@ CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); } else { - print_debug("Interleaving disabled\r\n"); + printk_debug("Interleaving disabled\n"); tom_k = 0; } @@ -1325,9 +1307,7 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, struct mem_info *meminfo) { - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); + printk_debug("disabling dimm %02x\n", index); if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); @@ -1402,9 +1382,9 @@ #if 1 if (meminfo->is_registered) { - print_debug("Registered\r\n"); + printk_debug("Registered\n"); } else { - print_debug("Unbuffered\r\n"); + printk_debug("Unbuffered\n"); } #endif return meminfo->dimm_mask; @@ -1448,15 +1428,11 @@ 4, /* *Column addresses */ 5, /* *Number of DIMM Ranks */ 6, /* *Module Data Width*/ - 9, /* *Cycle time at highest CAS Latency CL=X */ 11, /* *DIMM Conf Type */ 13, /* *Pri SDRAM Width */ 17, /* *Logical Banks */ - 18, /* *Supported CAS Latencies */ 20, /* *DIMM Type Info */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 1) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 2) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1464,11 +1440,18 @@ 36, /* *Write recovery time (tWR) */ 37, /* *Internal write to read command delay (tRDP) */ 38, /* *Internal read to precharge commanfd delay (tRTP) */ +#warning Why is SPD address 41 checked twice? 41, /* *Extension of Byte 41 tRC and Byte 42 tRFC */ 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */ 42, /* *Minimum Auto Refresh Command Time(Trfc) */ +#warning The SPD addresses below need special treatment like in spd_set_memclk. Right now they cause many false negatives. + 18, /* *Supported CAS Latencies */ + 9, /* *Cycle time at highest CAS Latency CL=X */ + 23, /* *Cycle time at CAS Latency (CLX - 1) */ + 26, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; + u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ #if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 @@ -1497,6 +1480,14 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; + /* Abort if the chips don't support a common CAS latency. */ + common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18); + if (!common_cl) { + printk_debug("No common CAS latency supported\n"); + goto single_channel; + } else { + printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl); + } for (j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; @@ -1509,11 +1500,12 @@ return -1; } if (value0 != value1) { + printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr); goto single_channel; } } } - print_spew("Enabling dual channel memory\r\n"); + printk_spew("Enabling dual channel memory\n"); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */ @@ -1566,7 +1558,7 @@ static const struct mem_param speed[] = { { - .name = "200Mhz\r\n", + .name = "200Mhz\n", .cycle_time = 0x500, .divisor = 200, // how many 1/40ns per clock .dch_memclk = DCH_MemClkFreq_200MHz, //0 @@ -1578,7 +1570,7 @@ }, { - .name = "266Mhz\r\n", + .name = "266Mhz\n", .cycle_time = 0x375, .divisor = 150, //???? .dch_memclk = DCH_MemClkFreq_266MHz, //1 @@ -1589,7 +1581,7 @@ .DcqByPassMax = 4, }, { - .name = "333Mhz\r\n", + .name = "333Mhz\n", .cycle_time = 0x300, .divisor = 120, .dch_memclk = DCH_MemClkFreq_333MHz, //2 @@ -1601,7 +1593,7 @@ }, { - .name = "400Mhz\r\n", + .name = "400Mhz\n", .cycle_time = 0x250, .divisor = 100, .dch_memclk = DCH_MemClkFreq_400MHz,//3 @@ -1628,9 +1620,10 @@ if (!param->cycle_time) { die("min_cycle_time to low"); } - print_spew(param->name); #ifdef DRAM_MIN_CYCLE_TIME - print_debug(param->name); + printk_debug(param->name); +#else + printk_spew(param->name); #endif return param; } @@ -1722,7 +1715,7 @@ } min_latency = 3; - print_tx("1 min_cycle_time:", min_cycle_time); + printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time); /* Compute the least latency with the fastest clock supported * by both the memory controller and the dimms. @@ -1734,7 +1727,7 @@ int latency; u32 spd_device = ctrl->channel0[i]; - print_tx("1.1 dimm_mask:", meminfo->dimm_mask); + printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & (1 << i))) { if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */ spd_device = ctrl->channel1[i]; @@ -1756,8 +1749,8 @@ latencies = spd_read_byte(spd_device, SPD_CAS_LAT); if (latencies <= 0) continue; - print_tx("i:",i); - print_tx("\tlatencies:", latencies); + printk_raminit("i: %08x\n",i); + printk_raminit("\tlatencies: %08x\n", latencies); /* Compute the lowest cas latency supported */ latency = log2(latencies) - 2; @@ -1773,15 +1766,15 @@ goto hw_error; } - print_tx("\tindex:", index); - print_tx("\t\tlatency:", latency); - print_tx("\t\tvalue1:", value); + printk_raminit("\tindex: %08x\n", index); + printk_raminit("\t\tlatency: %08x\n", latency); + printk_raminit("\t\tvalue1: %08x\n", value); value = convert_to_linear(value); - print_tx("\t\tvalue2:", value); + printk_raminit("\t\tvalue2: %08x\n", value); - /* Only increase the latency if we decreas the clock */ + /* Only increase the latency if we decrease the clock */ if (value >= min_cycle_time ) { if (value < new_cycle_time) { new_cycle_time = value; @@ -1792,8 +1785,8 @@ } } } - print_tx("\t\tnew_cycle_time:", new_cycle_time); - print_tx("\t\tnew_latency:", new_latency); + printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); + printk_raminit("\t\tnew_latency: %08x\n", new_latency); } @@ -1811,15 +1804,15 @@ min_latency = new_latency; } - print_tx("2 min_cycle_time:", min_cycle_time); - print_tx("2 min_latency:", min_latency); + printk_raminit("2 min_cycle_time: %08x\n", min_cycle_time); + printk_raminit("2 min_latency: %08x\n", min_latency); } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. */ - print_tx("3 min_cycle_time:", min_cycle_time); - print_tx("3 min_latency:", min_latency); + printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time); + printk_raminit("3 min_latency: %08x\n", min_latency); for (i = 0; (i < DIMM_SOCKETS); i++) { int latencies; @@ -1874,7 +1867,7 @@ meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo); } - print_tx("4 min_cycle_time:", min_cycle_time); + printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time); /* Now that I know the minimum cycle time lookup the memory parameters */ result.param = get_mem_param(min_cycle_time); @@ -1886,7 +1879,7 @@ value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); - print_debug(result.param->name); + printk_debug(result.param->name); /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); @@ -2054,16 +2047,16 @@ value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns if (value < 0) return -1; - print_tx("update_dimm_Tras: 0 value=", value); + printk_raminit("update_dimm_Tras: 0 value= %08x\n", value); value <<= 2; //convert it to in 1/4ns value *= 10; - print_tx("update_dimm_Tras: 1 value=", value); + printk_raminit("update_dimm_Tras: 1 value= %08x\n", value); clocks = (value + param->divisor - 1)/param->divisor; - print_tx("update_dimm_Tras: divisor=", param->divisor); - print_tx("update_dimm_Tras: clocks=", clocks); + printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor); + printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks); if (clocks < DTL_TRAS_MIN) { clocks = DTL_TRAS_MIN; } @@ -2366,8 +2359,8 @@ uint32_t reg; if ((val < TT_MIN) || (val > TT_MAX)) { - print_err(str); - die(" Unknown\r\n"); + printk_err(str); + die(" Unknown\n"); } reg = pci_read_config32(ctrl->f2, TT_REG); @@ -2610,12 +2603,12 @@ break; } - print_raminit("\tdimm_mask = ", meminfo->dimm_mask); - print_raminit("\tx4_mask = ", meminfo->x4_mask); - print_raminit("\tx16_mask = ", meminfo->x16_mask); - print_raminit("\tsingle_rank_mask = ", meminfo->single_rank_mask); - print_raminit("\tODC = ", dword); - print_raminit("\tAddr Timing= ", dwordx); + printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask); + printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask); + printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask); + printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask); + printk_raminit("\tODC = %08x\n", dword); + printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif #if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ @@ -2697,37 +2690,37 @@ !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) { continue; } - print_tx("spd_set_dram_timing dimm socket: ", i); + printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i); /* DRAM Timing Low Register */ - print_t("\ttrc\r\n"); + printk_raminit("\ttrc\n"); if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrcd\r\n"); + printk_raminit("\ttrcd\n"); if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrrd\r\n"); + printk_raminit("\ttrrd\n"); if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttras\r\n"); + printk_raminit("\ttras\n"); if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrp\r\n"); + printk_raminit("\ttrp\n"); if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrtp\r\n"); + printk_raminit("\ttrtp\n"); if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err; - print_t("\ttwr\r\n"); + printk_raminit("\ttwr\n"); if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; /* DRAM Timing High Register */ - print_t("\ttref\r\n"); + printk_raminit("\ttref\n"); if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttwtr\r\n"); + printk_raminit("\ttwtr\n"); if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrfc\r\n"); + printk_raminit("\ttrfc\n"); if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err; /* DRAM Config Low */ @@ -2784,37 +2777,37 @@ #endif meminfo = &sysinfo->meminfo[ctrl->node_id]; - print_debug_addr("sdram_set_spd_registers: paramx :", &paramx); + printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx); activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl); - print_tx("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { - print_debug("No memory for this cpu\r\n"); + printk_debug("No memory for this cpu\n"); return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); - print_tx("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo); - print_tx("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo); - print_tx("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; result = spd_set_memclk(ctrl, meminfo); param = result.param; meminfo->dimm_mask = result.dimm_mask; - print_tx("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2826,7 +2819,7 @@ paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor); meminfo->dimm_mask = spd_set_dram_timing(ctrl, &paramx, meminfo); - print_tx("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2961,13 +2954,13 @@ /* FIXME: How about 32 node machine later? */ tsc_t tsc, tsc0[8]; - print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]); + printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]); #endif uint32_t dword; /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { - die("No memory\r\n"); + die("No memory\n"); } /* Before enabling memory start the memory clocks */ @@ -2993,12 +2986,12 @@ /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */ memreset(controllers, ctrl); #if 0 - print_debug("prepare to InitDram:"); + printk_debug("prepare to InitDram:"); for (i=0; i<10; i++) { - print_debug_hex32(i); + printk_debug("%08x", i); print_debug("\b\b\b\b\b\b\b\b"); } - print_debug("\r\n"); + printk_debug("\n"); #endif for (i = 0; i < controllers; i++) { @@ -3015,7 +3008,7 @@ dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { uint32_t mnc; - print_spew("ECC enabled\r\n"); + printk_spew("ECC enabled\n"); mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_Width128) { @@ -3057,17 +3050,17 @@ /* Skip everything if I don't have any memory on this controller */ if (sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("Initializing memory: "); + printk_debug("Initializing memory: "); int loops = 0; do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops++; if ((loops & 1023) == 0) { - print_debug("."); + printk_debug("."); } } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { - print_debug(" failed\r\n"); + printk_debug(" failed\n"); continue; } @@ -3080,7 +3073,7 @@ if (cpu_f0_f1[i]) { tsc= rdtsc(); - print_debug_dqs_tsc("\r\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); + print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2); if (tsc.lo<tsc0[i].lo) { @@ -3095,7 +3088,7 @@ print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2); } #endif - print_debug(" done\r\n"); + printk_debug(" done\n"); } #if HW_MEM_HOLE_SIZEK != 0 Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f_dqs.c (Revision 3850) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f_dqs.c (Arbeitskopie) @@ -21,15 +21,16 @@ //0: mean no debug info #define DQS_TRAIN_DEBUG 0 +#if CONFIG_USE_PRINTK_IN_CAR +#else +#error This file needs CONFIG_USE_PRINTK_IN_CAR +#endif + static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x\r\n", str, val); - #else - print_debug(str); print_debug_hex32(val); print_debug("\r\n"); - #endif } #endif } @@ -38,11 +39,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); - #else - print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); - #endif } #endif } @@ -51,22 +48,14 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif } @@ -855,11 +844,7 @@ #if MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ - #if CONFIG_USE_PRINTK_IN_CAR - printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay); - #else - print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); - #endif + printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif return (CTLRMaxDelay==0xae)?1:0; @@ -1135,7 +1120,7 @@ print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3); - print_debug_addr("TrainDQSPos: MutualCSPassW[48] :", MutualCSPassW); + printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); for(DQSDelay=0; DQSDelay<48; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) @@ -1408,7 +1393,7 @@ print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); - print_debug_addr("TrainDQSRdWrPos: buf_a:", buf_a); + printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a); Errors = 0; channel = 0; @@ -1542,7 +1527,7 @@ { print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); + printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); return 1; } else { @@ -1705,19 +1690,11 @@ } sizek = 1 << align; #if MEM_TRAIN_SEQ != 1 - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); - #else - print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); - print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); - print_debug( (type==MTRR_TYPE_UNCACHEABLE)?"UC\r\n": - ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n") - ); - #endif #endif set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; @@ -1866,10 +1843,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass1: "); - print_debug_hex8(i); + printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); } tsc[1] = rdtsc(); @@ -1885,10 +1861,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:DQSPos: "); - print_debug_hex8(i); + printk_debug("DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); } tsc[3] = rdtsc(); @@ -1899,10 +1874,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass2: "); - print_debug_hex8(i); + printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); sysinfo->mem_trained[i]=1; } @@ -1943,8 +1917,7 @@ if(v) { tsc[0] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass1: "); - print_debug_hex8(i); + printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // @@ -1952,10 +1925,9 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[1] = rdtsc(); - print_debug("set DQS timing:DQSPos: "); - print_debug_hex8(i); + printk_debug("set DQS timing:DQSPos: %02x\n", i); } if(train_DqsPos(ctrl, sysinfo)) { @@ -1964,11 +1936,10 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[2] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass2: "); - print_debug_hex8(i); + printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // @@ -1976,7 +1947,7 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[3] = rdtsc(); } @@ -2027,7 +1998,7 @@ #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 - print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n"); + printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); #else /* Can copy dqs_timing to ap cache and run from cache? -- http://www.hailfinger.org/ Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Revision 3850) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Arbeitskopie) @@ -34,34 +34,20 @@ #define QRANK_DIMM_SUPPORT 0 #endif -static inline void print_raminit(const char *strval, uint32_t val) -{ #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%08x\r\n", strval, val); #else - print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); +#error This file needs CONFIG_USE_PRINTK_IN_CAR #endif -} -#define RAM_TIMING_DEBUG 0 +#define RAM_TIMING_DEBUG 1 -static inline void print_tx(const char *strval, uint32_t val) -{ #if RAM_TIMING_DEBUG == 1 - print_raminit(strval, val); +#define printk_raminit printk_debug +#else +#define printk_raminit(fmt, arg...) do {} while(0) #endif -} -static inline void print_t(const char *strval) -{ -#if RAM_TIMING_DEBUG == 1 - print_debug(strval); -#endif -} - - - #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 # error "CONFIG_LB_MEM_TOPK must be a power of 2" #endif @@ -713,9 +699,7 @@ } sysinfo->ctrl_present[ctrl->node_id] = 1; - print_spew("setting up CPU"); - print_spew_hex8(ctrl->node_id); - print_spew(" northbridge registers\r\n"); + printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { device_t dev; @@ -729,7 +713,7 @@ pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + printk_spew("done.\n"); } @@ -829,14 +813,14 @@ if (value <=4 ) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines if ( value != (sz->per_rank)) { - print_err("Bad RANK Size --\r\n"); + printk_err("Bad RANK Size --\n"); goto val_err; } goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz->per_rank = 0; @@ -1070,9 +1054,7 @@ } /* Report the amount of memory. */ - print_debug("RAM: 0x"); - print_debug_hex32(tom_k); - print_debug(" KB\r\n"); + printk_debug("RAM: 0x%08x kB\n", tom_k); msr_t msr; if (tom_k > (4*1024*1024)) { @@ -1202,7 +1184,7 @@ csbase += csbase_inc; } - print_debug("Interleaved\r\n"); + printk_debug("Interleaved\n"); /* Return the memory size in K */ return common_size << ((27-10) + bits); @@ -1306,7 +1288,7 @@ CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); } else { - print_debug("Interleaving disabled\r\n"); + printk_debug("Interleaving disabled\n"); tom_k = 0; } @@ -1325,9 +1307,7 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, struct mem_info *meminfo) { - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); + printk_debug("disabling dimm %02x\n", index); if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); @@ -1402,9 +1382,9 @@ #if 1 if (meminfo->is_registered) { - print_debug("Registered\r\n"); + printk_debug("Registered\n"); } else { - print_debug("Unbuffered\r\n"); + printk_debug("Unbuffered\n"); } #endif return meminfo->dimm_mask; @@ -1448,15 +1428,11 @@ 4, /* *Column addresses */ 5, /* *Number of DIMM Ranks */ 6, /* *Module Data Width*/ - 9, /* *Cycle time at highest CAS Latency CL=X */ 11, /* *DIMM Conf Type */ 13, /* *Pri SDRAM Width */ 17, /* *Logical Banks */ - 18, /* *Supported CAS Latencies */ 20, /* *DIMM Type Info */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 1) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 2) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1464,11 +1440,18 @@ 36, /* *Write recovery time (tWR) */ 37, /* *Internal write to read command delay (tRDP) */ 38, /* *Internal read to precharge commanfd delay (tRTP) */ +#warning Why is SPD address 41 checked twice? 41, /* *Extension of Byte 41 tRC and Byte 42 tRFC */ 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */ 42, /* *Minimum Auto Refresh Command Time(Trfc) */ +#warning The SPD addresses below need special treatment like in spd_set_memclk. Right now they cause many false negatives. + 18, /* *Supported CAS Latencies */ + 9, /* *Cycle time at highest CAS Latency CL=X */ + 23, /* *Cycle time at CAS Latency (CLX - 1) */ + 26, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; + u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ #if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 @@ -1497,6 +1480,14 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; + /* Abort if the chips don't support a common CAS latency. */ + common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18); + if (!common_cl) { + printk_debug("No common CAS latency supported\n"); + goto single_channel; + } else { + printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl); + } for (j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; @@ -1509,11 +1500,12 @@ return -1; } if (value0 != value1) { + printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr); goto single_channel; } } } - print_spew("Enabling dual channel memory\r\n"); + printk_spew("Enabling dual channel memory\n"); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */ @@ -1566,7 +1558,7 @@ static const struct mem_param speed[] = { { - .name = "200Mhz\r\n", + .name = "200Mhz\n", .cycle_time = 0x500, .divisor = 200, // how many 1/40ns per clock .dch_memclk = DCH_MemClkFreq_200MHz, //0 @@ -1578,7 +1570,7 @@ }, { - .name = "266Mhz\r\n", + .name = "266Mhz\n", .cycle_time = 0x375, .divisor = 150, //???? .dch_memclk = DCH_MemClkFreq_266MHz, //1 @@ -1589,7 +1581,7 @@ .DcqByPassMax = 4, }, { - .name = "333Mhz\r\n", + .name = "333Mhz\n", .cycle_time = 0x300, .divisor = 120, .dch_memclk = DCH_MemClkFreq_333MHz, //2 @@ -1601,7 +1593,7 @@ }, { - .name = "400Mhz\r\n", + .name = "400Mhz\n", .cycle_time = 0x250, .divisor = 100, .dch_memclk = DCH_MemClkFreq_400MHz,//3 @@ -1628,9 +1620,10 @@ if (!param->cycle_time) { die("min_cycle_time to low"); } - print_spew(param->name); #ifdef DRAM_MIN_CYCLE_TIME - print_debug(param->name); + printk_debug(param->name); +#else + printk_spew(param->name); #endif return param; } @@ -1722,7 +1715,7 @@ } min_latency = 3; - print_tx("1 min_cycle_time:", min_cycle_time); + printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time); /* Compute the least latency with the fastest clock supported * by both the memory controller and the dimms. @@ -1734,7 +1727,7 @@ int latency; u32 spd_device = ctrl->channel0[i]; - print_tx("1.1 dimm_mask:", meminfo->dimm_mask); + printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & (1 << i))) { if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */ spd_device = ctrl->channel1[i]; @@ -1756,8 +1749,8 @@ latencies = spd_read_byte(spd_device, SPD_CAS_LAT); if (latencies <= 0) continue; - print_tx("i:",i); - print_tx("\tlatencies:", latencies); + printk_raminit("i: %08x\n",i); + printk_raminit("\tlatencies: %08x\n", latencies); /* Compute the lowest cas latency supported */ latency = log2(latencies) - 2; @@ -1773,15 +1766,15 @@ goto hw_error; } - print_tx("\tindex:", index); - print_tx("\t\tlatency:", latency); - print_tx("\t\tvalue1:", value); + printk_raminit("\tindex: %08x\n", index); + printk_raminit("\t\tlatency: %08x\n", latency); + printk_raminit("\t\tvalue1: %08x\n", value); value = convert_to_linear(value); - print_tx("\t\tvalue2:", value); + printk_raminit("\t\tvalue2: %08x\n", value); - /* Only increase the latency if we decreas the clock */ + /* Only increase the latency if we decrease the clock */ if (value >= min_cycle_time ) { if (value < new_cycle_time) { new_cycle_time = value; @@ -1792,8 +1785,8 @@ } } } - print_tx("\t\tnew_cycle_time:", new_cycle_time); - print_tx("\t\tnew_latency:", new_latency); + printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); + printk_raminit("\t\tnew_latency: %08x\n", new_latency); } @@ -1811,15 +1804,15 @@ min_latency = new_latency; } - print_tx("2 min_cycle_time:", min_cycle_time); - print_tx("2 min_latency:", min_latency); + printk_raminit("2 min_cycle_time: %08x\n", min_cycle_time); + printk_raminit("2 min_latency: %08x\n", min_latency); } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. */ - print_tx("3 min_cycle_time:", min_cycle_time); - print_tx("3 min_latency:", min_latency); + printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time); + printk_raminit("3 min_latency: %08x\n", min_latency); for (i = 0; (i < DIMM_SOCKETS); i++) { int latencies; @@ -1874,7 +1867,7 @@ meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo); } - print_tx("4 min_cycle_time:", min_cycle_time); + printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time); /* Now that I know the minimum cycle time lookup the memory parameters */ result.param = get_mem_param(min_cycle_time); @@ -1886,7 +1879,7 @@ value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); - print_debug(result.param->name); + printk_debug(result.param->name); /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); @@ -2054,16 +2047,16 @@ value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns if (value < 0) return -1; - print_tx("update_dimm_Tras: 0 value=", value); + printk_raminit("update_dimm_Tras: 0 value= %08x\n", value); value <<= 2; //convert it to in 1/4ns value *= 10; - print_tx("update_dimm_Tras: 1 value=", value); + printk_raminit("update_dimm_Tras: 1 value= %08x\n", value); clocks = (value + param->divisor - 1)/param->divisor; - print_tx("update_dimm_Tras: divisor=", param->divisor); - print_tx("update_dimm_Tras: clocks=", clocks); + printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor); + printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks); if (clocks < DTL_TRAS_MIN) { clocks = DTL_TRAS_MIN; } @@ -2366,8 +2359,8 @@ uint32_t reg; if ((val < TT_MIN) || (val > TT_MAX)) { - print_err(str); - die(" Unknown\r\n"); + printk_err(str); + die(" Unknown\n"); } reg = pci_read_config32(ctrl->f2, TT_REG); @@ -2610,12 +2603,12 @@ break; } - print_raminit("\tdimm_mask = ", meminfo->dimm_mask); - print_raminit("\tx4_mask = ", meminfo->x4_mask); - print_raminit("\tx16_mask = ", meminfo->x16_mask); - print_raminit("\tsingle_rank_mask = ", meminfo->single_rank_mask); - print_raminit("\tODC = ", dword); - print_raminit("\tAddr Timing= ", dwordx); + printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask); + printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask); + printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask); + printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask); + printk_raminit("\tODC = %08x\n", dword); + printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif #if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ @@ -2697,37 +2690,37 @@ !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) { continue; } - print_tx("spd_set_dram_timing dimm socket: ", i); + printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i); /* DRAM Timing Low Register */ - print_t("\ttrc\r\n"); + printk_raminit("\ttrc\n"); if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrcd\r\n"); + printk_raminit("\ttrcd\n"); if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrrd\r\n"); + printk_raminit("\ttrrd\n"); if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttras\r\n"); + printk_raminit("\ttras\n"); if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrp\r\n"); + printk_raminit("\ttrp\n"); if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrtp\r\n"); + printk_raminit("\ttrtp\n"); if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err; - print_t("\ttwr\r\n"); + printk_raminit("\ttwr\n"); if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; /* DRAM Timing High Register */ - print_t("\ttref\r\n"); + printk_raminit("\ttref\n"); if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttwtr\r\n"); + printk_raminit("\ttwtr\n"); if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrfc\r\n"); + printk_raminit("\ttrfc\n"); if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err; /* DRAM Config Low */ @@ -2784,37 +2777,37 @@ #endif meminfo = &sysinfo->meminfo[ctrl->node_id]; - print_debug_addr("sdram_set_spd_registers: paramx :", &paramx); + printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx); activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl); - print_tx("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { - print_debug("No memory for this cpu\r\n"); + printk_debug("No memory for this cpu\n"); return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); - print_tx("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo); - print_tx("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo); - print_tx("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; result = spd_set_memclk(ctrl, meminfo); param = result.param; meminfo->dimm_mask = result.dimm_mask; - print_tx("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2826,7 +2819,7 @@ paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor); meminfo->dimm_mask = spd_set_dram_timing(ctrl, &paramx, meminfo); - print_tx("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2961,13 +2954,13 @@ /* FIXME: How about 32 node machine later? */ tsc_t tsc, tsc0[8]; - print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]); + printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]); #endif uint32_t dword; /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { - die("No memory\r\n"); + die("No memory\n"); } /* Before enabling memory start the memory clocks */ @@ -2993,12 +2986,12 @@ /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */ memreset(controllers, ctrl); #if 0 - print_debug("prepare to InitDram:"); + printk_debug("prepare to InitDram:"); for (i=0; i<10; i++) { - print_debug_hex32(i); + printk_debug("%08x", i); print_debug("\b\b\b\b\b\b\b\b"); } - print_debug("\r\n"); + printk_debug("\n"); #endif for (i = 0; i < controllers; i++) { @@ -3015,7 +3008,7 @@ dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { uint32_t mnc; - print_spew("ECC enabled\r\n"); + printk_spew("ECC enabled\n"); mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_Width128) { @@ -3057,17 +3050,17 @@ /* Skip everything if I don't have any memory on this controller */ if (sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("Initializing memory: "); + printk_debug("Initializing memory: "); int loops = 0; do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops++; if ((loops & 1023) == 0) { - print_debug("."); + printk_debug("."); } } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { - print_debug(" failed\r\n"); + printk_debug(" failed\n"); continue; } @@ -3080,7 +3073,7 @@ if (cpu_f0_f1[i]) { tsc= rdtsc(); - print_debug_dqs_tsc("\r\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); + print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2); if (tsc.lo<tsc0[i].lo) { @@ -3095,7 +3088,7 @@ print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2); } #endif - print_debug(" done\r\n"); + printk_debug(" done\n"); } #if HW_MEM_HOLE_SIZEK != 0 Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f_dqs.c (Revision 3850) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f_dqs.c (Arbeitskopie) @@ -21,15 +21,16 @@ //0: mean no debug info #define DQS_TRAIN_DEBUG 0 +#if CONFIG_USE_PRINTK_IN_CAR +#else +#error This file needs CONFIG_USE_PRINTK_IN_CAR +#endif + static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x\r\n", str, val); - #else - print_debug(str); print_debug_hex32(val); print_debug("\r\n"); - #endif } #endif } @@ -38,11 +39,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); - #else - print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); - #endif } #endif } @@ -51,22 +48,14 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif } @@ -855,11 +844,7 @@ #if MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ - #if CONFIG_USE_PRINTK_IN_CAR - printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay); - #else - print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); - #endif + printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif return (CTLRMaxDelay==0xae)?1:0; @@ -1135,7 +1120,7 @@ print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3); - print_debug_addr("TrainDQSPos: MutualCSPassW[48] :", MutualCSPassW); + printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); for(DQSDelay=0; DQSDelay<48; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) @@ -1408,7 +1393,7 @@ print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); - print_debug_addr("TrainDQSRdWrPos: buf_a:", buf_a); + printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a); Errors = 0; channel = 0; @@ -1542,7 +1527,7 @@ { print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); + printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); return 1; } else { @@ -1705,19 +1690,11 @@ } sizek = 1 << align; #if MEM_TRAIN_SEQ != 1 - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); - #else - print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); - print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); - print_debug( (type==MTRR_TYPE_UNCACHEABLE)?"UC\r\n": - ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n") - ); - #endif #endif set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; @@ -1866,10 +1843,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass1: "); - print_debug_hex8(i); + printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); } tsc[1] = rdtsc(); @@ -1885,10 +1861,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:DQSPos: "); - print_debug_hex8(i); + printk_debug("DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); } tsc[3] = rdtsc(); @@ -1899,10 +1874,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass2: "); - print_debug_hex8(i); + printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); sysinfo->mem_trained[i]=1; } @@ -1943,8 +1917,7 @@ if(v) { tsc[0] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass1: "); - print_debug_hex8(i); + printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // @@ -1952,10 +1925,9 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[1] = rdtsc(); - print_debug("set DQS timing:DQSPos: "); - print_debug_hex8(i); + printk_debug("set DQS timing:DQSPos: %02x\n", i); } if(train_DqsPos(ctrl, sysinfo)) { @@ -1964,11 +1936,10 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[2] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass2: "); - print_debug_hex8(i); + printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // @@ -1976,7 +1947,7 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[3] = rdtsc(); } @@ -2027,7 +1998,7 @@ #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 - print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n"); + printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); #else /* Can copy dqs_timing to ap cache and run from cache?

3 5

r3865 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 16 Jan '09

16 Jan '09

Author: hailfinger Date: 2009-01-16 01:19:17 +0100 (Fri, 16 Jan 2009) New Revision: 3865 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c Log: Since all K8 targets now have CONFIG_USE_PRINTK_IN_CAR enabled, using print_* in K8 RAM init does not make sense anymore. Convert almost all print_* to printk_*. This improves readability a lot and makes the code shorter. Reorder the SPD equality checks in the dual channel DIMM compatibility checking code. This is to make sure that we know if any other mismatches are present in the DIMM. The new order eases debugging with the old code. Add a comment about false negatives in that code. This needs to be implemented correctly, but that is hard to do in an efficient way. Check if the DIMMS in a dual channel setup have any compatible CAS latencies. Add better comments to explain why wrong-at-first-glance SPD CL walking code is actually correct. Fix a few typos. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-01-15 02:35:30 UTC (rev 3864) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-01-16 00:19:17 UTC (rev 3865) @@ -34,34 +34,20 @@ #define QRANK_DIMM_SUPPORT 0 #endif -static inline void print_raminit(const char *strval, uint32_t val) -{ #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%08x\r\n", strval, val); #else - print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); +#error This file needs CONFIG_USE_PRINTK_IN_CAR #endif -} #define RAM_TIMING_DEBUG 0 -static inline void print_tx(const char *strval, uint32_t val) -{ #if RAM_TIMING_DEBUG == 1 - print_raminit(strval, val); +#define printk_raminit printk_debug +#else +#define printk_raminit(fmt, arg...) #endif -} -static inline void print_t(const char *strval) -{ -#if RAM_TIMING_DEBUG == 1 - print_debug(strval); -#endif -} - - - #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 # error "CONFIG_LB_MEM_TOPK must be a power of 2" #endif @@ -713,9 +699,7 @@ } sysinfo->ctrl_present[ctrl->node_id] = 1; - print_spew("setting up CPU"); - print_spew_hex8(ctrl->node_id); - print_spew(" northbridge registers\r\n"); + printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { device_t dev; @@ -729,7 +713,7 @@ pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + printk_spew("done.\n"); } @@ -829,14 +813,14 @@ if (value <=4 ) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines if ( value != (sz->per_rank)) { - print_err("Bad RANK Size --\r\n"); + printk_err("Bad RANK Size --\n"); goto val_err; } goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz->per_rank = 0; @@ -1070,9 +1054,7 @@ } /* Report the amount of memory. */ - print_debug("RAM: 0x"); - print_debug_hex32(tom_k); - print_debug(" KB\r\n"); + printk_debug("RAM: 0x%08x kB\n", tom_k); msr_t msr; if (tom_k > (4*1024*1024)) { @@ -1202,7 +1184,7 @@ csbase += csbase_inc; } - print_debug("Interleaved\r\n"); + printk_debug("Interleaved\n"); /* Return the memory size in K */ return common_size << ((27-10) + bits); @@ -1306,7 +1288,7 @@ CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); } else { - print_debug("Interleaving disabled\r\n"); + printk_debug("Interleaving disabled\n"); tom_k = 0; } @@ -1325,9 +1307,7 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, struct mem_info *meminfo) { - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); + printk_debug("disabling dimm %02x\n", index); if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); @@ -1402,9 +1382,9 @@ #if 1 if (meminfo->is_registered) { - print_debug("Registered\r\n"); + printk_debug("Registered\n"); } else { - print_debug("Unbuffered\r\n"); + printk_debug("Unbuffered\n"); } #endif return meminfo->dimm_mask; @@ -1420,6 +1400,7 @@ int byte; unsigned device; device = ctrl->channel0[i]; + printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device); if (device) { byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */ if (byte == SPD_MEM_TYPE_SDRAM_DDR2) { @@ -1427,6 +1408,7 @@ } } device = ctrl->channel1[i]; + printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device); if (device) { byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE); if (byte == SPD_MEM_TYPE_SDRAM_DDR2) { @@ -1448,27 +1430,32 @@ 4, /* *Column addresses */ 5, /* *Number of DIMM Ranks */ 6, /* *Module Data Width*/ - 9, /* *Cycle time at highest CAS Latency CL=X */ 11, /* *DIMM Conf Type */ 13, /* *Pri SDRAM Width */ 17, /* *Logical Banks */ - 18, /* *Supported CAS Latencies */ 20, /* *DIMM Type Info */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 1) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 2) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ 30, /* *tRAS Activate to Precharge */ 36, /* *Write recovery time (tWR) */ 37, /* *Internal write to read command delay (tRDP) */ - 38, /* *Internal read to precharge commanfd delay (tRTP) */ - 41, /* *Extension of Byte 41 tRC and Byte 42 tRFC */ + 38, /* *Internal read to precharge command delay (tRTP) */ + 40, /* *Extension of Byte 41 tRC and Byte 42 tRFC */ 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */ 42, /* *Minimum Auto Refresh Command Time(Trfc) */ + /* The SPD addresses 18, 9, 23, 26 need special treatment like + * in spd_set_memclk. Right now they cause many false negatives. + * Keep them at the end to see other mismatches (if any). + */ + 18, /* *Supported CAS Latencies */ + 9, /* *Cycle time at highest CAS Latency CL=X */ + 23, /* *Cycle time at CAS Latency (CLX - 1) */ + 26, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; + u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ #if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 @@ -1497,6 +1484,14 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; + /* Abort if the chips don't support a common CAS latency. */ + common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18); + if (!common_cl) { + printk_debug("No common CAS latency supported\n"); + goto single_channel; + } else { + printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl); + } for (j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; @@ -1509,11 +1504,12 @@ return -1; } if (value0 != value1) { + printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr); goto single_channel; } } } - print_spew("Enabling dual channel memory\r\n"); + printk_spew("Enabling dual channel memory\n"); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */ @@ -1566,7 +1562,7 @@ static const struct mem_param speed[] = { { - .name = "200Mhz\r\n", + .name = "200MHz", .cycle_time = 0x500, .divisor = 200, // how many 1/40ns per clock .dch_memclk = DCH_MemClkFreq_200MHz, //0 @@ -1578,7 +1574,7 @@ }, { - .name = "266Mhz\r\n", + .name = "266MHz", .cycle_time = 0x375, .divisor = 150, //???? .dch_memclk = DCH_MemClkFreq_266MHz, //1 @@ -1589,7 +1585,7 @@ .DcqByPassMax = 4, }, { - .name = "333Mhz\r\n", + .name = "333MHz", .cycle_time = 0x300, .divisor = 120, .dch_memclk = DCH_MemClkFreq_333MHz, //2 @@ -1601,7 +1597,7 @@ }, { - .name = "400Mhz\r\n", + .name = "400MHz", .cycle_time = 0x250, .divisor = 100, .dch_memclk = DCH_MemClkFreq_400MHz,//3 @@ -1628,10 +1624,7 @@ if (!param->cycle_time) { die("min_cycle_time to low"); } - print_spew(param->name); -#ifdef DRAM_MIN_CYCLE_TIME - print_debug(param->name); -#endif + printk_debug("%s\n", param->name); return param; } @@ -1736,7 +1729,7 @@ } min_latency = 3; - print_tx("1 min_cycle_time:", min_cycle_time); + printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time); /* Compute the least latency with the fastest clock supported * by both the memory controller and the dimms. @@ -1748,7 +1741,7 @@ int latency; u32 spd_device = ctrl->channel0[i]; - print_tx("1.1 dimm_mask:", meminfo->dimm_mask); + printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & (1 << i))) { if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */ spd_device = ctrl->channel1[i]; @@ -1770,9 +1763,16 @@ latencies = spd_read_byte(spd_device, SPD_CAS_LAT); if (latencies <= 0) continue; - print_tx("i:",i); - print_tx("\tlatencies:", latencies); - /* Compute the lowest cas latency supported */ + printk_raminit("i: %08x\n",i); + printk_raminit("\tlatencies: %08x\n", latencies); + /* Compute the lowest cas latency which can be expressed in this + * particular SPD EEPROM. You can store at most settings for 3 + * contiguous CAS latencies, so by taking the highest CAS + * latency maked as supported in the SPD and subtracting 2 you + * get the lowest expressable CAS latency. That latency is not + * necessarily supported, but a (maybe invalid) entry exists + * for it. + */ latency = log2(latencies) - 2; /* Loop through and find a fast clock with a low latency */ @@ -1787,15 +1787,15 @@ goto hw_error; } - print_tx("\tindex:", index); - print_tx("\t\tlatency:", latency); - print_tx("\t\tvalue1:", value); + printk_raminit("\tindex: %08x\n", index); + printk_raminit("\t\tlatency: %08x\n", latency); + printk_raminit("\t\tvalue1: %08x\n", value); value = convert_to_linear(value); - print_tx("\t\tvalue2:", value); + printk_raminit("\t\tvalue2: %08x\n", value); - /* Only increase the latency if we decreas the clock */ + /* Only increase the latency if we decrease the clock */ if (value >= min_cycle_time ) { if (value < new_cycle_time) { new_cycle_time = value; @@ -1806,8 +1806,8 @@ } } } - print_tx("\t\tnew_cycle_time:", new_cycle_time); - print_tx("\t\tnew_latency:", new_latency); + printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time); + printk_raminit("\t\tnew_latency: %08x\n", new_latency); } @@ -1825,15 +1825,15 @@ min_latency = new_latency; } - print_tx("2 min_cycle_time:", min_cycle_time); - print_tx("2 min_latency:", min_latency); + printk_raminit("2 min_cycle_time: %08x\n", min_cycle_time); + printk_raminit("2 min_latency: %08x\n", min_latency); } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. */ - print_tx("3 min_cycle_time:", min_cycle_time); - print_tx("3 min_latency:", min_latency); + printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time); + printk_raminit("3 min_latency: %08x\n", min_latency); for (i = 0; (i < DIMM_SOCKETS); i++) { int latencies; @@ -1888,7 +1888,7 @@ meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo); } - print_tx("4 min_cycle_time:", min_cycle_time); + printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time); /* Now that I know the minimum cycle time lookup the memory parameters */ result.param = get_mem_param(min_cycle_time); @@ -1900,7 +1900,7 @@ value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); - print_debug(result.param->name); + printk_debug("%s\n", result.param->name); /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); @@ -2068,16 +2068,16 @@ value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns if (value < 0) return -1; - print_tx("update_dimm_Tras: 0 value=", value); + printk_raminit("update_dimm_Tras: 0 value= %08x\n", value); value <<= 2; //convert it to in 1/4ns value *= 10; - print_tx("update_dimm_Tras: 1 value=", value); + printk_raminit("update_dimm_Tras: 1 value= %08x\n", value); clocks = (value + param->divisor - 1)/param->divisor; - print_tx("update_dimm_Tras: divisor=", param->divisor); - print_tx("update_dimm_Tras: clocks=", clocks); + printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor); + printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks); if (clocks < DTL_TRAS_MIN) { clocks = DTL_TRAS_MIN; } @@ -2380,8 +2380,8 @@ uint32_t reg; if ((val < TT_MIN) || (val > TT_MAX)) { - print_err(str); - die(" Unknown\r\n"); + printk_err(str); + die(" Unknown\n"); } reg = pci_read_config32(ctrl->f2, TT_REG); @@ -2624,12 +2624,12 @@ break; } - print_raminit("\tdimm_mask = ", meminfo->dimm_mask); - print_raminit("\tx4_mask = ", meminfo->x4_mask); - print_raminit("\tx16_mask = ", meminfo->x16_mask); - print_raminit("\tsingle_rank_mask = ", meminfo->single_rank_mask); - print_raminit("\tODC = ", dword); - print_raminit("\tAddr Timing= ", dwordx); + printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask); + printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask); + printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask); + printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask); + printk_raminit("\tODC = %08x\n", dword); + printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif #if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ @@ -2711,37 +2711,37 @@ !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) { continue; } - print_tx("spd_set_dram_timing dimm socket: ", i); + printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i); /* DRAM Timing Low Register */ - print_t("\ttrc\r\n"); + printk_raminit("\ttrc\n"); if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrcd\r\n"); + printk_raminit("\ttrcd\n"); if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrrd\r\n"); + printk_raminit("\ttrrd\n"); if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttras\r\n"); + printk_raminit("\ttras\n"); if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrp\r\n"); + printk_raminit("\ttrp\n"); if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrtp\r\n"); + printk_raminit("\ttrtp\n"); if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err; - print_t("\ttwr\r\n"); + printk_raminit("\ttwr\n"); if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; /* DRAM Timing High Register */ - print_t("\ttref\r\n"); + printk_raminit("\ttref\n"); if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttwtr\r\n"); + printk_raminit("\ttwtr\n"); if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err; - print_t("\ttrfc\r\n"); + printk_raminit("\ttrfc\n"); if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err; /* DRAM Config Low */ @@ -2798,37 +2798,37 @@ #endif meminfo = &sysinfo->meminfo[ctrl->node_id]; - print_debug_addr("sdram_set_spd_registers: paramx :", &paramx); + printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx); activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl); - print_tx("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { - print_debug("No memory for this cpu\r\n"); + printk_debug("No memory for this cpu\n"); return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); - print_tx("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo); - print_tx("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo); - print_tx("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; result = spd_set_memclk(ctrl, meminfo); param = result.param; meminfo->dimm_mask = result.dimm_mask; - print_tx("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2840,7 +2840,7 @@ paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor); meminfo->dimm_mask = spd_set_dram_timing(ctrl, &paramx, meminfo); - print_tx("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2975,13 +2975,13 @@ /* FIXME: How about 32 node machine later? */ tsc_t tsc, tsc0[8]; - print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]); + printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]); #endif uint32_t dword; /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { - die("No memory\r\n"); + die("No memory\n"); } /* Before enabling memory start the memory clocks */ @@ -3004,15 +3004,15 @@ } } - /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */ + /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */ memreset(controllers, ctrl); #if 0 - print_debug("prepare to InitDram:"); + printk_debug("prepare to InitDram:"); for (i=0; i<10; i++) { - print_debug_hex32(i); + printk_debug("%08x", i); print_debug("\b\b\b\b\b\b\b\b"); } - print_debug("\r\n"); + printk_debug("\n"); #endif for (i = 0; i < controllers; i++) { @@ -3029,7 +3029,7 @@ dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { uint32_t mnc; - print_spew("ECC enabled\r\n"); + printk_spew("ECC enabled\n"); mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_Width128) { @@ -3071,17 +3071,17 @@ /* Skip everything if I don't have any memory on this controller */ if (sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("Initializing memory: "); + printk_debug("Initializing memory: "); int loops = 0; do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops++; if ((loops & 1023) == 0) { - print_debug("."); + printk_debug("."); } } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { - print_debug(" failed\r\n"); + printk_debug(" failed\n"); continue; } @@ -3094,7 +3094,7 @@ if (cpu_f0_f1[i]) { tsc= rdtsc(); - print_debug_dqs_tsc("\r\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); + print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2); if (tsc.lo<tsc0[i].lo) { @@ -3109,7 +3109,7 @@ print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2); } #endif - print_debug(" done\r\n"); + printk_debug(" done\n"); } #if HW_MEM_HOLE_SIZEK != 0 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2009-01-15 02:35:30 UTC (rev 3864) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2009-01-16 00:19:17 UTC (rev 3865) @@ -21,15 +21,16 @@ //0: mean no debug info #define DQS_TRAIN_DEBUG 0 +#if CONFIG_USE_PRINTK_IN_CAR +#else +#error This file needs CONFIG_USE_PRINTK_IN_CAR +#endif + static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x\r\n", str, val); - #else - print_debug(str); print_debug_hex32(val); print_debug("\r\n"); - #endif } #endif } @@ -38,11 +39,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); - #else - print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); - #endif } #endif } @@ -51,22 +48,14 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif } @@ -868,11 +857,7 @@ #if MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ - #if CONFIG_USE_PRINTK_IN_CAR - printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay); - #else - print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); - #endif + printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif return (CTLRMaxDelay==0xae)?1:0; @@ -1148,7 +1133,7 @@ print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3); - print_debug_addr("TrainDQSPos: MutualCSPassW[48] :", MutualCSPassW); + printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); for(DQSDelay=0; DQSDelay<48; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) @@ -1421,7 +1406,7 @@ print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); - print_debug_addr("TrainDQSRdWrPos: buf_a:", buf_a); + printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a); Errors = 0; channel = 0; @@ -1555,7 +1540,7 @@ { print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); + printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); return 1; } else { @@ -1688,7 +1673,7 @@ return r; } -/* fms: find least sigificant bit set */ +/* fls: find least sigificant bit set */ static inline unsigned int fls(unsigned int x) { int r; @@ -1718,19 +1703,11 @@ } sizek = 1 << align; #if MEM_TRAIN_SEQ != 1 - #if CONFIG_USE_PRINTK_IN_CAR printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); - #else - print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); - print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); - print_debug( (type==MTRR_TYPE_UNCACHEABLE)?"UC\r\n": - ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n") - ); - #endif #endif set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; @@ -1879,10 +1856,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass1: "); - print_debug_hex8(i); + printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); } tsc[1] = rdtsc(); @@ -1898,10 +1874,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:DQSPos: "); - print_debug_hex8(i); + printk_debug("DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); } tsc[3] = rdtsc(); @@ -1912,10 +1887,9 @@ /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass2: "); - print_debug_hex8(i); + printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - print_debug(" done\r\n"); + printk_debug(" done\r\n"); sysinfo->mem_trained[i]=1; } @@ -1956,8 +1930,7 @@ if(v) { tsc[0] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass1: "); - print_debug_hex8(i); + printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // @@ -1965,10 +1938,9 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[1] = rdtsc(); - print_debug("set DQS timing:DQSPos: "); - print_debug_hex8(i); + printk_debug("set DQS timing:DQSPos: %02x\n", i); } if(train_DqsPos(ctrl, sysinfo)) { @@ -1977,11 +1949,10 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[2] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass2: "); - print_debug_hex8(i); + printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // @@ -1989,7 +1960,7 @@ } if(v) { - print_debug(" done\r\n"); + printk_debug(" done\r\n"); tsc[3] = rdtsc(); } @@ -2040,7 +2011,7 @@ #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 - print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n"); + printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); #else /* Can copy dqs_timing to ap cache and run from cache?

1 0

K8 dual channel problem
by Carl-Daniel Hailfinger 15 Jan '09

15 Jan '09

Hi, I have two DDR2 DIMMS with 2 GB each, but coreboot refuses to use them in a dualchannel setup. Instead, one DIMM is ignored. I have attached the result from decode-dimms. Regards, Carl-Daniel -- http://www.hailfinger.org/ Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0050 Guessing DIMM is in bank 1 ---=== SPD EEPROM Information ===--- EEPROM Checksum of bytes 0-62 OK (0x18) # of bytes written to SDRAM EEPROM 128 Total number of bytes in EEPROM 256 Fundamental Memory type DDR2 SDRAM SPD Revision 1.2 ---=== Memory Characteristics ===--- Maximum module speed 800MHz (PC2-6400) Size 2048 MB Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 Ranks 2 SDRAM Device Width 8 bits Module Height 30.0 mm Module Type UDIMM (133.25 mm) DRAM Package Planar Voltage Interface Level SSTL 1.8V Refresh Rate Reduced (7.8 us) - Self Refresh Supported Burst Lengths 4, 8 tCL-tRCD-tRP-tRAS 5-5-5-18 Supported CAS Latencies (tCL) 5T, 4T Minimum Cycle Time at CAS 5 (tCK min) 2.50 ns Maximum Access Time at CAS 5 (tAC) 0.40 ns Minimum Cycle Time at CAS 4 3.75 ns Maximum Access Time at CAS 4 0.50 ns Maximum Cycle Time (tCK max) 8.00 ns ---=== Timing Parameters ===--- Address/Command Setup Time Before Clock (tIS) 0.17 ns Address/Command Hold Time After Clock (tIH) 0.25 ns Data Input Setup Time Before Strobe (tDS) 0.05 ns Data Input Hold Time After Strobe (tDH) 0.12 ns Minimum Row Precharge Delay (tRP) 12.50 ns Minimum Row Active to Row Active Delay (tRRD) 7.50 ns Minimum RAS# to CAS# Delay (tRCD) 12.50 ns Minimum RAS# Pulse Width (tRAS) 45.00 ns Write Recovery Time (tWR) 15.00 ns Minimum Write to Read CMD Delay (tWTR) 7.50 ns Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns Minimum Active to Auto-refresh Delay (tRC) 60.00 ns Minimum Recovery Delay (tRFC) 127.50 ns Maximum DQS to DQ Skew (tDQSQ) 0.20 ns Maximum Read Data Hold Skew (tQHS) 0.30 ns ---=== Manufacturing Information ===--- Manufacturer Mushkin Manufacturing Location Code 0x01 Part Number 991558 (996558) Manufacturing Date 2008-W02 Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0051 Guessing DIMM is in bank 2 ---=== SPD EEPROM Information ===--- EEPROM Checksum of bytes 0-62 OK (0x4A) # of bytes written to SDRAM EEPROM 128 Total number of bytes in EEPROM 256 Fundamental Memory type DDR2 SDRAM SPD Revision 1.2 ---=== Memory Characteristics ===--- Maximum module speed 800MHz (PC2-6400) Size 2048 MB Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 Ranks 2 SDRAM Device Width 8 bits Module Height 30.0 mm Module Type UDIMM (133.25 mm) DRAM Package Planar Voltage Interface Level SSTL 1.8V Refresh Rate Reduced (7.8 us) - Self Refresh Supported Burst Lengths 4, 8 tCL-tRCD-tRP-tRAS 6-5-5-18 Supported CAS Latencies (tCL) 6T, 5T, 4T Minimum Cycle Time at CAS 6 (tCK min) 2.50 ns Maximum Access Time at CAS 6 (tAC) 0.40 ns Minimum Cycle Time at CAS 5 2.50 ns Maximum Access Time at CAS 5 0.40 ns Minimum Cycle Time at CAS 4 3.75 ns Maximum Access Time at CAS 4 0.50 ns Maximum Cycle Time (tCK max) 8.00 ns ---=== Timing Parameters ===--- Address/Command Setup Time Before Clock (tIS) 0.17 ns Address/Command Hold Time After Clock (tIH) 0.25 ns Data Input Setup Time Before Strobe (tDS) 0.05 ns Data Input Hold Time After Strobe (tDH) 0.12 ns Minimum Row Precharge Delay (tRP) 12.50 ns Minimum Row Active to Row Active Delay (tRRD) 7.50 ns Minimum RAS# to CAS# Delay (tRCD) 12.50 ns Minimum RAS# Pulse Width (tRAS) 45.00 ns Write Recovery Time (tWR) 15.00 ns Minimum Write to Read CMD Delay (tWTR) 7.50 ns Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns Minimum Active to Auto-refresh Delay (tRC) 57.00 ns Minimum Recovery Delay (tRFC) 127.50 ns Maximum DQS to DQ Skew (tDQSQ) 0.20 ns Maximum Read Data Hold Skew (tQHS) 0.30 ns ---=== Manufacturing Information ===--- Manufacturer AENEON Manufacturing Location Code E Part Number AET860UD00-25DC08X Revision Code 0x0143 Manufacturing Date 2008-W13 Assembly Serial Number 0x1503005C

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[announce] coreboot-announce
by Stefan Reinauer 15 Jan '09

15 Jan '09

Hi, coreboot readers, we now have a coreboot-announce mailing list for all those that do not want to cope with an average of meanwhile over a thousand mails per month without losing the track on what's new in coreboot. I decided against subscribing everyone on the coreboot mailing list automatically to the new list, so if you wish to receive mail to coreboot-announce(a)coreboot.org please subscribe yourself. You can achieve this using the web frontend: https://www.coreboot.org/mailman/listinfo/coreboot-announce or by sending an email to coreboot-announce-subscribe(a)coreboot.org Please direct feedback and problems with the new list to me. Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Supermicro H8DME-2 Coreboot v2
by Kevin Connelly 15 Jan '09

15 Jan '09

Hi All, I am attempting to boot a H8DME-2 using the Supermicro H8DMR-i2 code as a starting point. I am having problems getting the ram to initialize properly. I can get a bootable system, but not with the proper amount of ram available in the OS. Using i2cdetect, it appears that the ram off the first cpu is at 30-37, and the ram off the second cpu is at 50-57. Setting these addresses in Congig.lb does not seem to fix the problem. I have attached lspci and dmidecode dumps. Please let me know what other debug information would be helpful. Any help or guidance is greatly appreciated. Thanks in advance. Kevin # dmidecode 2.9 SMBIOS 2.4 present. 82 structures occupying 3583 bytes. Table at 0x000FB960. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: American Megatrends Inc. Version: 080014 Release Date: 10/13/2008 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 1024 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 KB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported LS-120 boot is supported ATAPI Zip drive boot is supported BIOS boot specification is supported Targeted content distribution is supported BIOS Revision: 8.14 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Supermicro Product Name: H8DM8-2 Version: 1234567890 Serial Number: 1234567890 UUID: 00020003-0004-0005-0006-000700080009 Wake-up Type: Power Switch SKU Number: To Be Filled By O.E.M. Family: To Be Filled By O.E.M. Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: Supermicro Product Name: H8DM8-2 Version: 1234567890 Serial Number: 1234567890 Asset Tag: To Be Filled By O.E.M. Features: Board is a hosting board Board is replaceable Location In Chassis: To Be Filled By O.E.M. Chassis Handle: 0x0003 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 21 bytes Chassis Information Manufacturer: To Be Filled By O.E.M. Type: Desktop Lock: Not Present Version: To Be Filled By O.E.M. Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0004, DMI type 4, 40 bytes Processor Information Socket Designation: CPU 1 Type: Central Processor Family: Dual-Core Opteron Manufacturer: AMD ID: 12 0F 04 00 FF FB 8B 17 Signature: Family 15, Model 65, Stepping 2 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) HTT (Hyper-threading technology) Version: Dual-Core AMD Opteron(tm) Processor 2216 Voltage: 1.5 V External Clock: 200 MHz Max Speed: 2400 MHz Current Speed: 2400 MHz Status: Populated, Enabled Upgrade: Other L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Part Number: To Be Filled By O.E.M. Core Count: 2 Core Enabled: 2 Characteristics: 64-bit capable Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 256 KB Maximum Size: 256 KB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Data Associativity: 4-way Set-associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 2048 KB Maximum Size: 2048 KB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 4-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Disabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 0 KB Maximum Size: 0 KB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x0008, DMI type 4, 40 bytes Processor Information Socket Designation: CPU 2 Type: Central Processor Family: Dual-Core Opteron Manufacturer: AMD ID: 12 0F 04 00 FF FB 8B 17 Signature: Family 15, Model 65, Stepping 2 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) HTT (Hyper-threading technology) Version: Dual-Core AMD Opteron(tm) Processor 2216 Voltage: 1.5 V External Clock: 200 MHz Max Speed: 2400 MHz Current Speed: 2400 MHz Status: Populated, Enabled Upgrade: Other L1 Cache Handle: 0x0009 L2 Cache Handle: 0x000A L3 Cache Handle: 0x000B Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Part Number: To Be Filled By O.E.M. Core Count: 2 Core Enabled: 2 Characteristics: 64-bit capable Handle 0x0009, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 256 KB Maximum Size: 256 KB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Data Associativity: 4-way Set-associative Handle 0x000A, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 2048 KB Maximum Size: 2048 KB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 4-way Set-associative Handle 0x000B, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Disabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 0 KB Maximum Size: 0 KB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: PS2Mouse External Connector Type: PS/2 Port Type: Mouse Port Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: Keyboard External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2 Internal Connector Type: None External Reference Designator: USB1 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2 Internal Connector Type: None External Reference Designator: USB2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J4A1 Internal Connector Type: None External Reference Designator: LPT 1 External Connector Type: DB-25 male Port Type: Parallel Port ECP/EPP Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A1 Internal Connector Type: None External Reference Designator: COM A External Connector Type: DB-9 male Port Type: Serial Port 16550A Compatible Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6A1 Internal Connector Type: None External Reference Designator: Audio Mic In External Connector Type: Mini Jack (headphones) Port Type: Audio Port Handle 0x0013, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6A1 Internal Connector Type: None External Reference Designator: Audio Line In External Connector Type: Mini Jack (headphones) Port Type: Audio Port Handle 0x0014, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6B1 - AUX IN Internal Connector Type: On Board Sound Input From CD-ROM External Reference Designator: Not Specified External Connector Type: None Port Type: Audio Port Handle 0x0015, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6B2 - CDIN Internal Connector Type: On Board Sound Input From CD-ROM External Reference Designator: Not Specified External Connector Type: None Port Type: Audio Port Handle 0x0016, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6J2 - PRI IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0017, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6J1 - SEC IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0018, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J4J1 - FLOPPY Internal Connector Type: On Board Floppy External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0019, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9H1 - FRONT PNL Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1B1 - CHASSIS REAR FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2F1 - CPU FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J8B4 - FRONT FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G2 - FNT USB Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6C3 - FP AUD Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G1 - CONFIG Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0020, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J8C1 - SCSI LED Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0021, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9J2 - INTRUDER Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0022, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G4 - ITP Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0023, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2H1 - MAIN POWER Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0024, DMI type 9, 13 bytes System Slot Information Designation: PCI0 Type: 64-bit PCI-X Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0025, DMI type 9, 13 bytes System Slot Information Designation: PCI1 Type: 64-bit PCI-X Current Usage: Available Length: Short ID: 2 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0026, DMI type 9, 13 bytes System Slot Information Designation: PCI2 Type: 64-bit PCI-X Current Usage: Available Length: Short ID: 3 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0027, DMI type 9, 13 bytes System Slot Information Designation: PCI3 Type: 64-bit PCI-X Current Usage: Available Length: Short ID: 4 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0028, DMI type 9, 13 bytes System Slot Information Designation: PCI4 Type: x8 PCI Express Current Usage: Available Length: Short ID: 5 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0029, DMI type 9, 13 bytes System Slot Information Designation: PCI5 Type: x8 PCI Express Current Usage: Available Length: Short ID: 6 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x002A, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: To Be Filled By O.E.M. Handle 0x002B, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 1 en|US|iso8859-1 Currently Installed Language: en|US|iso8859-1 Handle 0x002C, DMI type 15, 55 bytes System Event Log Area Length: 1008 bytes Header Start Offset: 0x1810 Data Start Offset: 0x1810 Access Method: General-purpose non-volatile data functions Access Address: 0x0002 Status: Valid, Not Full Change Token: 0x00000000 Header Format: No Header Supported Log Type Descriptors: 9 Descriptor 1: Single-bit ECC memory error Data Format 1: Multiple-event handle Descriptor 2: Multi-bit ECC memory error Data Format 2: Multiple-event handle Descriptor 3: Parity memory error Data Format 3: Multiple-event Descriptor 4: I/O channel block Data Format 4: Multiple-event Descriptor 5: POST error Data Format 5: POST results bitmap Descriptor 6: PCI parity error Data Format 6: Multiple-event handle Descriptor 7: PCI system error Data Format 7: Multiple-event handle Descriptor 8: System limit exceeded Data Format 8: Multiple-event system management Descriptor 9: OEM-specific Data Format 9: POST results bitmap Handle 0x002D, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 8 GB Error Information Handle: Not Provided Number Of Devices: 16 Handle 0x002E, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0081FFFFFFF Range Size: 33280 MB Physical Array Handle: 0x002D Partition Width: 0 Handle 0x002F, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM0 Bank Locator: BANK0 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer0 Serial Number: SerNum0 Asset Tag: AssetTagNum0 Part Number: PartNum0 Handle 0x0030, DMI type 126, 19 bytes Inactive Handle 0x0031, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK1 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer1 Serial Number: SerNum1 Asset Tag: AssetTagNum1 Part Number: PartNum1 Handle 0x0032, DMI type 126, 19 bytes Inactive Handle 0x0033, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK2 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer2 Serial Number: SerNum2 Asset Tag: AssetTagNum2 Part Number: PartNum2 Handle 0x0034, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0033 Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x0035, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM3 Bank Locator: BANK3 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer3 Serial Number: SerNum3 Asset Tag: AssetTagNum3 Part Number: PartNum3 Handle 0x0036, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00100000000 Ending Address: 0x001FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0035 Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x0037, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM4 Bank Locator: BANK4 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer4 Serial Number: SerNum4 Asset Tag: AssetTagNum4 Part Number: PartNum4 Handle 0x0038, DMI type 126, 19 bytes Inactive Handle 0x0039, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM5 Bank Locator: BANK5 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer5 Serial Number: SerNum5 Asset Tag: AssetTagNum5 Part Number: PartNum5 Handle 0x003A, DMI type 126, 19 bytes Inactive Handle 0x003B, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM6 Bank Locator: BANK6 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer6 Serial Number: SerNum6 Asset Tag: AssetTagNum6 Part Number: PartNum6 Handle 0x003C, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00200000000 Ending Address: 0x002FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x003B Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x003D, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM7 Bank Locator: BANK7 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer7 Serial Number: SerNum7 Asset Tag: AssetTagNum7 Part Number: PartNum7 Handle 0x003E, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00300000000 Ending Address: 0x003FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x003D Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x003F, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM8 Bank Locator: BANK8 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer8 Serial Number: SerNum8 Asset Tag: AssetTagNum8 Part Number: PartNum8 Handle 0x0040, DMI type 126, 19 bytes Inactive Handle 0x0041, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM9 Bank Locator: BANK9 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer9 Serial Number: SerNum9 Asset Tag: AssetTagNum9 Part Number: PartNum9 Handle 0x0042, DMI type 126, 19 bytes Inactive Handle 0x0043, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM10 Bank Locator: BANK10 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer10 Serial Number: SerNum10 Asset Tag: AssetTagNum10 Part Number: PartNum10 Handle 0x0044, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00400000000 Ending Address: 0x004FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0043 Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x0045, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM11 Bank Locator: BANK11 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer11 Serial Number: SerNum11 Asset Tag: AssetTagNum11 Part Number: PartNum11 Handle 0x0046, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00500000000 Ending Address: 0x005FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0045 Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x0047, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM12 Bank Locator: BANK12 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer12 Serial Number: SerNum12 Asset Tag: AssetTagNum12 Part Number: PartNum12 Handle 0x0048, DMI type 126, 19 bytes Inactive Handle 0x0049, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM13 Bank Locator: BANK13 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer13 Serial Number: SerNum13 Asset Tag: AssetTagNum13 Part Number: PartNum13 Handle 0x004A, DMI type 126, 19 bytes Inactive Handle 0x004B, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM14 Bank Locator: BANK14 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer14 Serial Number: SerNum14 Asset Tag: AssetTagNum14 Part Number: PartNum14 Handle 0x004C, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00600000000 Ending Address: 0x006FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x004B Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x004D, DMI type 17, 27 bytes Memory Device Array Handle: 0x002D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM15 Bank Locator: BANK15 Type: DDR2 Type Detail: Synchronous Speed: 333 MHz (3.0 ns) Manufacturer: Manufacturer15 Serial Number: SerNum15 Asset Tag: AssetTagNum15 Part Number: PartNum15 Handle 0x004E, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00700000000 Ending Address: 0x007FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x004D Memory Array Mapped Address Handle: 0x002E Partition Row Position: 1 Handle 0x004F, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x0050, DMI type 38, 18 bytes IPMI Device Information Interface Type: KCS (Keyboard Control Style) Specification Version: 1.5 I2C Slave Address: 0x00 NV Storage Device: Not Present Base Address: 0x0000000000000000 (Memory-mapped) Register Spacing: Successive Byte Boundaries Handle 0x0051, DMI type 127, 4 bytes End Of Table -[0000:00]-+-00.0 nVidia Corporation MCP55 Memory Controller +-01.0 nVidia Corporation MCP55 LPC Bridge +-01.1 nVidia Corporation MCP55 SMBus +-02.0 nVidia Corporation MCP55 USB Controller +-02.1 nVidia Corporation MCP55 USB Controller +-04.0 nVidia Corporation MCP55 IDE +-05.0 nVidia Corporation MCP55 SATA Controller +-05.1 nVidia Corporation MCP55 SATA Controller +-05.2 nVidia Corporation MCP55 SATA Controller +-06.0-[0000:01]----05.0 ATI Technologies Inc ES1000 +-08.0 nVidia Corporation MCP55 Ethernet +-09.0 nVidia Corporation MCP55 Ethernet +-0a.0-[0000:02-04]--+-00.0-[0000:03]-- | \-00.1-[0000:04]-- +-0d.0-[0000:05]-- +-0e.0-[0000:06]-- +-0f.0-[0000:07]-- +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a2) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [dc] HyperTransport: MSI Mapping 00: de 10 69 03 06 01 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: de 10 64 03 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at dc00 [size=64] Region 4: I/O ports at 2d00 [size=64] Region 5: I/O ports at 2e00 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 68 03 01 00 b0 00 a3 00 05 0c 00 00 80 00 10: 01 dc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 2d 00 00 01 2e 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 00 00 00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) (prog-if 10 [OHCI]) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at feafb000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 6c 03 07 00 b0 00 a1 10 03 0c 00 00 80 00 10: 00 b0 af fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 07 01 03 01 00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) (prog-if 20 [EHCI]) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 22 Region 0: Memory at feafac00 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 6d 03 06 00 b0 00 a2 20 03 0c 00 00 80 00 10: 00 ac af fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: Unknown device f5d9:1611 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at ffa0 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 6e 03 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: a1 ff 00 00 00 00 00 00 00 00 00 00 d9 f5 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at d480 [size=8] Region 1: I/O ports at d400 [size=4] Region 2: I/O ports at d080 [size=8] Region 3: I/O ports at d000 [size=4] Region 4: I/O ports at cc00 [size=16] Region 5: Memory at feaf9000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 81 d4 00 00 01 d4 00 00 81 d0 00 00 01 d0 00 00 20: 01 cc 00 00 00 90 af fe 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 22 Region 0: I/O ports at c880 [size=8] Region 1: I/O ports at c800 [size=4] Region 2: I/O ports at c480 [size=8] Region 3: I/O ports at c400 [size=4] Region 4: I/O ports at c080 [size=16] Region 5: Memory at feaf8000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 81 c8 00 00 01 c8 00 00 81 c4 00 00 01 c4 00 00 20: 81 c0 00 00 00 80 af fe 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 02 03 01 00:05.2 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin C routed to IRQ 21 Region 0: I/O ports at c000 [size=8] Region 1: I/O ports at bc00 [size=4] Region 2: I/O ports at b880 [size=8] Region 3: I/O ports at b800 [size=4] Region 4: I/O ports at b480 [size=16] Region 5: Memory at feaf7000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 01 c0 00 00 01 bc 00 00 81 b8 00 00 01 b8 00 00 20: 81 b4 00 00 00 70 af fe 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 03 03 01 00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000e000-0000efff Memory behind bridge: feb00000-febfffff Prefetchable memory behind bridge: f0000000-f7ffffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- Capabilities: [b8] Subsystem: Super Micro Computer Inc Unknown device 1611 Capabilities: [8c] HyperTransport: MSI Mapping 00: de 10 70 03 07 00 b0 00 a2 01 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 e0 e0 80 02 20: b0 fe b0 fe 00 f0 f0 f7 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 1a 02 00:08.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 2299 Region 0: Memory at feaf6000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b400 [size=8] Region 2: Memory at feafa800 (32-bit, non-prefetchable) [size=256] Region 3: Memory at feafa400 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Vector table: BAR=2 offset=00000000 PBA: BAR=3 offset=00000000 Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/3 Enable+ Address: 00000000fee0f00c Data: 4189 Masking: 000000fe Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping 00: de 10 73 03 07 04 b0 00 a3 00 80 06 00 00 00 00 10: 00 60 af fe 01 b4 00 00 00 a8 af fe 00 a4 af fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 01 14 00:09.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at feaf5000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b080 [size=8] Region 2: Memory at feafa000 (32-bit, non-prefetchable) [size=256] Region 3: Memory at feaf4c00 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Vector table: BAR=2 offset=00000000 PBA: BAR=3 offset=00000000 Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/3 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping 00: de 10 73 03 07 00 b0 00 a3 00 80 06 00 00 00 00 10: 00 50 af fe 81 b0 00 00 00 a0 af fe 00 4c af fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 01 14 00:0a.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device 0000 Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4149 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <64ns, L1 <1us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x8, ASPM L0s L1, Port 5 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x8 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 76 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 04 00 f1 01 00 20 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0d.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device 0000 Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4151 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <64ns, L1 <1us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x4, ASPM L0s L1, Port 2 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x4 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 78 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0e.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device 0000 Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4159 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <64ns, L1 <1us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x8, ASPM L0s L1, Port 1 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x8 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 75 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device 0000 Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4161 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <64ns, L1 <1us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x8, ASPM L0s L1, Port 0 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x16 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 77 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 07 07 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [a0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [c0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [f0] #0f [0010] 00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [a0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [c0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=N/C LWO=N/C Revision ID: 1.02 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [f0] #0f [0010] 00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 01:05.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) (prog-if 00 [VGA controller]) Subsystem: Super Micro Computer Inc Unknown device 1611 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (2000ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 10 Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at e000 [size=256] Region 2: Memory at febf0000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at feb00000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 5e 51 87 00 90 02 02 00 00 03 10 40 00 00 10: 08 00 00 f0 01 e0 00 00 00 00 bf fe 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 16 30: 00 00 bc fe 50 00 00 00 00 00 00 00 0a 01 08 00 02:00.0 PCI bridge: NEC Corporation uPD720400 PCI Express - PCI/PCI-X Bridge (rev 07) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=02, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity+ SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Express PCI/PCI-X Bridge IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <64ns, L1 <1us Device: AtnBtn- AtnInd- PwrInd- Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported- Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x8, ASPM L0s L1, Port 0 Link: Latency L0s <4us, L1 <16us Link: ASPM Disabled CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x8 Capabilities: [54] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=02:00.0 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=32 CommitmentLimit=32 Downstream: Capacity=16 CommitmentLimit=16 Capabilities: [64] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=55mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ 00: 33 10 25 01 04 01 10 00 07 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 02 03 03 40 f1 01 20 24 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 07 00 02:00.1 PCI bridge: NEC Corporation uPD720400 PCI Express - PCI/PCI-X Bridge (rev 07) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=02, secondary=04, subordinate=04, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity+ SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Express PCI/PCI-X Bridge IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <64ns, L1 <1us Device: AtnBtn- AtnInd- PwrInd- Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported- Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x8, ASPM L0s L1, Port 0 Link: Latency L0s <4us, L1 <16us Link: ASPM Disabled CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x8 Capabilities: [54] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=02:00.1 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=32 CommitmentLimit=32 Downstream: Capacity=16 CommitmentLimit=16 Capabilities: [64] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=55mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ 00: 33 10 25 01 04 01 10 00 07 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 02 04 04 40 f1 01 20 24 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 07 00

4 3

r1116 - coreboot-v3/include/arch/x86/arch
by svn＠coreboot.org 15 Jan '09

15 Jan '09

Author: rminnich Date: 2009-01-15 17:56:44 +0100 (Thu, 15 Jan 2009) New Revision: 1116 Added: coreboot-v3/include/arch/x86/arch/atomic.h Log: Right from Linux. I am not comfortable inserting our headers in linux files. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: coreboot-v3/include/arch/x86/arch/atomic.h =================================================================== --- coreboot-v3/include/arch/x86/arch/atomic.h (rev 0) +++ coreboot-v3/include/arch/x86/arch/atomic.h 2009-01-15 16:56:44 UTC (rev 1116) @@ -0,0 +1,70 @@ +/* this implementation is from Linux. */ +#ifndef ARCH_ATOMIC_H +#define ARCH_ATOMIC_H + +/* + * Make sure gcc doesn't try to be clever and move things around + * on us. We need to use _exactly_ the address the user gave us, + * not some alias that contains the same information. + */ +struct atomic { volatile int counter; }; + +#define ATOMIC_INIT(i) { (i) } + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +/** + * atomic_read - read atomic variable + * @v: pointer of type struct atomic + * + * Atomically reads the value of @v. Note that the guaranteed + * useful range of an struct atomic is only 24 bits. + */ +#define atomic_read(v) ((v)->counter) + +/** + * atomic_set - set atomic variable + * @v: pointer of type struct atomic + * @i: required value + * + * Atomically sets the value of @v to @i. Note that the guaranteed + * useful range of an struct atomic is only 24 bits. + */ +#define atomic_set(v,i) (((v)->counter) = (i)) + +/** + * atomic_inc - increment atomic variable + * @v: pointer of type struct atomic + * + * Atomically increments @v by 1. Note that the guaranteed + * useful range of an struct atomic is only 24 bits. + */ +static __inline__ __attribute__((always_inline)) void atomic_inc(struct atomic *v) +{ + __asm__ __volatile__( + "lock ; incl %0" + :"=m" (v->counter) + :"m" (v->counter)); +} + +/** + * atomic_dec - decrement atomic variable + * @v: pointer of type struct atomic + * + * Atomically decrements @v by 1. Note that the guaranteed + * useful range of an struct atomic is only 24 bits. + */ +static __inline__ __attribute__((always_inline)) void atomic_dec(struct atomic *v) +{ + __asm__ __volatile__( + "lock ; decl %0" + :"=m" (v->counter) + :"m" (v->counter)); +} + + + +#endif /* ARCH_ATOMIC_H */

1 0

patch: atomic.h
by ron minnich 15 Jan '09

15 Jan '09

attached. ron

3 2

Trac reminder: list of new ticket(s)
by coreboot tracker 15 Jan '09

15 Jan '09

1 0

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coreboot January 2009