coreboot May 2008

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r3334 build service
by coreboot information 19 May '08

19 May '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3334 to the coreboot source repository and caused the following changes: Change Log: Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R. This also contains various improvements of the CN700 code in svn. Signed-off-by: Aaron Lwe <aaron.lwe(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3334&device=epia-cn&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3334 - in trunk/coreboot-v2: src/mainboard/via src/mainboard/via/epia-cn src/northbridge/via/cn700 targets/via targets/via/epia-cn
by svn＠coreboot.org 19 May '08

19 May '08

Author: uwe Date: 2008-05-19 14:17:43 +0200 (Mon, 19 May 2008) New Revision: 3334 Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c trunk/coreboot-v2/targets/via/epia-cn/ trunk/coreboot-v2/targets/via/epia-cn/Config.lb Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c Log: Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R. This also contains various improvements of the CN700 code in svn. Signed-off-by: Aaron Lwe <aaron.lwe(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,142 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE object irq_tables.o end +if HAVE_MP_TABLE object mptable.o end +if HAVE_ACPI_TABLES + object fadt.o + object dsdt.o + object acpi_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc +dir /pc80 +config chip.h + +chip northbridge/via/cn700 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + device pci f.0 on end # IDE + register "fn_ctrl_lo" = "0x8a" + register "fn_ctrl_hi" = "0x9d" + device pci 10.0 on end # USB 1.1 + device pci 10.1 on end # USB 1.1 + device pci 10.2 on end # USB 1.1 + device pci 10.3 on end # USB 1.1 + device pci 11.0 on # Southbridge LPC + chip superio/via/vt1211 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end # Ethernet + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,108 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses HAVE_ACPI_TABLES +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_PCI_ROM_RUN +uses CONFIG_CONSOLE_VGA +uses CONFIG_MAX_PCI_BUSES +uses TTYS0_BAUD +uses CONFIG_CHIP_NAME +uses CONFIG_VIDEO_MB +uses CONFIG_IOAPIC + +default ROM_SIZE = 512 * 1024 +default CONFIG_IOAPIC = 0 +default CONFIG_VIDEO_MB = 32 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_CONSOLE_VGA = 0 +default CONFIG_CHIP_NAME = 1 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_HARD_RESET = 0 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 10 +default HAVE_ACPI_TABLES = 0 +default HAVE_OPTION_TABLE = 1 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = ROM_SIZE +default USE_FALLBACK_IMAGE = 1 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" + +## +## Set this to the max PCI bus number you would ever use for PCI config I/O. +## Setting this number very high will make pci_locate_device() take a long +## time when it can't find a device. +## +default CONFIG_MAX_PCI_BUSES = 3 + +end + Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/via/cn700/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8235/vt8235_early_serial.c" + +static void memreset_setup(void) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/via/cn700/raminit.c" + +static void enable_mainboard_devices(void) +{ + device_t dev; + u8 reg; + + /* + * If I enable SATA, FILO will not find the IDE disk, so I'll disable + * SATA here. To not conflict with PCI spec, I'll move IDE device + * from 00:0f.1 to 00:0f.0. + */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT6420_SATA), 0); + if (dev != PCI_DEV_INVALID) { + /* Enable PATA. */ + reg = pci_read_config8(dev, 0xd1); + reg |= 0x08; + pci_write_config8(dev, 0xd1, reg); + reg = pci_read_config8(dev, 0x49); + reg |= 0x80; + pci_write_config8(dev, 0x49, reg); + } else { + print_debug("No SATA device\r\n"); + } + + /* Disable SATA, and PATA device will be 00:0f.0. */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Southbridge not found!!!\r\n"); + reg = pci_read_config8(dev, 0x50); + reg |= 0x08; + pci_write_config8(dev, 0x50, reg); +} + +static const struct mem_controller ctrl = { + .d0f0 = 0x0000, + .d0f2 = 0x2000, + .d0f3 = 0x3000, + .d0f4 = 0x4000, + .d0f7 = 0x7000, + .d1f0 = 0x8000, + .channel0 = { 0x50 }, +}; + +static void main(unsigned long bist) +{ + unsigned long x; + device_t dev; + + /* Enable multifunction for northbridge. */ + pci_write_config8(ctrl.d0f0, 0x4f, 0x01); + + enable_vt8235_serial(); + uart_init(); + console_init(); + + print_spew("In auto.c:main()\r\n"); + + enable_smbus(); + smbus_fixup(&ctrl); + + if (bist == 0) { + print_debug("doing early_mtrr\r\n"); + early_mtrr_init(); + } + + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + print_debug("Enabling mainboard devices\r\n"); + enable_mainboard_devices(); + + ddr_ram_setup(&ctrl); + + /* ram_check(0, 640 * 1024); */ + + print_spew("Leaving auto.c:main()\r\n"); +} Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_via_epia_cn_ops; + +struct mainboard_via_epia_cn_config { + int nothing; +}; Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x11 << 3) | 0x0, /* Interrupt router device */ + 0x828, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x596, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3e, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_via_epia_cn_ops = { + CHIP_NAME("VIA EPIA-CN Mainboard") +}; Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2008-05-17 21:33:35 UTC (rev 3333) +++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2008-05-19 12:17:43 UTC (rev 3334) @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -34,10 +36,12 @@ static void memctrl_init(device_t dev) { + device_t vlink_dev; u16 reg16; + u8 ranks; + u8 pagec, paged, pagee, pagef; + u8 shadowreg; - pci_write_config8(dev, 0x86, 0x2d); - /* Set up the vga framebuffer size */ reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15); pci_write_config16(dev, 0xa0, reg16); @@ -45,8 +49,41 @@ /* Set up VGA timers */ pci_write_config8(dev, 0xa2, 0x44); - pci_write_config16(dev, 0xb0, 0xaa60); + for (ranks = 0x4b; ranks >= 0x48; ranks--) { + if (pci_read_config8(dev, ranks)) { + ranks -= 0x48; + break; + } + } + if (ranks == 0x47) + ranks = 0x00; + reg16 = 0xaae0; + reg16 |= ranks; + /* GMINT Misc. FrameBuffer rank */ + pci_write_config16(dev, 0xb0, reg16); + /* AGPCINT Misc. */ pci_write_config8(dev, 0xb8, 0x08); + + /* shadown ram */ + pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30; + /* PAGE C, D, E are all read write enable */ + pci_write_config8(dev, 0x80, pagec); + pci_write_config8(dev, 0x81, paged); + pci_write_config8(dev, 0x82, pagee); + /* PAGE F are read/writable */ + shadowreg = pci_read_config8(dev, 0x83); + shadowreg |= pagef; + pci_write_config8(dev, 0x83, shadowreg); + /* vlink mirror */ + vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_VLINK, 0); + if (vlink_dev) { + pci_write_config8(vlink_dev, 0x61, pagec); + pci_write_config8(vlink_dev, 0x62, paged); + pci_write_config8(vlink_dev, 0x64, pagee); + shadowreg = pci_read_config8(vlink_dev, 0x63); + shadowreg |= pagef; + pci_write_config8(vlink_dev, 0x63, shadowreg); + } } static const struct device_operations memctrl_operations = { @@ -124,7 +161,10 @@ static void pci_domain_set_resources(device_t dev) { - static const u8 ramregs[] = {0x40, 0x41, 0x42, 0x43}; + /* + * the order is important to find the correct ram size. + */ + static const u8 ramregs[] = {0x43, 0x42, 0x41, 0x40}; device_t mc_dev; u32 pci_tolm; @@ -133,19 +173,25 @@ pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); - + if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; int i, idx; + /* + * once the register value is not zero, the ramsize is + * this register's value multiply 64 * 1024 * 1024 + */ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; - reg = pci_read_config8(mc_dev, ramregs[i]); - rambits += reg; + rambits = pci_read_config8(mc_dev, ramregs[i]); + if (rambits != 0) + break; } - tomk = rambits; + tomk = rambits * 64 * 1024; + printk_spew("tomk is 0x%x\n", tomk); /* Compute the Top Of Low Memory, in Kb */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { @@ -156,16 +202,15 @@ idx = 10; /* TODO: Hole needed? */ ram_resource(dev, idx++, 0, 640); /* first 640k */ - /* Leave a hole for vga */ - ram_resource(dev, idx++, 768, (tolmk - 768 - - (CONFIG_VIDEO_MB * 1024))); + /* Leave a hole for vga, 0xa0000 - 0xc0000 */ + ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } assign_resources(&dev->link[0]); } static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) { - printk_spew("Entering cn700 pci_domain_scan_bus.\n"); + printk_debug("Entering cn700 pci_domain_scan_bus.\n"); max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); return max; Modified: trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c 2008-05-17 21:33:35 UTC (rev 3333) +++ trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c 2008-05-19 12:17:43 UTC (rev 3334) @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -39,7 +41,7 @@ #define DUMPNORTH() #endif -static void do_ram_command(device_t dev, u8 command, u32 addr_offset) +static void do_ram_command(device_t dev, u8 command) { u8 reg; @@ -55,11 +57,8 @@ PRINT_DEBUG_MEM(" to 0x"); PRINT_DEBUG_MEM_HEX32(0 + addr_offset); PRINT_DEBUG_MEM("\r\n"); - - read32(0 + addr_offset); } - /** * Configure the bus between the cpu and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers @@ -83,7 +82,7 @@ /* Arbitration */ pci_write_config8(dev, 0x53, 0x88); /* Miscellaneous Control */ - pci_write_config8(dev, 0x54, 0x10); + pci_write_config8(dev, 0x54, 0x1e); pci_write_config8(dev, 0x55, 0x16); /* Write Policy */ pci_write_config8(dev, 0x56, 0x01); @@ -93,9 +92,8 @@ * 010 : 166MHz 011 : 200MHz * 100 : 266MHz 101 : 333MHz * 110/111 : Reserved */ - //pci_write_config8(dev, 0x57, 0x60);//set 200MHz dram clock /* CPU Miscellaneous Control */ - pci_write_config8(dev, 0x59, 0x60); + pci_write_config8(dev, 0x59, 0x44); /* Write Policy */ pci_write_config8(dev, 0x5d, 0xb2); /* Bandwidth Timer */ @@ -113,16 +111,16 @@ pci_write_config8(dev, 0x65, 0x0f); /* Read Line Burst DRDY# Timing Control */ pci_write_config8(dev, 0x66, 0xff); - pci_write_config8(dev, 0x67, 0x70); + pci_write_config8(dev, 0x67, 0x30); /* Host Bus IO Circuit (See datasheet) */ /* Host Address Pullup/down Driving */ - pci_write_config8(dev, 0x70, 0x33); - pci_write_config8(dev, 0x71, 0x00); - pci_write_config8(dev, 0x72, 0x33); - pci_write_config8(dev, 0x73, 0x00); + pci_write_config8(dev, 0x70, 0x11); + pci_write_config8(dev, 0x71, 0x11); + pci_write_config8(dev, 0x72, 0x11); + pci_write_config8(dev, 0x73, 0x11); /* Miscellaneous Control */ - pci_write_config8(dev, 0x74, 0x00); + pci_write_config8(dev, 0x74, 0x35); /* AGTL+ I/O Circuit */ pci_write_config8(dev, 0x75, 0x28); /* AGTL+ Compensation Status */ @@ -135,239 +133,330 @@ pci_write_config8(dev, 0x79, 0xaa); /* Address Strobe Input Delay Control */ pci_write_config8(dev, 0x7a, 0x24); - /* Address CKG Rising/Falling Time Control */ - pci_write_config8(dev, 0x7b, 0x00); + // Address CKG Rising/Falling Time Control + pci_write_config8(dev, 0x7b, 0xaa); /* Address CKG Clock Rising/Falling Time Control */ pci_write_config8(dev, 0x7c, 0x00); /* Undefined (can't remember why I did this) */ - pci_write_config8(dev, 0x7d, 0x6d); + pci_write_config8(dev, 0x7d, 0x6d); + pci_write_config8(dev, 0x7e, 0x00); + pci_write_config8(dev, 0x7f, 0x00); + pci_write_config8(dev, 0x80, 0x1b); + pci_write_config8(dev, 0x81, 0x0a); + pci_write_config8(dev, 0x82, 0x0a); + pci_write_config8(dev, 0x83, 0x0a); } /** + * Set up dram size according to spd data. Eventually, DRAM timings should be + * done in a similar manner. + * + * @param ctrl The northbridge devices and spd addresses. + */ +static void sdram_set_size(const struct mem_controller *ctrl) +{ + u8 density, ranks, result, col; + + ranks = spd_read_byte(ctrl->channel0[0], SPD_NUM_DIMM_BANKS); + ranks = (ranks & 0x07) + 1; + density = spd_read_byte(ctrl->channel0[0], SPD_DENSITY_OF_EACH_ROW_ON_MODULE); + switch (density) + { + case 0x80: + result = 0x08; /* 512MB / 64MB = 0x08 */ + break; + case 0x40: + result = 0x04; + break; + case 0x20: + result = 0x02; + break; + case 0x10: + result = 0xff; /* 16GB */ + break; + case 0x08: + result = 0xff; /* 8GB */ + break; + case 0x04: + result = 0xff; /* 4GB */ + break; + case 0x02: + result = 0x20; /* 2GB */ + break; + case 0x01: + result = 0x10; /* 1GB */ + break; + } + + if (result == 0xff) + die("dram module size too big, not supported by cn700\r\n"); + + pci_write_config8(ctrl->d0f3, 0x40, result); + pci_write_config8(ctrl->d0f3, 0x48, 0x00); + if (ranks == 2) { + pci_write_config8(ctrl->d0f3, 0x41, result * ranks); + pci_write_config8(ctrl->d0f3, 0x49, result); + } + /* size mirror */ + pci_write_config8(ctrl->d0f7, 0xe5, (result * ranks) << 2); + pci_write_config8(ctrl->d0f7, 0x57, (result * ranks) << 2); + /* Low Top Address */ + pci_write_config8(ctrl->d0f3, 0x84, 0x00); + pci_write_config8(ctrl->d0f3, 0x85, (result * ranks) << 2); + pci_write_config8(ctrl->d0f3, 0x88, (result * ranks) << 2); + + /* Physical-Virtual Mapping */ + if (ranks == 2) + pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4 | 1 << 3 | 1 << 0); + if (ranks == 1) + pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4); + pci_write_config8(ctrl->d0f3, 0x55, 0x00); + /* virtual rank interleave, disable */ + pci_write_config32(ctrl->d0f3, 0x58, 0x00); + + /* MA Map Type */ + result = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM); + if (result == 8) { + col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS); + switch (col) + { + case 10: + pci_write_config8(ctrl->d0f3, 0x50, 0xa0); + break; + case 11: + pci_write_config8(ctrl->d0f3, 0x50, 0xc0); + break; + case 12: + pci_write_config8(ctrl->d0f3, 0x50, 0xe0); + break; + } + } + else if (result == 4) { + col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS); + switch (col) + { + case 9: + pci_write_config8(ctrl->d0f3, 0x50, 0x00); + break; + case 10: + pci_write_config8(ctrl->d0f3, 0x50, 0x20); + break; + case 11: + pci_write_config8(ctrl->d0f3, 0x50, 0x40); + break; + case 12: + pci_write_config8(ctrl->d0f3, 0x50, 0x60); + break; + } + } + pci_write_config8(ctrl->d0f3, 0x51, 0x00); +} + +/** * Set up various ram and other control registers statically. Some of these may * not be needed, other should be done with spd info, but that's a project for * the future */ static void sdram_set_registers(const struct mem_controller *ctrl) { + u8 reg; + + /* Set WR=5 */ + pci_write_config8(ctrl->d0f3, 0x61, 0xe0); + /* Set CAS=4 */ + pci_write_config8(ctrl->d0f3, 0x62, 0xfa); + /* dram timing-3 */ + pci_write_config8(ctrl->d0f3, 0x63, 0xca); + /* dram timing-4 */ + pci_write_config8(ctrl->d0f3, 0x64, 0xcc); + /* DIMM command / Address Selection */ + pci_write_config8(ctrl->d0f3, 0x67, 0x00); + /* Disable cross bank/multi page mode */ + pci_write_config8(ctrl->d0f3, 0x69, 0x00); + /* disable refresh now */ + pci_write_config8(ctrl->d0f3, 0x6a, 0x00); + + /* frequency 100MHZ */ + pci_write_config8(ctrl->d0f3, 0x90, 0x00); + pci_write_config8(ctrl->d0f2, 0x57, 0x18); + /* Allow manual dll reset */ + pci_write_config8(ctrl->d0f3, 0x6b, 0x10); + + /* Bank/Rank Interleave Address Select */ + pci_write_config8(ctrl->d0f3, 0x52, 0x33); + pci_write_config8(ctrl->d0f3, 0x53, 0x3f); + + /* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */ + pci_write_config8(ctrl->d0f3, 0x6c, 0xc8); + + /* DRAM Bus Turn-Around Setting */ + pci_write_config8(ctrl->d0f3, 0x60, 0x03); + /* DRAM Arbitration Control */ + pci_write_config8(ctrl->d0f3, 0x66, 0x80); + /* DQS Tuning: testing on a couple different boards has shown this is + * static, or close enough that it can be. Which is good, because the + * tuning function used too many registers + */ + /* DQS Output Delay for CHannel A */ + pci_write_config8(ctrl->d0f3, 0x70, 0x00); + /* MD Output Delay for Channel A */ + pci_write_config8(ctrl->d0f3, 0x71, 0x01); + pci_write_config8(ctrl->d0f3, 0x73, 0x01); + + /* dram arbitration timer */ + pci_write_config8(ctrl->d0f3, 0x65, 0xd9); + + /* dram signal timing control */ + pci_write_config8(ctrl->d0f3, 0x74, 0x01); + pci_write_config8(ctrl->d0f3, 0x75, 0x01); + pci_write_config8(ctrl->d0f3, 0x76, 0x06); + pci_write_config8(ctrl->d0f3, 0x77, 0x92); + pci_write_config8(ctrl->d0f3, 0x78, 0x83); + pci_write_config8(ctrl->d0f3, 0x79, 0x83); + pci_write_config8(ctrl->d0f3, 0x7a, 0x00); + pci_write_config8(ctrl->d0f3, 0x7b, 0x10); + + /* dram clocking control */ + pci_write_config8(ctrl->d0f3, 0x91, 0x01); + /* CS/CKE Clock Phase Control */ + pci_write_config8(ctrl->d0f3, 0x92, 0x02); + /* SCMD/MA Clock Phase Control */ + pci_write_config8(ctrl->d0f3, 0x93, 0x02); + /* DCLKO Feedback Mode Output Control */ + pci_write_config8(ctrl->d0f3, 0x94, 0x00); + pci_write_config8(ctrl->d0f3, 0x9d, 0x0f); + + /* SDRAM ODT Control */ + pci_write_config8(ctrl->d0f3, 0xda, 0x80); + /* Channel A DQ/DQS CKG Output Delay Control */ + pci_write_config8(ctrl->d0f3, 0xdc, 0x54); + /* Channel A DQ/DQS CKG Output Delay Control */ + pci_write_config8(ctrl->d0f3, 0xdd, 0x55); + /* odt lookup table */ + pci_write_config8(ctrl->d0f3, 0xd8, 0x01); + pci_write_config8(ctrl->d0f3, 0xd9, 0x0a); + + /* ddr sdram control */ + pci_write_config8(ctrl->d0f3, 0x6d, 0xc0); + pci_write_config8(ctrl->d0f3, 0x6f, 0x41); + /* DQ/DQS Strength Control */ - pci_write_config8(ctrl->d0f3, 0xd0, 0x88); - pci_write_config8(ctrl->d0f3, 0xd1, 0x8b); - pci_write_config8(ctrl->d0f3, 0xd2, 0x89); - /* SMM and APIC Decoding */ - pci_write_config8(ctrl->d0f3, 0x86, 0x2d); - - /* Driving selection */ - /* DQ / DQS ODT Driving and Range Select */ + pci_write_config8(ctrl->d0f3, 0xd0, 0xaa); + + /* Compensation Control */ + pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /*enable auto compensation*/ + /* ODT (some are set with driving select above) */ + pci_write_config8(ctrl->d0f3, 0xd4, 0x80); pci_write_config8(ctrl->d0f3, 0xd5, 0x8a); /* Memory Pads Driving and Range Select */ pci_write_config8(ctrl->d0f3, 0xd6, 0xaa); - /* DRAM Driving – Group DQS */ + pci_write_config8(ctrl->d0f3, 0xe0, 0xee); - /* DRAM Driving – Group DQ (DQ, MPD, DQM) */ - pci_write_config8(ctrl->d0f3, 0xe2, 0xac);//ba - /* DRAM Driving – Group CS */ + pci_write_config8(ctrl->d0f3, 0xe2, 0xac); pci_write_config8(ctrl->d0f3, 0xe4, 0x66); - /* DRAM Driving – Group MA */ + pci_write_config8(ctrl->d0f3, 0xe6, 0x33); pci_write_config8(ctrl->d0f3, 0xe8, 0x86); - /* DRAM Driving – Group MCLK */ - pci_write_config8(ctrl->d0f3, 0xe6, 0xaa); - - /* ODT (some are set with driving select above) */ - /* Memory Pad ODT Pullup / Pulldown Control */ - pci_write_config8(ctrl->d0f3, 0xd4, 0x0a); - /* Memory Ranks ODT Lookup Table */ - pci_write_config8(ctrl->d0f3, 0xd8, 0x00);//was 1 - /* Compensation Control */ - pci_write_config8(ctrl->d0f3, 0xd3, 0x89);//enable auto compensation - - /* MCLKO Phase Control */ - pci_write_config8(ctrl->d0f3, 0x91, 0x02); - /* CS/CKE Clock Phase Control */ - pci_write_config8(ctrl->d0f3, 0x92, 0x06); - /* SCMD/MA Clock Phase Control */ - pci_write_config8(ctrl->d0f3, 0x93, 0x07); - /* Channel A DQS Input Capture Range Control */ - pci_write_config8(ctrl->d0f3, 0x78, 0x83); - /* DQS Input Capture Range Control */ - /* Set in accordance with the BIOS update note */ - pci_write_config8(ctrl->d0f3, 0x7a, 0x00); - /* DQS Input Delay Offset Control */ - pci_write_config8(ctrl->d0f3, 0x7c, 0x00); - /* SDRAM ODT Control */ - pci_write_config8(ctrl->d0f3, 0xda, 0x80); - /* DQ/DQS CKG Output Delay Control - I */ - pci_write_config8(ctrl->d0f3, 0xdc, 0xff); - /* DQ/DQS CKG Output Delay Control - II */ - pci_write_config8(ctrl->d0f3, 0xdd, 0xff); /* DQS / DQ CKG Duty Cycle Control */ - pci_write_config8(ctrl->d0f3, 0xec, 0x88); + pci_write_config8(ctrl->d0f3, 0xec, 0x00); /* MCLK Output Duty Control */ pci_write_config8(ctrl->d0f3, 0xee, 0x00); - pci_write_config8(ctrl->d0f3, 0xed, 0x10); /* DQS CKG Input Delay Control */ pci_write_config8(ctrl->d0f3, 0xef, 0x10); - - pci_write_config8(ctrl->d0f3, 0x77, 0x9d); - pci_write_config8(ctrl->d0f3, 0x79, 0x83); - pci_write_config16(ctrl->d0f3, 0x88, 0x0020); - pci_write_config8(ctrl->d0f4, 0xa7, 0x80); + /* dram duty control */ + pci_write_config8(ctrl->d0f3, 0xed, 0x10); - /* VLink Control */ - pci_write_config8(ctrl->d0f7, 0xb0, 0x05); - pci_write_config8(ctrl->d0f7, 0xb1, 0x01); - - /* Memory base */ - pci_write_config16(ctrl->d1f0, 0x20, 0xfb00); - /* Memory limit */ - pci_write_config16(ctrl->d1f0, 0x22, 0xfcf0); - /* Prefetch memory base */ - pci_write_config16(ctrl->d1f0, 0x24, 0xf400); - /* Prefetch memory limit */ - pci_write_config16(ctrl->d1f0, 0x26, 0xf7f0); - /* PCI to PCI bridge control */ - pci_write_config16(ctrl->d1f0, 0x3e, 0x0008); - - /* CPU to PCI flow control 1 */ - pci_write_config8(ctrl->d1f0, 0x40, 0x83); - pci_write_config8(ctrl->d1f0, 0x41, 0xc3);//clear reset error, set to 43 - pci_write_config8(ctrl->d1f0, 0x42, 0xe2); - pci_write_config8(ctrl->d1f0, 0x43, 0x44); - pci_write_config8(ctrl->d1f0, 0x44, 0x34); - pci_write_config8(ctrl->d1f0, 0x45, 0x72); + /* SMM and APIC deocoding, we donot use SMM */ + reg = 0x29; + pci_write_config8(ctrl->d0f3, 0x86, reg); + /* SMM and APIC decoding mirror */ + pci_write_config8(ctrl->d0f7, 0xe6, reg); - /* Disable cross bank/multi page mode */ - pci_write_config8(ctrl->d0f3, DDR_PAGE_CTL, 0x80); - pci_write_config8(ctrl->d0f3, DRAM_REFRESH_COUNTER, 0x00); - - /* Set WR=5 and RFC */ - pci_write_config8(ctrl->d0f3, 0x61, 0xc7); - /* Set CAS=5 */ - pci_write_config8(ctrl->d0f3, 0x62, 0xaf); - pci_write_config8(ctrl->d0f3, 0x63, 0xca); - /* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */ - pci_write_config8(ctrl->d0f3, 0x6c, 0xc8); - /* Allow manual dll reset */ - pci_write_config8(ctrl->d0f3, 0x6b, 0x10); - + /* dram module configuration */ pci_write_config8(ctrl->d0f3, 0x6e, 0x89); - pci_write_config8(ctrl->d0f3, 0x67, 0x50); - pci_write_config8(ctrl->d0f3, 0x65, 0xd9); - - /* Only enable bank 1, for now */ - /* TODO: Multiple, dynamically controlled bank enables */ - pci_write_config8(ctrl->d0f3, 0x54, 0x80); - pci_write_config8(ctrl->d0f3, 0x55, 0x00); - - /* Set to 2T, MA Map type 1. - * TODO: Needs to become dynamic */ - pci_write_config16(ctrl->d0f3, 0x50, 0x0020); +} - /* BA0-2 Selection. Don't mess with */ - pci_write_config8(ctrl->d0f3, 0x52, 0x33); - pci_write_config8(ctrl->d0f3, 0x53, 0x3f); - - /* Disable bank interleaving. This feature seems useless anyways */ - pci_write_config32(ctrl->d0f3, 0x58, 0x00000000); - pci_write_config8(ctrl->d0f3, 0x88, 0x08); +static void sdram_set_post(const struct mem_controller *ctrl) +{ + device_t dev = ctrl->d0f3; + /* Enable multipage mode. */ + pci_write_config8(dev, 0x69, 0x03); - /* Some DQS control stuffs */ - pci_write_config8(ctrl->d0f3, 0x74, 0x04); - pci_write_config8(ctrl->d0f3, 0x75, 0x04); - pci_write_config8(ctrl->d0f3, 0x76, 0x00); -} + /* Enable refresh. */ + pci_write_config8(dev, 0x6a, 0x32); -/** - * Set up dram size according to spd data. Eventually, DRAM timings should be - * done in a similar manner. - * - * @param ctrl The northbridge devices and spd addresses. - */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - u8 spd_data, spd_data2; + // vga device + pci_write_config16(dev, 0xa0, (1 <<15)); + pci_write_config16(dev, 0xa4, 0x0010); - /* DRAM Bank Size */ - spd_data = spd_read_byte(ctrl->channel0[0], - SPD_DENSITY_OF_EACH_ROW_ON_MODULE); - /* I know this seems weird. Blame JEDEC/Via. */ - if(spd_data >= 0x10) - spd_data = spd_data >> 1; - else - spd_data = spd_data << 1; - - /* Check for double sided dimm and adjust size accordingly */ - spd_data2 = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM); - /* There should be 4 banks on a single sided dimm, - * or 8 on a dual sided one */ - spd_data = spd_data * (spd_data2 / 4); - pci_write_config8(ctrl->d0f3, 0x40, spd_data); - /* TODO: The rest of the DIMMs */ } -static void sdram_enable(device_t dev) +static void sdram_enable(device_t dev, unsigned long rank_address) { - int i; + u8 i; /* 1. Apply NOP. */ PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n"); - do_ram_command(dev, RAM_COMMAND_NOP, 0); - udelay(200); + do_ram_command(dev, RAM_COMMAND_NOP); + udelay(100); + read32(rank_address + 0x10); /* 2. Precharge all. */ + udelay(400); PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); - do_ram_command(dev, RAM_COMMAND_PRECHARGE, 0); + do_ram_command(dev, RAM_COMMAND_PRECHARGE); + read32(rank_address + 0x10); /* 3. Mode register set. */ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); - do_ram_command(dev, RAM_COMMAND_MRS, 0x2000);//enable dll - do_ram_command(dev, RAM_COMMAND_MRS, 0x800);//reset dll + do_ram_command(dev, RAM_COMMAND_MRS); + read32(rank_address + 0x120000);// EMRS DLL Enable + read32(rank_address + 0x800); // MRS DLL Reset /* 4. Precharge all again. */ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); - do_ram_command(dev, RAM_COMMAND_PRECHARGE, 0); + do_ram_command(dev, RAM_COMMAND_PRECHARGE); + read32(rank_address + 0x0); /* 5. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n"); - do_ram_command(dev, RAM_COMMAND_CBR, 0); - /* First read is actually done by do_ram_command */ - for(i = 0; i < 7; i++) { + do_ram_command(dev, RAM_COMMAND_CBR); + for(i = 0; i < 8; i++) { + read32(rank_address + 0x20); udelay(100); - read32(0); } /* 6. Mode register set. */ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); - //safe value for now, BL=8, WR=5, CAS=5 + //safe value for now, BL=8, WR=5, CAS=4 /* (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ - do_ram_command(dev, RAM_COMMAND_MRS, 0x0022d8); + do_ram_command(dev, RAM_COMMAND_MRS); + read32(rank_address + 0x002258); // MRS command + read32(rank_address + 0x121c20); // EMRS OCD Default + read32(rank_address + 0x120020); // EMRS OCD Calibration Mode Exit - /* 7. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); - do_ram_command(dev, RAM_COMMAND_MRS, 0x21c20);//default OCD calibration - do_ram_command(dev, RAM_COMMAND_MRS, 0x20020);//exit calibration mode - /* 8. Normal operation */ PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); - do_ram_command(dev, RAM_COMMAND_NORMAL, 0); - - /* Enable multipage mode. */ - pci_write_config8(dev, DDR_PAGE_CTL, 0x83); - /* Enable refresh. */ - pci_write_config8(dev, DRAM_REFRESH_COUNTER, 0x32); - - /* DQS Tuning: testing on a couple different boards has shown this is - * static, or close enough that it can be. Which is good, because the - * tuning function used too many registers. */ - pci_write_config8(dev, CH_A_DQS_OUTPUT_DELAY, 0x00); - pci_write_config8(dev, CH_A_MD_OUTPUT_DELAY, 0x03); + do_ram_command(dev, RAM_COMMAND_NORMAL); + read32(rank_address + 0x30); +} - /* Enable VGA device with no memory, add memory later. We need this - * here to enable the actual device, otherwise it won't show up until - * later and LB will have a fit. */ - pci_write_config16(dev, 0xa0, (1 << 15)); - pci_write_config16(dev, 0xa4, 0x0010); +/* + * Support one dimm with up to 2 ranks + */ +static void ddr_ram_setup(const struct mem_controller *ctrl) +{ + u8 reg; + + c7_cpu_setup(ctrl->d0f2); + sdram_set_registers(ctrl); + sdram_set_size(ctrl); + sdram_enable(ctrl->d0f3, 0); + reg = pci_read_config8(ctrl->d0f3, 0x41); + if (reg != 0) + sdram_enable(ctrl->d0f3, pci_read_config8(ctrl->d0f3, 0x40) << 26); + sdram_set_post(ctrl); } + Added: trunk/coreboot-v2/targets/via/epia-cn/Config.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-cn/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/via/epia-cn/Config.lb 2008-05-19 12:17:43 UTC (rev 3334) @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target via_epia_cn +mainboard via/epia-cn + +# +# Generate the final ROM like this: +# cat vgabios bochsbios coreboot.rom > coreboot.rom.final +# +option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024) + +romimage "image" + option COREBOOT_EXTRA_VERSION = "-epiacn" + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "image"

1 0

Thomson IP1000 Full Bootlog
by Joseph Smith 18 May '08

18 May '08

Here is a Full Bootlog of the Thomson IP1000 for the Wiki. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org --------------------------------------------- coreboot-2.0.0_RM4100 Wed May 14 19:50:46 EDT 2008 starting... Setting initial registers.... Initial registers have been set. No DIMM found in slot 00 DRB 0x60 has been set to 0x00 DRB1 0x61 has been set to 0x00 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x02 DRB3 0x63 has been set to 0x02 No DIMM found in slot 00, setting DRA to 0xFF DRA 0x70 has been set to 0xff Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command 0x00000010 to 0x00000000 RAM Enable 2: Precharge all Sending RAM command 0x00000020 to 0x00000000 RAM Enable 3: CBR Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 RAM Enable 4: Mode register set Sending RAM command 0x00000030 to 0x000001d0 RAM Enable 5: Normal operation Sending RAM command 0x20000270 to 0x00000000 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 20 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 00 00 02 02 02 02 00 00 00 00 00 00 00 00 00 00 70: ff f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c d0 21 cd 1d cc Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0_RM4100 Wed May 14 19:50:46 EDT 2008 booting... end 85599ec0, start 0 32-bit delta 1826 calibrate_tsc 32-bit result is 1826 clocks_per_usec: 1826 Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/3575] ops PCI: 00:00.0 [8086/3575] enabled PCI: devfn 0x8, bad id 0xffffffff PCI: 00:02.0 [8086/3577] enabled PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: 00:1d.0 [8086/24c2] ops PCI: 00:1d.0 [8086/24c2] enabled PCI: 00:1d.1 [8086/24c4] ops PCI: 00:1d.1 [8086/24c4] enabled PCI: 00:1d.2 [8086/24c7] ops PCI: 00:1d.2 [8086/24c7] enabled PCI: devfn 0xeb, bad id 0xffffffff PCI: devfn 0xec, bad id 0xffffffff PCI: devfn 0xed, bad id 0xffffffff PCI: devfn 0xee, bad id 0xffffffff PCI: 00:1d.7 [8086/24cd] ops PCI: 00:1d.7 [8086/24cd] enabled PCI: 00:1e.0 [8086/244e] bus ops PCI: 00:1e.0 [8086/244e] enabled PCI: 00:1f.0 [8086/24c0] bus ops PCI: 00:1f.0 [8086/24c0] enabled PCI: 00:1f.1 [8086/24cb] ops PCI: 00:1f.1 [8086/24cb] enabled PCI: devfn 0xfa, bad id 0xffffffff PCI: 00:1f.3 [8086/24c3] enabled PCI: devfn 0xfc, bad id 0xffffffff PCI: 00:1f.5 [8086/24c5] ops PCI: 00:1f.5 [8086/24c5] enabled PCI: 00:1f.6 [8086/24c6] ops PCI: 00:1f.6 [8086/24c6] enabled PCI: devfn 0xff, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 01 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: 01:08.0 [8086/103a] ops PCI: 01:08.0 [8086/103a] enabled PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:1f.0 Found SMSC Super I/O (ID=0x60, rev=0x01) PNP: 002e.0 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.7 enabled PNP: 002e.9 disabled PNP: 002e.a enabled PNP: 002e.b disabled scan_static_bus for PCI: 00:1f.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:1e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:08.0 14 * [0x00000000 - 0x0000003f] io PCI: 00:1e.0 compute_allocate_io: base: 00000040 size: 00001000 align: 12 gran: 12 done PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:08.0 10 * [0x00000000 - 0x00000fff] mem PCI: 00:1e.0 compute_allocate_mem: base: 00001000 size: 00100000 align: 20 gran: 20 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io PCI: 00:1d.0 20 * [0x000028c0 - 0x000028df] io PCI: 00:1d.1 20 * [0x000028e0 - 0x000028ff] io PCI: 00:1d.2 20 * [0x00002c00 - 0x00002c1f] io PCI: 00:1f.3 20 * [0x00002c20 - 0x00002c3f] io PCI: 00:1f.1 20 * [0x00002c40 - 0x00002c4f] io PCI: 00:1f.1 10 * [0x00002c50 - 0x00002c57] io PCI: 00:1f.1 18 * [0x00002c60 - 0x00002c67] io PCI: 00:1f.1 14 * [0x00002c70 - 0x00002c73] io PCI: 00:1f.1 1c * [0x00002c80 - 0x00002c83] io Root Device compute_allocate_io: base: 00002c84 size: 00002884 align: 12 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:02.0 10 * [0x00000000 - 0x07ffffff] prefmem PCI: 00:1e.0 20 * [0x08000000 - 0x080fffff] mem PCI: 00:02.0 14 * [0x08100000 - 0x0817ffff] mem PCI: 00:1d.7 10 * [0x08180000 - 0x081803ff] mem PCI: 00:1f.1 24 * [0x08181000 - 0x081813ff] mem PCI: 00:1f.5 18 * [0x08182000 - 0x081821ff] mem PCI: 00:1f.5 1c * [0x08183000 - 0x081830ff] mem Root Device compute_allocate_mem: base: 08183100 size: 08183100 align: 27 gran: 0 done Done reading resources. Allocating VGA resource PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00002884 align: 12 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io PCI: 00:1d.0 20 * [0x000028c0 - 0x000028df] io PCI: 00:1d.1 20 * [0x000028e0 - 0x000028ff] io PCI: 00:1d.2 20 * [0x00002c00 - 0x00002c1f] io PCI: 00:1f.3 20 * [0x00002c20 - 0x00002c3f] io PCI: 00:1f.1 20 * [0x00002c40 - 0x00002c4f] io PCI: 00:1f.1 10 * [0x00002c50 - 0x00002c57] io PCI: 00:1f.1 18 * [0x00002c60 - 0x00002c67] io PCI: 00:1f.1 14 * [0x00002c70 - 0x00002c73] io PCI: 00:1f.1 1c * [0x00002c80 - 0x00002c83] io Root Device compute_allocate_io: base: 00002c84 size: 00001c84 align: 12 gran: 0 done Root Device compute_allocate_mem: base: f0000000 size: 08183100 align: 27 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:02.0 10 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:1e.0 20 * [0xf8000000 - 0xf80fffff] mem PCI: 00:02.0 14 * [0xf8100000 - 0xf817ffff] mem PCI: 00:1d.7 10 * [0xf8180000 - 0xf81803ff] mem PCI: 00:1f.1 24 * [0xf8181000 - 0xf81813ff] mem PCI: 00:1f.5 18 * [0xf8182000 - 0xf81821ff] mem PCI: 00:1f.5 1c * [0xf8183000 - 0xf81830ff] mem Root Device compute_allocate_mem: base: f8183100 size: 08183100 align: 27 gran: 0 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 57344 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem PCI: 00:02.0 14 <- [0x00f8100000 - 0x00f817ffff] size 0x00080000 gran 0x13 mem PCI: 00:02.0 30 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x00 romem PCI: 00:1d.0 20 <- [0x00000028c0 - 0x00000028df] size 0x00000020 gran 0x05 io PCI: 00:1d.1 20 <- [0x00000028e0 - 0x00000028ff] size 0x00000020 gran 0x05 io PCI: 00:1d.2 20 <- [0x0000002c00 - 0x0000002c1f] size 0x00000020 gran 0x05 io PCI: 00:1d.7 10 <- [0x00f8180000 - 0x00f81803ff] size 0x00000400 gran 0x0a mem PCI: 00:1e.0 compute_allocate_io: base: 00001000 size: 00001000 align: 12 gran: 12 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:08.0 14 * [0x00001000 - 0x0000103f] io PCI: 00:1e.0 compute_allocate_io: base: 00001040 size: 00001000 align: 12 gran: 12 done PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:1e.0 compute_allocate_mem: base: f8000000 size: 00100000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:08.0 10 * [0xf8000000 - 0xf8000fff] mem PCI: 00:1e.0 compute_allocate_mem: base: f8001000 size: 00100000 align: 20 gran: 20 done PCI: 00:1e.0 20 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:1e.0 assign_resources, bus 1 link: 0 PCI: 01:08.0 10 <- [0x00f8000000 - 0x00f8000fff] size 0x00001000 gran 0x0c mem PCI: 01:08.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:1e.0 assign_resources, bus 1 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.5 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.7 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.7 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.7 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.a 60 <- [0x0000000800 - 0x00000007ff] size 0x00000000 gran 0x00 io PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.1 10 <- [0x0000002c50 - 0x0000002c57] size 0x00000008 gran 0x03 io PCI: 00:1f.1 14 <- [0x0000002c70 - 0x0000002c73] size 0x00000004 gran 0x02 io PCI: 00:1f.1 18 <- [0x0000002c60 - 0x0000002c67] size 0x00000008 gran 0x03 io PCI: 00:1f.1 1c <- [0x0000002c80 - 0x0000002c83] size 0x00000004 gran 0x02 io PCI: 00:1f.1 20 <- [0x0000002c40 - 0x0000002c4f] size 0x00000010 gran 0x04 io PCI: 00:1f.1 24 <- [0x00f8181000 - 0x00f81813ff] size 0x00000400 gran 0x0a mem PCI: 00:1f.3 20 <- [0x0000002c20 - 0x0000002c3f] size 0x00000020 gran 0x05 io PCI: 00:1f.5 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:1f.5 14 <- [0x0000002880 - 0x00000028bf] size 0x00000040 gran 0x06 io PCI: 00:1f.5 18 <- [0x00f8182000 - 0x00f81821ff] size 0x00000200 gran 0x09 mem PCI: 00:1f.5 1c <- [0x00f8183000 - 0x00f81830ff] size 0x00000100 gran 0x08 mem PCI: 00:1f.6 10 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 00:1f.6 14 <- [0x0000002800 - 0x000000287f] size 0x00000080 gran 0x07 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 00/00 PCI: 00:02.0 cmd <- 03 PCI: 00:1d.0 cmd <- 01 PCI: 00:1d.1 cmd <- 01 PCI: 00:1d.2 cmd <- 01 PCI: 00:1d.7 subsystem <- 00/00 PCI: 00:1d.7 cmd <- 02 PCI: 00:1e.0 bridge ctrl <- 0003 PCI: 00:1e.0 cmd <- 07 PCI: 01:08.0 cmd <- 03 PCI: 00:1f.0 cmd <- 0f PCI: 00:1f.1 cmd <- 03 PCI: 00:1f.3 subsystem <- 00/00 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.5 cmd <- 03 PCI: 00:1f.6 cmd <- 01 done. Initializing devices... Root Device init PCI: 00:00.0 init Northbridge init PCI: 00:02.0 init rom address for PCI: 00:02.0 = fff00000 PCI Expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 PCI ROM Image, Vendor 8086, Device 3577, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from 0xfff00000 to 0xc0000, 0x10000 bytes entering emulator halt_sys: file /home/joe/coreboot-v2/src/devices/emulator/x86emu/ops.c, line 4387 PCI: 00:1d.0 init PCI: 00:1d.1 init PCI: 00:1d.2 init PCI: 00:1d.7 init EHCI: Setting up controller.. done. PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 2000000 Set power on if power fails RTC Init PNP: 002e.3 init PNP: 002e.4 init PNP: 002e.5 init PNP: 002e.7 init Keyboard init... PNP: 002e.a init PCI: 00:1f.1 init IDE0 IDE1 PCI: 00:1f.3 init APIC_CLUSTER: 0 init malloc Enter, size 1100, free_mem_ptr 00028000 malloc 0x00028000 Initializing CPU #0 CPU: vendor Intel device 6b4 CPU: family 06, model 0b, stepping 04 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 32MB, range: 16MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 48MB, range: 8MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode_info: sig = 0x000006b4 pf=0x00000010 rev = 0x00000000 Disabling local apic...done. CPU #0 Initialized Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000768 checksum a720 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfff10000 - 0xfffdffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 0002844c malloc 0x0002844c New segment addr 0x100000 size 0x3ce80 offset 0xc0 filesize 0x12e68 (cleaned up) New segment addr 0x100000 size 0x3ce80 offset 0xc0 filesize 0x12e68 lb: [0x0000000000004000, 0x000000000002c000) malloc Enter, size 32, free_mem_ptr 0002846c malloc 0x0002846c New segment addr 0x13ce80 size 0x48 offset 0x12f40 filesize 0x48 (cleaned up) New segment addr 0x13ce80 size 0x48 offset 0x12f40 filesize 0x48 lb: [0x0000000000004000, 0x000000000002c000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000003ce80 filesz: 0x0000000000012e68 [ 0x0000000000100000, 0000000000112e68, 0x000000000013ce80) <- 00000000000000c0 Clearing Segment: addr: 0x0000000000112e68 memsz: 0x000000000002a018 Loading Segment: addr: 0x000000000013ce80 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x000000000013ce80, 000000000013cec8, 0x000000000013cec8) <- 0000000000012f40 Loaded segments verified segments closed down stream Jumping to boot code at 0x10e61c entry = 0x0010e61c lb_start = 0x00004000 lb_size = 0x00028000 adjust = 0x037d4000 buffer = 0x037b0000 elf_boot_notes = 0x00021c20 adjusted_boot_notes = 0x037f5c20 FILO version 0.5 (joe(a)localhost.localdomain) Fri Mar 28 09:16:02 EDT 2008 menu: hdc1:/grub/grub.conf hdc: LBA 40GB: WDC WD400BB-23FJA0 Mounted ext2fs Press any key to continue. [H[J FILO 0.5 [m[4;2H+-------------------------------------------------------------------------+[5;2H|[5;76H|[6;2H|[6;76H|[7;2H|[7;76H|[8;2H|[8;76H|[9;2H|[9;76H|[10;2H|[10;76H|[11;2H|[11;76H|[12;2H|[12;76H|[13;2H|[13;76H|[14;2H|[14;76H|[15;2H|[15;76H|[16;2H|[16;76H|[17;2H+-------------------------------------------------------------------------+[m Use the ^ and v keys to select which entry is highlighted. Press enter to boot the selected OS, 'e' to edit the commands before booting, 'a' to modify the kernel arguments before booting, or 'c' for a command-line.[5;78H [m[7m[5;3H Fedora (2.6.23.15-80.fc7) [5;75H[m[m[6;3H Fedora Console (2.6.23.15-80.fc7) [6;75H[m[m[7;3H [7;75H[m[m[8;3H [8;75H[m[m[9;3H [9;75H[m[m[10;3H [10;75H[m[m[11;3H [11;75H[m[m[12;3H [12;75H[m[m[13;3H [13;75H[m[m[14;3H [14;75H[m[m[15;3H [15;75H[m[m[16;3H [16;75H[m[16;78H [5;75H[23;4HThe highlighted entry will be booted automatically in 10 seconds. [5;75H[23;4HThe highlighted entry will be booted automatically in 9 seconds. [5;75H[23;4H [5;75H[m[5;3H Fedora (2.6.23.15-80.fc7) [5;75H[m[m[7m[6;3H Fedora Console (2.6.23.15-80.fc7) [6;75H[m[H[J Booting 'Fedora Console (2.6.23.15-80.fc7)' root (hd2,0) kernel /vmlinuz-2.6.23.15-80.fc7 ro root=LABEL=/ console=tty0 console=ttyS0,115 200n8 s initrd /initrd-2.6.23.15-80.fc7.img [H[J Booting 'hdc1:/vmlinuz-2.6.23.15-80.fc7 ro root=LABEL=/ console=tty0 console=tt yS0,115200n8 s initrd=/initrd-2.6.23.15-80.fc7.img' Found Linux version 2.6.23.15-80.fc7 (mockbuild(a)xenbuilder4.fedora.phx.redhat.com) #1 SMP Sun Feb 10 17:29:10 EST 2008 bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... Linux version 2.6.23.15-80.fc7 (mockbuild(a)xenbuilder4.fedora.phx.redhat.com) (gcc version 4.1.2 20070925 (Red Hat 4.1.2-27)) #1 SMP Sun Feb 10 17:29:10 EST 2008 BIOS-provided physical RAM map: BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 0000000000100000 - 0000000003800000 (usable) 0MB HIGHMEM available. 56MB LOWMEM available. Using x86 segment limits to approximate NX protection Zone PFN ranges: DMA 0 -> 4096 Normal 4096 -> 14336 HighMem 14336 -> 14336 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0 -> 14336 DMI not present or invalid. Using APIC driver default ACPI: no DMI BIOS year, acpi=force is required to enable ACPI ACPI: Disabling ACPI support Allocating PCI resources starting at 10000000 (gap: 03800000:fc800000) swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000 Built 1 zonelists in Zone order. Total pages: 14224 Kernel command line: ro root=LABEL=/ console=tty0 console=ttyS0,115200n8 s Local APIC disabled by BIOS -- you can enable it with "lapic" Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 CPU 0 irqstacks, hard=c07a6000 soft=c0786000 PID hash table entries: 256 (order: 8, 1024 bytes) Detected 933.116 MHz processor. Console: colour VGA+ 80x25 console [tty0] enabled console [ttyS0] enabled Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 49120k/57344k available (2178k kernel code, 7816k reserved, 1114k data, 280k init, 0k highmem) virtual kernel memory layout: fixmap : 0xffc53000 - 0xfffff000 (3760 kB) pkmap : 0xff800000 - 0xffc00000 (4096 kB) vmalloc : 0xc4000000 - 0xff7fe000 ( 951 MB) lowmem : 0xc0000000 - 0xc3800000 ( 56 MB) .init : 0xc073d000 - 0xc0783000 ( 280 kB) .data : 0xc062098d - 0xc0737544 (1114 kB) .text : 0xc0400000 - 0xc062098d (2178 kB) Checking if this processor honours the WP bit even in supervisor mode... Ok. SLUB: Genslabs=22, HWalign=32, Order=0-1, MinObjects=4, CPUs=1, Nodes=1 Calibrating delay using timer specific routine.. 1867.13 BogoMIPS (lpj=933568) Security Framework v1.0.0 initialized SELinux: Initializing. selinux_register_security: Registering secondary module capability Capability LSM initialized as secondary Mount-cache hash table entries: 512 CPU: L1 I cache: 16K, L1 D cache: 16K CPU: L2 cache: 512K Intel machine check architecture supported. Intel machine check reporting enabled on CPU#0. Compat vDSO mapped to ffffe000. Checking 'hlt' instruction... OK. SMP alternatives: switching to UP code Freeing SMP alternatives: 14k freed CPU0: Intel(R) Pentium(R) III CPU - S 933MHz stepping 04 SMP motherboard not detected. Local APIC not detected. Using dummy APIC emulation. Brought up 1 CPUs Booting paravirtualized kernel on bare hardware Time: 1:00:09 Date: 88/08/80 NET: Registered protocol family 16 ACPI Exception (utmutex-0263): AE_BAD_PARAMETER, Thread C37D2000 could not acquire Mutex [1] [20070126] No dock devices found. PCI: Using configuration type 1 Setting up standard PCI resources ACPI: Interpreter disabled. Linux Plug and Play Support v0.97 (c) Adam Belay pnp: PnP ACPI: disabled usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb PCI: Probing PCI hardware * The chipset may have PM-Timer Bug. Due to workarounds for a bug, * this clock source is slow. If you are sure your timer does not have * this bug, please use "acpi_pm_good" to disable the workaround PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO PCI quirk: region 0500-053f claimed by ICH4 GPIO PCI: Transparent bridge - 0000:00:1e.0 PCI: Using IRQ router PIIX/ICH [8086/24c0] at 0000:00:1f.0 PCI: Found IRQ 3 for device 0000:00:02.0 PCI: Sharing IRQ 3 with 0000:00:1d.0 PCI: Found IRQ 7 for device 0000:00:1d.1 PCI: Found IRQ 6 for device 0000:00:1d.2 PCI: Sharing IRQ 6 with 0000:00:1f.1 PCI: Found IRQ 12 for device 0000:00:1d.7 PCI: Found IRQ 5 for device 0000:00:1f.3 PCI: Sharing IRQ 5 with 0000:00:1f.5 PCI: Found IRQ 9 for device 0000:01:08.0 NetLabel: Initializing NetLabel: domain hash size = 128 NetLabel: protocols = UNLABELED CIPSOv4 NetLabel: unlabeled traffic allowed by default Time: tsc clocksource has been installed. PCI: Bridge: 0000:00:1e.0 IO window: 1000-1fff MEM window: f8000000-f80fffff PREFETCH window: disabled. NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 2048 (order: 2, 24576 bytes) TCP bind hash table entries: 2048 (order: 2, 16384 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP reno registered checking if image is initramfs... it is Freeing initrd memory: 2847k freed apm: BIOS not found. audit: initializing netlink socket (disabled) audit(545965209.833:1): initialized Total HugeTLB memory allocated, 0 VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) ksign: Installing public key data Loading keyring - Added public key 4AF11E66D9C7B2BE - key was been created 656713375 seconds in future - User ID: Red Hat, Inc. (Kernel Module GPG key) io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) PCI: Firmware left 0000:01:08.0 e100 interrupts enabled, disabling pci_hotplug: PCI Hot Plug PCI Core version: 0.5 isapnp: Scanning for PnP cards... isapnp: No Plug & Play device found Real Time Clock Driver v1.12ac Non-volatile memory driver v1.2 Linux agpgart interface v0.102 agpgart: Detected an Intel 830M Chipset. agpgart: Detected 8060K stolen memory. agpgart: AGP aperture is 128M @ 0xf0000000 Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled �serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A serial8250: ttyS1 at I/O 0x2f8 (irq = 0) is a 16550A RAMDISK driver initialized: 16 RAM disks of 16384K size 4096 blocksize input: Macintosh mouse button emulation as /class/input/input0 PNP: No PS/2 controller found. Probing ports directly. serio: i8042 KBD port at 0x60,0x64 irq 1 mice: PS/2 mouse device common for all mice input: AT Translated Set 2 keyboard as /class/input/input1 usbcore: registered new interface driver hiddev usbcore: registered new interface driver usbhid drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 Using IPI No-Shortcut mode Magic number: 12:182:3 Freeing unused kernel memory: 280k freed Write protecting the kernel read-only data: 846k Red Hat nash version 6.0.9 starting Mounting proc filesystem Mounting sysfs filesystem Creating /dev Creating initial device nodes Setting up hotplug. Clocksource tsc unstable (delta = 68873901 ns) Time: pit clocksource has been installed. Creating block device nodes. Loading uhci-hcd.ko module USB Universal Host Controller Interface driver v3.0 PCI: Found IRQ 3 for device 0000:00:1d.0 PCI: Sharing IRQ 3 with 0000:00:02.0 uhci_hcd 0000:00:1d.0: UHCI Host Controller uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 1 uhci_hcd 0000:00:1d.0: irq 3, io base 0x00002440 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected PCI: Found IRQ 7 for device 0000:00:1d.1 uhci_hcd 0000:00:1d.1: UHCI Host Controller uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 2 uhci_hcd 0000:00:1d.1: irq 7, io base 0x00002460 usb usb2: configuration #1 chosen from 1 choice hub 2-0:1.0: USB hub found hub 2-0:1.0: 2 ports detected PCI: Found IRQ 6 for device 0000:00:1d.2 PCI: Sharing IRQ 6 with 0000:00:1f.1 uhci_hcd 0000:00:1d.2: UHCI Host Controller uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 3 uhci_hcd 0000:00:1d.2: irq 6, io base 0x00002480 usb usb3: configuration #1 chosen from 1 choice hub 3-0:1.0: USB hub found hub 3-0:1.0: 2 ports detected usb 1-2: new low speed USB device using uhci_hcd and address 2 Loading ohci-hcd.ko module Loading ehci-hcd.ko module PCI: Found IRQ 12 for device 0000:00:1d.7 ehci_hcd 0000:00:1d.7: EHCI Host Controller ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 4 ehci_hcd 0000:00:1d.7: debug port 1 ehci_hcd 0000:00:1d.7: irq 12, io mem 0xf8180000 ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004 usb usb4: configuration #1 chosen from 1 choice hub 4-0:1.0: USB hub found hub 4-0:1.0: 6 ports detected Loading mbcache.ko module Loading jbd.ko module Loading ext3.ko module Loading scsi_mod.ko module SCSI subsystem initialized Loading sd_mod.ko module Loading libata.ko module Loading ata_piix.ko module PCI: Found IRQ 6 for device 0000:00:1f.1 PCI: Sharing IRQ 6 with 0000:00:1d.2 scsi0 : ata_piix scsi1 : ata_piix ata1: PATA max UDMA/100 cmd 0x000101f0 ctl 0x000103f6 bmdma 0x000124c0 irq 14 ata2: PATA max UDMA/100 cmd 0x00010170 ctl 0x00010376 bmdma 0x000124c8 irq 15 usb 1-2: device not accepting address 2, error -71 ata2.00: ATA-6: WDC WD400BB-23FJA0, 13.03G13, max UDMA/100 ata2.00: 78156288 sectors, multi 0: LBA ata2.00: limited to UDMA/33 due to 40-wire cable ata2.00: configured for UDMA/33 scsi 1:0:0:0: Direct-Access ATA WDC WD400BB-23FJ 13.0 PQ: 0 ANSI: 5 sd 1:0:0:0: [sda] 78156288 512-byte hardware sectors (40016 MB) sd 1:0:0:0: [sda] Write Protect is off sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 1:0:0:0: [sda] 78156288 512-byte hardware sectors (40016 MB) sd 1:0:0:0: [sda] Write Protect is off sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sda: sda1 sda2 sda3 sd 1:0:0:0: [sda] Attached SCSI disk Waiting for driver initialization. usb 1-2: new low speed USB device using uhci_hcd and address 4 usb 1-2: configuration #1 chosen from 1 choice input: Chicony USB Keyboard as /class/input/input2 input: USB HID v1.00 Keyboard [Chicony USB Keyboard] on usb-0000:00:1d.0-2 input: Chicony USB Keyboard as /class/input/input3 input,hiddev96: USB HID v1.00 Device [Chicony USB Keyboard] on usb-0000:00:1d.0-2 Loading ata_generic.ko module Loading usb-storage.ko module Initializing USB Mass Storage driver... usbcore: registered new interface driver usb-storage USB Mass Storage support registered. Waiting for driver initialization. Trying to resume from LABEL=SWAP-sda3 No suspend signature on swap, not resuming. Creating root device. Mounting root filesystem. kjournald starting. Commit interval 5 seconds EXT3-fs: mounted filesystem with ordered data mode. Setting up other filesystems. Setting up new root fs no fstab.sys, mounting internal defaults Switching to new root and running init. unmounting old /dev unmounting old /proc unmounting old /sys SELinux: Disabled at runtime. audit(545965223.190:2): selinux=0 auid=4294967295 INIT: version 2.86 booting Welcome to Fedora Press 'I' to enter interactive startup. Setting clock (utc): Tue Apr 7 21:00:26 EDT 1987 [ OK ] Starting udev: [ OK ] Loading default keymap (us): [ OK ] Setting hostname localhost.localdomain: [ OK ] No devices found Setting up Logical Volume Management: No volume groups found [ OK ] Checking filesystems Checking all file systems. [/sbin/fsck.ext3 (1) -- /] fsck.ext3 -a /dev/sda2 /: Superblock last write time is in the future. FIXED. /: clean, 142733/9755328 files, 1091052/9747438 blocks [/sbin/fsck.ext3 (1) -- /boot] fsck.ext3 -a /dev/sda1 /boot1: recovering journal /boot1: clean, 37/26104 files, 20498/104388 blocks [ OK ] Remounting root filesystem in read-write mode: [ OK ] Mounting local filesystems: [ OK ] Enabling local filesystem quotas: [ OK ] Enabling /etc/fstab swaps: [ OK ] INIT: Entering runlevel: 3 Entering non-interactive startup Applying Intel CPU microcode update: [ OK ] Checking for hardware changes [ OK ] Bringing up loopback interface: [ OK ] Starting auditd: [ OK ] Starting system logger: [ OK ] Starting kernel logger: [ OK ] Starting irqbalance: [ OK ] Starting rpcbind: [ OK ] Starting NFS statd: [ OK ] Starting RPC idmapd: [ OK ] Starting system message bus: [ OK ] Starting Bluetooth services:[ OK ] [ OK ] Mounting other filesystems: [ OK ] Starting PC/SC smart card daemon (pcscd): [ OK ] Starting hidd: [ OK ] Starting autofs: Loading autofs4: [ OK ] Starting automount: [ OK ] [ OK ] Starting hpiod: [ OK ] Starting hpssd: [ OK ] Starting cups: [ OK ] Starting sshd: [ OK ] Starting ntpd: [ OK ] Starting sendmail: [ OK ] Starting sm-client: [ OK ] Starting console mouse services: [ OK ] Starting ConsoleKit: [ OK ] Starting crond: [ OK ] [ OK ] Starting xfs: [ OK ] Starting anacron: [ OK ] Starting atd: [ OK ] Starting dhcdbd:[ OK ] Starting yum-updatesd: [ OK ] Starting Avahi daemon... [ OK ] Starting HAL daemon: [ OK ] Starting smartd: [ OK ] Fedora release 7 (Moonshine) Kernel 2.6.23.15-80.fc7 on an i686 localhost.localdomain login: root [root@localhost ~]#

2 4

[PATCH] flashrom: Add support for SPI-Chips on ICH9
by Dominik Geyer 18 May '08

18 May '08

Adds support for SPI-Chips on ICH9. This is done by using the generic SPI interface. Signed-off-by: Dominik Geyer <dominik.geyer <at> kontron.com> --- Hi Carl-Daniel, this is the rework of the initial patch. It is based on r3321 and was tested with an "Atmel 25DF321" and a "ST M25P32". All points you noted were fixed. The ich_spi_command acts as a wrapper function for converting arguments from spi_command to run_opcodes. Something I noticed during fixing: 1) What exactly is the flashchip.page_size? For LPC flashes it seems to be the erase-granularity, for SPI flashes it seems to be the page-write-granularity. Regards, Dominik -- Dominik Geyer - SW R&D - Kontron Modular Computers Sudetenstraße 7 D - 87600 Kaufbeuren Tel.: +49 (0) 83 41 / 803 -395 dominik.geyer(a)kontron.com -- diff -Naur coreboot-v2.orig/util/flashrom/Makefile coreboot-v2/util/flashrom/Makefile --- coreboot-v2.orig/util/flashrom/Makefile 2008-05-16 09:13:01.000000000 +0000 +++ coreboot-v2/util/flashrom/Makefile 2008-05-16 09:16:58.000000000 +0000 @@ -24,7 +24,8 @@ sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ w49f002u.o 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \ - flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o + flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ + ichspi.o all: pciutils dep $(PROGRAM) diff -Naur coreboot-v2.orig/util/flashrom/chipset_enable.c coreboot-v2/util/flashrom/chipset_enable.c --- coreboot-v2.orig/util/flashrom/chipset_enable.c 2008-05-16 09:13:01.000000000 +0000 +++ coreboot-v2/util/flashrom/chipset_enable.c 2008-05-16 09:13:55.000000000 +0000 @@ -198,7 +198,7 @@ /* Calculate the Root Complex Register Block address */ tmp &= 0xffffc000; printf_debug("Root Complex Register Block address = 0x%x\n", tmp); - rcrb = mmap(0, 0x4000, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); + rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp); if (rcrb == MAP_FAILED) { perror("Can't mmap memory using " MEM_DEV); exit(1); diff -Naur coreboot-v2.orig/util/flashrom/flash.h coreboot-v2/util/flashrom/flash.h --- coreboot-v2.orig/util/flashrom/flash.h 2008-05-16 09:13:01.000000000 +0000 +++ coreboot-v2/util/flashrom/flash.h 2008-05-16 09:13:33.000000000 +0000 @@ -499,4 +499,9 @@ int probe_stm50flw0x0x(struct flashchip *flash); int erase_stm50flw0x0x(struct flashchip *flash); int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf); + +/* ichspi.c */ +int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int ich_spi_read(struct flashchip *flash, uint8_t * buf); +int ich_spi_write(struct flashchip *flash, uint8_t * buf); #endif /* !__FLASH_H__ */ diff -Naur coreboot-v2.orig/util/flashrom/flashchips.c coreboot-v2/util/flashrom/flashchips.c --- coreboot-v2.orig/util/flashrom/flashchips.c 2008-05-16 09:13:01.000000000 +0000 +++ coreboot-v2/util/flashrom/flashchips.c 2008-05-16 09:14:15.000000000 +0000 @@ -43,6 +43,7 @@ {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, @@ -101,7 +102,7 @@ {"ST", "M25P40-old", ST_ID, ST_M25P40_RES, 512, 256, TEST_UNTESTED, probe_spi_res, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, diff -Naur coreboot-v2.orig/util/flashrom/ichspi.c coreboot-v2/util/flashrom/ichspi.c --- coreboot-v2.orig/util/flashrom/ichspi.c 1970-01-01 00:00:00.000000000 +0000 +++ coreboot-v2/util/flashrom/ichspi.c 2008-05-16 09:14:41.000000000 +0000 @@ -0,0 +1,468 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann(a)kontron.com> + * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> + * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* + * This module is designed for supporting the devices + * ST M25P40 + * ST M25P80 + * ST M25P16 + * ST M25P32 already tested + * ST M25P64 + * AT 25DF321 already tested + * + */ + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include <sys/mman.h> +#include <pci/pci.h> +#include "flash.h" +#include "spi.h" + +#define MAXDATABYTES 0x40 + +/*ICH9 controller register definition*/ +#define REG_FADDR 0x08 /* 32 Bits */ +#define REG_FDATA0 0x10 /* 64 Bytes */ +#define REG_SSFS 0x90 /* 08 Bits */ +#define SSFS_SCIP 0x00000001 +#define SSFS_CDS 0x00000004 +#define SSFS_FCERR 0x00000008 +#define SSFS_AEL 0x00000010 +#define REG_SSFC 0x91 /* 24 Bits */ +#define SSFC_SCGO 0x00000200 +#define SSFC_ACS 0x00000400 +#define SSFC_SPOP 0x00000800 +#define SSFC_COP 0x00001000 +#define SSFC_DBC 0x00010000 +#define SSFC_DS 0x00400000 +#define SSFC_SME 0x00800000 +#define SSFC_SCF 0x01000000 +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 +#define REG_PREOP 0x94 /* 16 Bits */ +#define REG_OPTYPE 0x96 /* 16 Bits */ +#define REG_OPMENU 0x98 /* 64 BITS */ + +// ICH9R SPI commands +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 + + +typedef struct _OPCODE { + uint8_t opcode; //This commands spi opcode + uint8_t spi_type; //This commands spi type + uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 +} OPCODE; + +/* Opcode definition: + * Preop 1: Write Enable + * Preop 2: Write Status register enable + * + * OP 0: Write address + * OP 1: Read Address + * OP 2: ERASE block + * OP 3: Read Status register + * OP 4: Read ID + * OP 5: Write Status register + * OP 6: chip private (read JDEC id) + * OP 7: Chip erase + */ +typedef struct _OPCODES { + uint8_t preop[2]; + OPCODE opcode[8]; +} OPCODES; + + +static OPCODES *curopcodes=NULL; + + +/* HW access functions */ +static inline uint32_t REGREAD32(int X) +{ + volatile uint32_t regval; + regval = *(volatile uint32_t *)((uint8_t *)ich_spibar + X); + return regval; +} + +#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)ich_spibar+X)=Y) +#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)ich_spibar+X)=Y) +#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)ich_spibar+X)=Y) + + +/* Common SPI functions */ +static int program_opcodes(OPCODES * op); +static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); +static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset); +static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int Offset); +static int ich_spi_erase_block(struct flashchip *flash, int offset); + + +OPCODES O_ST_M25P = { + { + JEDEC_WREN, + 0 + }, + { + {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte + {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data + {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector + {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg + {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down + {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register + {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID + {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase + } +}; + + +int program_opcodes(OPCODES * op) +{ + uint8_t a; + uint16_t temp16; + uint32_t temp32; + + /* Program Prefix Opcodes */ + temp16 = 0; + /* 0:7 Prefix Opcode 1 */ + temp16 = (op->preop[0]); + /* 8:16 Prefix Opcode 2 */ + temp16 |= ((uint16_t) op->preop[1]) << 8; + REGWRITE16(REG_PREOP, temp16); + + /*Program Opcode Types 0 - 7 */ + temp16 = 0; + for (a = 0; a < 8; a++) { + temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2); + } + REGWRITE16(REG_OPTYPE, temp16); + + /*Program Allowable Opcodes 0 - 3 */ + temp32 = 0; + for (a = 0; a < 4; a++) { + temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8); + } + REGWRITE32(REG_OPMENU, temp32); + + /*Program Allowable Opcodes 4 - 7 */ + temp32 = 0; + for (a = 4; a < 8; a++) { + temp32 |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); + } + REGWRITE32(REG_OPMENU + 4, temp32); + + return 0; +} + +int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength, + uint8_t * data) +{ + int write_cmd = 0; + uint32_t temp32; + uint32_t a; + + /* Is it a write command? */ + if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) + || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { + write_cmd = 1; + } + + /* Programm Offset in Flash into FADDR */ + REGWRITE32(REG_FADDR, (offset & 0x00FFFFFF)); /*SPI addresses are 24 BIT only */ + + /* Program data into FDATA0 to N */ + if (write_cmd && (datalength != 0)) { + temp32 = 0; + for (a = 0; a < datalength; a++) { + if ((a % 4) == 0) { + temp32 = 0; + } + + temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); + + if ((a % 4) == 3) { + REGWRITE32(REG_FDATA0 + (a - (a % 4)), temp32); + } + } + if (((a - 1) % 4) != 3) { + REGWRITE32(REG_FDATA0 + ((a - 1) - ((a - 1) % 4)), + temp32); + } + + } + + /* Assemble SSFS + SSFC */ + temp32 = 0; + + /* clear error status registers */ + temp32 |= (SSFS_CDS + SSFS_FCERR); + /* USE 20 MhZ */ + temp32 |= SSFC_SCF_20MHZ; + + if (datalength != 0) { + uint32_t datatemp; + temp32 |= SSFC_DS; + datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + temp32 |= datatemp; + } + + /* Select opcode */ + temp32 |= ((uint32_t) (nr & 0x07)) << (8 + 4); + + /* Handle Atomic */ + if (op.atomic != 0) { + /* Select atomic command */ + temp32 |= SSFC_ACS; + /* Selct prefix opcode */ + if ((op.atomic - 1) == 1) { + /*Select prefix opcode 2 */ + temp32 |= SSFC_SPOP; + } + } + + /* Start */ + temp32 |= SSFC_SCGO; + + /* write it */ + REGWRITE32(REG_SSFS, temp32); + + /*wait for cycle complete */ + while ((REGREAD32(REG_SSFS) & SSFS_CDS) == 0) { + /*TODO; Do something that this can't lead into an endless loop. but some + * commands may cause this to be last more than 30 seconds */ + } + + if ((REGREAD32(REG_SSFS) & SSFS_FCERR) != 0) { + printf_debug("Transaction error!\n"); + return 1; + } + + if ((!write_cmd) && (datalength != 0)) { + for (a = 0; a < datalength; a++) { + if ((a % 4) == 0) { + temp32 = REGREAD32(REG_FDATA0 + (a)); + } + + data[a] = + (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >> + ((a % 4) * 8); + } + } + + return 0; +} + + +static int ich_spi_erase_block(struct flashchip *flash, int offset) +{ + printf_debug("Spi_Erase,Offset=%d,sectors=%d\n", offset, 1); + + if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) { + printf_debug("Error erasing sector at 0x%x", offset); + return -1; + } + + printf("DONE BLOCK 0x%x\n", offset); + + return 0; +} + +static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset) +{ + int page_size = flash->page_size; + uint32_t remaining = flash->page_size; + int a; + + printf_debug("Spi_Read,Offset=%d,number=%d,buf=%p\n", Offset, page_size, buf); + + for (a = 0; a < page_size; a += MAXDATABYTES) { + if (remaining < MAXDATABYTES) { + + if (run_opcode + (1, curopcodes->opcode[1], + Offset + (page_size - remaining), remaining, + &buf[page_size - remaining]) != 0) { + printf_debug("Error reading"); + return 1; + } + remaining = 0; + } else { + if (run_opcode + (1, curopcodes->opcode[1], + Offset + (page_size - remaining), MAXDATABYTES, + &buf[page_size - remaining]) != 0) { + printf_debug("Error reading"); + return 1; + } + remaining -= MAXDATABYTES; + } + } + + return 0; +} + +static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, + int Offset) +{ + int page_size = flash->page_size; + uint32_t remaining = page_size; + int a; + + printf_debug("write_page_ichspi,Offset=%d,number=%d,buf=%p\n", Offset, page_size, + bytes); + + for (a = 0; a < page_size; a += MAXDATABYTES) { + if (remaining < MAXDATABYTES) { + if (run_opcode + (0, curopcodes->opcode[0], + Offset + (page_size - remaining), remaining, + &bytes[page_size - remaining]) != 0) { + printf_debug("Error writing"); + return 1; + } + remaining = 0; + } else { + if (run_opcode + (0, curopcodes->opcode[0], + Offset + (page_size - remaining), MAXDATABYTES, + &bytes[page_size - remaining]) != 0) { + printf_debug("Error writing"); + return 1; + } + remaining -= MAXDATABYTES; + } + } + + return 0; +} + + +int ich_spi_read(struct flashchip *flash, uint8_t * buf) +{ + int i, rc = 0; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + + for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { + rc = ich_spi_read_page(flash, (void *)(buf + i * page_size), + i * page_size); + } + + return rc; +} + + +int ich_spi_write(struct flashchip *flash, uint8_t * buf) +{ + int i, j, rc = 0; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + int erase_size = 64 * 1024; + + spi_disable_blockprotect(); + + printf("Programming page: \n"); + + for (i = 0; i < total_size / erase_size; i++) { + rc = ich_spi_erase_block(flash, i * erase_size); + if (rc) { + printf("Error erasing block at 0x%x\n", i); + break; + } + + for (j = 0; j < erase_size / page_size; j++) { + ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)), + (i * erase_size) + (j * page_size)); + } + } + + printf("\n"); + + return rc; +} + +int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +{ + int a; + int opcode_index = -1; + const unsigned char cmd = *writearr; + OPCODE *opcode; + uint32_t addr = 0; + uint8_t *data; + int count; + + /* program opcodes if not already done */ + if (curopcodes == NULL) { + printf_debug("Programming OPCODES\n"); + curopcodes=&O_ST_M25P; + program_opcodes(curopcodes); + } + + /* find cmd in opcodes-table */ + for (a = 0; a < 8; a++) { + if ((curopcodes->opcode[a]).opcode == cmd) { + opcode_index = a; + break; + } + } + + /* unknown / not programmed command */ + if (opcode_index == -1) { + printf_debug("Invalid OPCODE 0x%02x\n", cmd); + return 1; + } + + opcode = &(curopcodes->opcode[opcode_index]); + + /* if opcode-type requires an address */ + if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || + opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { + addr = (writearr[1]<<16) | + (writearr[2]<<8) | + (writearr[3]<<0); + } + + /* translate read/write array/count */ + if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { + data = (uint8_t*)(writearr+1); + count = writecnt-1; + } + else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { + data = (uint8_t*)(writearr+4); + count = writecnt-4; + } + else { + data = (uint8_t*)readarr; + count = readcnt; + } + + if (run_opcode(opcode_index, *opcode, addr, count, data) != 0) { + printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); + return 1; + } + + return 0; +} diff -Naur coreboot-v2.orig/util/flashrom/spi.c coreboot-v2/util/flashrom/spi.c --- coreboot-v2.orig/util/flashrom/spi.c 2008-05-16 09:13:01.000000000 +0000 +++ coreboot-v2/util/flashrom/spi.c 2008-05-16 09:15:52.000000000 +0000 @@ -35,6 +35,8 @@ { if (it8716f_flashport) return it8716f_spi_command(writecnt, readcnt, writearr, readarr); + else if (ich9_detected) + return ich_spi_command(writecnt, readcnt, writearr, readarr); printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); return 1; } @@ -345,6 +347,8 @@ { if (it8716f_flashport) return it8716f_spi_chip_read(flash, buf); + else if (ich9_detected) + return ich_spi_read(flash, buf); printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); return 1; } @@ -353,6 +357,8 @@ { if (it8716f_flashport) return it8716f_spi_chip_write(flash, buf); + else if (ich9_detected) + return ich_spi_write(flash, buf); printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); return 1; } Kontron Modular Computers GmbH Geschaeftsfuehrer / Managing Directors: Ulrich Gehrmann, Thomas Sabisch Sitz der Gesellschaft / Registered Office: Kaufbeuren, Rechtsform / Legal: GmbH Amtsgericht / Local District Court Kempten, HRB Nr. / Trade Register No. 6195 The information contained in this document is CONFIDENTIAL and property of Kontron. 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5 9

[patch] Cleanups in Makefile for flashrom and superiotool
by Peter Lemenkov 18 May '08

18 May '08

Hello All! In order to simplify the mainteinance of packages for these two utilities in Fedora/RHEL we need to be able to redefine several makefile variables such as CFLAGS and PREFIX. There are two ways to do so: * first (ugly and a bit annoying) is to patch Makefile each time it changes by mainstream developers. * second - we may patch Makefile one time to allow conditional assignments for these variables and submit it to upstream (as I'm doing right now). Conditional assignment means that instead of defininv variables in the folowing way: PREFIX = /usr/local we must define it as following: PREFIX ?= /usr/local That means "if prefix was not defined somethere earlier we assign it to /usr/local". Another one issue is simplification of "install" section in Makefile. Installation preserves timestamps, creates necessary directories and ensures that man-page will not have the executable permission. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- Two simple patches attached. They also available at http://peter.fedorapeople.org/LinuxBIOS/ -- With best regards!

2 6

[tool] inteltool
by Stefan Reinauer 18 May '08

18 May '08

Hi there, After I wrote a number of small utilities a while back to dump the several memory mapped and io mapped registers of the Intel northbridges and southbridges, the number of these utilities became a bit overwhelming, while each utility was very limited. So I joined my utility collection and made one bigger tool out of it: inteltool inteltool dumps all registers of a typical intel system that I ran into so far. This includes GPIOs, RCBA, Egress Ports BAR, PMBASE, MCHBAR, DMIBAR, PCIEXBAR as well as an extended number of system MSRs. The tool also has a cleaner way of distinguishing between different Intel northbridges and southbridges now. Though only i945 and ICH7 are implemented and tested. It should be fairly easy to add other chips. I suggest dropping my first attempt in utils/inteltools and take this much better utility instead in utils/inteltool. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Attached as single files, as a patch does not make much sense Best wishes, Stefan # # Makefile for inteltool utility # # Copyright (C) 2008 by coresystems GmbH # written by Stefan Reinauer <stepan(a)coresystems.de> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # PROGRAM = inteltool CC = gcc INSTALL = /usr/bin/install PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz OBJS = inteltool.o all: pciutils dep $(PROGRAM) $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) clean: rm -f *.o *~ distclean: clean rm -f $(PROGRAM) .dependencies dep: @$(CC) -MM *.c > .dependencies pciutils: @echo; echo -n "Checking for pciutils and zlib... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ echo "found." || ( echo "not found."; echo; \ echo "Please install pciutils-devel and zlib-devel."; \ echo "See README for more information."; echo; \ rm -f .test.c .test; exit 1) @rm -f .test.c .test install: $(PROGRAM) $(INSTALL) $(PROGRAM) $(PREFIX)/sbin mkdir -p $(PREFIX)/share/man/man8 $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils -include .dependencies /* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * written by Stefan Reinauer <stepan(a)coresystems.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <errno.h> #include <fcntl.h> #include <unistd.h> #include <stdio.h> #include <string.h> #include <stdlib.h> #include <stdint.h> #include <getopt.h> #include <sys/mman.h> #include <sys/io.h> #include <pci/pci.h> #define INTELTOOL_VERSION "1.0" #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) typedef struct { uint32_t hi, lo; } msr_t; int fd_mem; int fd_msr; typedef struct { uint16_t addr; int size; char *name; } io_register_t; int print_gpios(struct pci_dev *sb) { int i; uint16_t gpiobase; io_register_t ich7_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, { 0x0c, 4, "GP_LVL" }, { 0x10, 4, "RESERVED" }, { 0x14, 4, "RESERVED" }, { 0x18, 4, "GPO_BLINK" }, { 0x1c, 4, "RESERVED" }, { 0x20, 4, "RESERVED" }, { 0x24, 4, "RESERVED" }, { 0x28, 4, "RESERVED" }, { 0x2c, 4, "GPI_INV" }, { 0x30, 4, "GPIO_USE_SEL2" }, { 0x34, 4, "GP_IO_SEL2" }, { 0x38, 4, "GP_LVL2" }, { 0x3C, 4, "RESERVED" } }; printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { case 0x27b8: // ICH7 gpiobase = pci_read_word(sb, 0x48) & 0xfffc; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This southbridge does not have GPIOBASE.\n"); return 1; default: printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n"); return 1; } printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase); for (i=0; i<ARRAY_SIZE(ich7_gpio_registers); i++) { switch (ich7_gpio_registers[i].size) { case 4: printf("gpiobase+0x%04x: 0x%08x (%s)\n", ich7_gpio_registers[i].addr, inl(gpiobase+ich7_gpio_registers[i].addr), ich7_gpio_registers[i].name); break; case 2: printf("gpiobase+0x%04x: 0x%04x (%s)\n", ich7_gpio_registers[i].addr, inw(gpiobase+ich7_gpio_registers[i].addr), ich7_gpio_registers[i].name); break; case 1: printf("gpiobase+0x%04x: 0x%02x (%s)\n", ich7_gpio_registers[i].addr, inb(gpiobase+ich7_gpio_registers[i].addr), ich7_gpio_registers[i].name); break; } } return 0; } int print_rcba(struct pci_dev *sb) { int i, size=0x4000; volatile uint8_t *rcba; uint32_t rcba_phys; printf("\n============= RCBA ==============\n\n"); switch (sb->device_id) { case 0x27b8: // ICH7 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This southbridge does not have RCBA.\n"); return 1; default: printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n"); return 1; } rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) rcba_phys); if (rcba == MAP_FAILED) { perror("Error mapping RCBA"); exit(1); } printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys); for (i=0; i<size; i+=4) { if(*(uint32_t *)(rcba+i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba+i)); } munmap((void *) rcba, size); return 0; } int print_pmbase(struct pci_dev *sb) { int i, size=0x80; uint16_t pmbase; printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { case 0x27b8: // ICH7 pmbase = pci_read_word(sb, 0x40) & 0xfffc; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This southbridge does not have PMBASE.\n"); return 1; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); return 1; } printf("PMBASE = 0x%04x (IO)\n\n", pmbase); for (i=0; i<size; i+=4) { printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase+i)); } return 0; } /* * (G)MCH MMIO Config Space */ int print_mchbar(struct pci_dev *nb) { int i, size=(16*1024); volatile uint8_t *mchbar; uint32_t mchbar_phys; printf("\n============= MCHBAR ============\n\n"); switch (nb->device_id) { case 0x27a0: // i945 mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have MCHBAR.\n"); return 1; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1; } mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) mchbar_phys ); if (mchbar == MAP_FAILED) { perror("Error mapping MCHBAR"); exit(1); } printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys); for (i=0; i<size; i+=4) { if(*(uint32_t *)(mchbar+i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); } munmap((void *) mchbar, size); return 0; } /* * Egress Port Root Complex MMIO configuration space */ int print_epbar(struct pci_dev *nb) { int i, size=4096; volatile uint8_t *epbar; uint32_t epbar_phys; printf("\n============= EPBAR =============\n\n"); switch (nb->device_id) { case 0x27a0: // i945 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have EPBAR.\n"); return 1; default: printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); return 1; } epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) epbar_phys ); if (epbar == MAP_FAILED) { perror("Error mapping EPBAR"); exit(1); } printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys); for (i=0; i<size; i+=4) { if(*(uint32_t *)(epbar+i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); } munmap((void *) epbar, size); return 0; } /* * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space */ int print_dmibar(struct pci_dev *nb) { int i, size=4096; volatile uint8_t *dmibar; uint32_t dmibar_phys; printf("\n============= DMIBAR ============\n\n"); switch (nb->device_id) { case 0x27a0: // i945 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have DMIBAR.\n"); return 1; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; } dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) dmibar_phys ); if (dmibar == MAP_FAILED) { perror("Error mapping DMIBAR"); exit(1); } printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys); for (i=0; i<size; i+=4) { if(*(uint32_t *)(dmibar+i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); } munmap((void *) dmibar, size); return 0; } /* * PCIe MMIO configuration space */ int print_pciexbar(struct pci_dev *nb) { uint32_t pciexbar_reg; uint32_t pciexbar_phys; volatile uint8_t *pciexbar; int max_busses, devbase, i; int bus, dev, fn; printf("========= PCIEXBAR ========\n\n"); switch (nb->device_id) { case 0x27a0: // i945 pciexbar_reg = pci_read_long(nb, 0x48); break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have PCIEXBAR.\n"); return 1; default: printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); return 1; } if( !(pciexbar_reg & (1 << 0))) { printf("PCIEXBAR register is disabled.\n"); return 0; } switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); max_busses = 256; break; case 1: // 128M pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); max_busses = 128; break; case 2: // 64M pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); max_busses = 64; break; default: // RSVD printf("Undefined Address base. Bailing out\n"); return 1; } printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) pciexbar_phys ); if (pciexbar == MAP_FAILED) { perror("Error mapping PCIEXBAR"); exit(1); } for (bus = 0; bus < max_busses; bus++) { for (dev = 0; dev < 32; dev++) { for (fn = 0; fn < 8; fn++) { devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024); if (*(uint16_t *)(pciexbar + devbase) == 0xffff) continue; /* This is a heuristics. Anyone got a better check? */ if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) && (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) { #if DEBUG printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn); #endif continue; } printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn); for (i=0; i<4096; i++) { if((i % 0x10) == 0) printf("\n%04x:", i); printf(" %02x", *(pciexbar+devbase+i)); } printf("\n"); } } } munmap((void *) pciexbar, (max_busses * 1024 * 1024)); return 0; } int msr_readerror = 0; msr_t rdmsr(int addr) { unsigned char buf[8]; msr_t msr = { 0xffffffff, 0xffffffff }; if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { perror("Could not lseek() to MSR"); close(fd_msr); exit(1); } if (read(fd_msr, buf, 8) == 8) { msr.lo = *(uint32_t *)buf; msr.hi = *(uint32_t *)(buf+4); return msr; } if (errno == 5) { printf(" (*)"); // Not all bits of the MSR could be read msr_readerror = 1; } else { // A severe error. perror("Could not read() MSR"); close(fd_msr); exit(1); } return msr; } int print_intel_core_msrs(void) { unsigned int i, core; msr_t msr; #define IA32_PLATFORM_ID 0x0017 #define EBL_CR_POWERON 0x002a #define FSB_CLK_STS 0x00cd #define IA32_TIME_STAMP_COUNTER 0x0010 #define IA32_APIC_BASE 0x001b typedef struct { int number; char *name; } msr_entry_t; msr_entry_t global_msrs[] = { { 0x0017, "IA32_PLATFORM_ID" }, { 0x002a, "EBL_CR_POWERON" }, { 0x00cd, "FSB_CLOCK_STS" }, { 0x00ce, "FSB_CLOCK_VCC" }, { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, { 0x00e3, "PMG_IO_BASE_ADDR" }, { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, { 0x00ee, "EXT_CONFIG" }, { 0x011e, "BBL_CR_CTL3" }, { 0x0194, "CLOCK_FLEX_MAX" }, { 0x0198, "IA32_PERF_STATUS" }, { 0x01a0, "IA32_MISC_ENABLES" }, { 0x01aa, "PIC_SENS_CFG" }, { 0x0400, "IA32_MC0_CTL" }, { 0x0401, "IA32_MC0_STATUS" }, { 0x0402, "IA32_MC0_ADDR" }, //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO { 0x040c, "IA32_MC4_CTL" }, { 0x040d, "IA32_MC4_STATUS" }, { 0x040e, "IA32_MC4_ADDR" }, //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO }; msr_entry_t per_core_msrs[] = { { 0x0010, "IA32_TIME_STAMP_COUNTER" }, { 0x001b, "IA32_APIC_BASE" }, { 0x003a, "IA32_FEATURE_CONTROL" }, { 0x003f, "IA32_TEMPERATURE_OFFSET" }, //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO { 0x008b, "IA32_BIOS_SIGN_ID" }, { 0x00e7, "IA32_MPERF" }, { 0x00e8, "IA32_APERF" }, { 0x00fe, "IA32_MTRRCAP" }, { 0x015f, "DTS_CAL_CTRL" }, { 0x0179, "IA32_MCG_CAP" }, { 0x017a, "IA32_MCG_STATUS" }, { 0x0199, "IA32_PERF_CONTROL" }, { 0x019a, "IA32_CLOCK_MODULATION" }, { 0x019b, "IA32_THERM_INTERRUPT" }, { 0x019c, "IA32_THERM_STATUS" }, { 0x019d, "GV_THERM" }, { 0x01d9, "IA32_DEBUGCTL" }, { 0x0200, "IA32_MTRR_PHYSBASE0" }, { 0x0201, "IA32_MTRR_PHYSMASK0" }, { 0x0202, "IA32_MTRR_PHYSBASE1" }, { 0x0203, "IA32_MTRR_PHYSMASK1" }, { 0x0204, "IA32_MTRR_PHYSBASE2" }, { 0x0205, "IA32_MTRR_PHYSMASK2" }, { 0x0206, "IA32_MTRR_PHYSBASE3" }, { 0x0207, "IA32_MTRR_PHYSMASK3" }, { 0x0208, "IA32_MTRR_PHYSBASE4" }, { 0x0209, "IA32_MTRR_PHYSMASK4" }, { 0x020a, "IA32_MTRR_PHYSBASE5" }, { 0x020b, "IA32_MTRR_PHYSMASK5" }, { 0x020c, "IA32_MTRR_PHYSBASE6" }, { 0x020d, "IA32_MTRR_PHYSMASK6" }, { 0x020e, "IA32_MTRR_PHYSBASE7" }, { 0x020f, "IA32_MTRR_PHYSMASK7" }, { 0x0250, "IA32_MTRR_FIX64K_00000" }, { 0x0258, "IA32_MTRR_FIX16K_80000" }, { 0x0259, "IA32_MTRR_FIX16K_A0000" }, { 0x0268, "IA32_MTRR_FIX4K_C0000" }, { 0x0269, "IA32_MTRR_FIX4K_C8000" }, { 0x026a, "IA32_MTRR_FIX4K_D0000" }, { 0x026b, "IA32_MTRR_FIX4K_D8000" }, { 0x026c, "IA32_MTRR_FIX4K_E0000" }, { 0x026d, "IA32_MTRR_FIX4K_E8000" }, { 0x026e, "IA32_MTRR_FIX4K_F0000" }, { 0x026f, "IA32_MTRR_FIX4K_F8000" }, { 0x02ff, "IA32_MTRR_DEF_TYPE" }, //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO }; fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (fd_msr<0) { perror("Error while opening /dev/cpu/0/msr"); printf("Did you run 'modprobe msr'?\n"); return -1; } printf("\n===================== SHARED MSRs (All Cores) =====================\n"); for (i = 0; i < ARRAY_SIZE(global_msrs); i++) { msr = rdmsr(global_msrs[i].number); printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", global_msrs[i].number, msr.hi, msr.lo, global_msrs[i].name); } close(fd_msr); for (core=0; core < 8; core++) { char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", core); fd_msr = open(msrfilename, O_RDWR); if (fd_msr<0) { /* If the file is not there, we're probably through. * No error, since we successfully opened /dev/cpu/0/msr before */ break; } printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); for (i = 0; i < ARRAY_SIZE(per_core_msrs); i++) { msr = rdmsr(per_core_msrs[i].number); printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", per_core_msrs[i].number, msr.hi, msr.lo, per_core_msrs[i].name); } close(fd_msr); } if (msr_readerror) printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); return 0; } void print_version(void) { printf("inteltool v%s -- ", INTELTOOL_VERSION); printf("Copyright (C) 2008 coresystems GmbH\n\n"); printf( "This program is free software: you can redistribute it and/or modify\n" "it under the terms of the GNU General Public License as published by\n" "the Free Software Foundation, version 2 of the License.\n\n" "This program is distributed in the hope that it will be useful,\n" "but WITHOUT ANY WARRANTY; without even the implied warranty of\n" "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" "GNU General Public License for more details.\n\n" "You should have received a copy of the GNU General Public License\n" "along with this program. If not, see <http://www.gnu.org/licenses/>.\n\n"); } void print_usage(const char *name) { printf("usage: %s [-vh?grpmedPM]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -g | --gpio: dump soutbridge GPIO registers\n" " -r | --rcba: dump soutbridge RCBA registers\n" " -p | --pmbase: dump soutbridge Power Management registers\n\n" " -m | --mchbar: dump northbridge Memory Controller registers\n" " -e | --epbar: dump northbridge EPBAR registers\n" " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" "\n"); exit(1); } int main(int argc, char *argv[]) { struct pci_access *pacc; struct pci_dev *sb, *nb; int opt; int option_index = 0; char *sbname, *nbname; int dump_gpios=0, dump_mchbar=0, dump_rcba=0; int dump_pmbase=0, dump_epbar=0, dump_dmibar=0; int dump_pciexbar=0, dump_coremsrs=0; static struct option long_options[] = { {"version", 0, 0, 'v'}, {"help", 0, 0, 'h'}, {"gpios", 0, 0, 'g'}, {"mchbar", 0, 0, 'm'}, {"rcba", 0, 0, 'r'}, {"pmbase", 0, 0, 'p'}, {"epbar", 0, 0, 'e'}, {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, {"all", 0, 0, 'a'}, {0, 0, 0, 0} }; while ((opt = getopt_long(argc, argv, "vh?gmrpedPca", long_options, &option_index)) != EOF) { switch (opt) { case 'v': print_version(); exit(0); break; case 'g': dump_gpios = 1; break; case 'm': dump_mchbar = 1; break; case 'r': dump_rcba = 1; break; case 'p': dump_pmbase = 1; break; case 'e': dump_epbar = 1; break; case 'd': dump_dmibar = 1; break; case 'P': dump_pciexbar = 1; break; case 'M': dump_coremsrs = 1; break; case 'a': dump_gpios = 1; dump_mchbar = 1; dump_rcba = 1; dump_pmbase = 1; dump_epbar = 1; dump_dmibar = 1; dump_pciexbar = 1; dump_coremsrs = 1; break; case 'h': case '?': default: print_usage(argv[0]); exit(0); break; } } if (iopl(3)) { printf("You need to be root.\n"); exit(1); } if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); } pacc = pci_alloc(); pci_init(pacc); pci_scan_bus(pacc); /* Find the required devices */ sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); if (!sb) { printf("No southbridge found.\n"); exit(1); } pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); if (sb->vendor_id != 0x8086) { printf("Not an Intel(R) southbridge.\n"); exit(1); } nb = pci_get_dev(pacc, 0, 0, 0x00, 0); if (!nb) { printf("No northbridge found.\n"); exit(1); } pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); if (nb->vendor_id != 0x8086) { printf("Not an Intel(R) northbridge.\n"); exit(1); } /* TODO check cpuid, too */ /* Determine names */ switch(nb->device_id) { case 0x27a0: nbname="i945"; break; default: nbname="unknown"; } switch(sb->device_id) { case 0x27b8: sbname="ICH7"; break; default: sbname="unknown"; } printf("Intel Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); printf("Intel Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ if (dump_gpios) { print_gpios(sb); printf("\n\n"); } if (dump_rcba) { print_rcba(sb); printf("\n\n"); } if (dump_pmbase) { print_pmbase(sb); printf("\n\n"); } if (dump_mchbar) { print_mchbar(nb); printf("\n\n"); } if (dump_epbar) { print_epbar(nb); printf("\n\n"); } if (dump_dmibar) { print_dmibar(nb); printf("\n\n"); } if (dump_pciexbar) { print_pciexbar(nb); printf("\n\n"); } if (dump_coremsrs) { print_intel_core_msrs(); printf("\n\n"); } /* Clean up */ pci_free_dev(nb); pci_free_dev(sb); pci_cleanup(pacc); return 0; } .TH INTELTOOL 8 "May 12, 2008" .SH NAME inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters .SH SYNOPSIS .B inteltool \fR[\fB\-vh?grpmedPM\fR] .SH DESCRIPTION .B inteltool is a handy little tool for dumping the configuration space of Intel(R) CPUs, northbridges and southbridges. This tool has been developed for the coreboot project (see .B http://www.coreboot.org/ for details on coreboot). .SH OPTIONS .TP .B "\-h, \-\-help" Show a help text and exit. .TP .B "\-v, \-\-version" Show version information and exit. .TP .B "\-a, \-\-all" Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs. .TP .B "\-g, \-\-gpio" Dump I/O Controller Hub (ICH) southbridge GPIO registers .TP .B "\-r, \-\-rcba" Dump I/O Controller Hub (ICH) southbridge RCBA registers .TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge pmbase registers .TP .B "\-m, \-\-mchbar" Dump Intel(R) northbridge MCHBAR registers .TP .B "\-e, \-\-epbar" Dump Intel(R) northbridge EPBAR registers .TP .B "\-d, \-\-dmibar" Dump Intel(R) northbridge DMIBAR registers .TP .B "\-P, \-\-pciexbar" Dump Intel(R) northbridge PCIEXBAR registers .TP .B "\-M, \-\-msrs" Dump Intel(R) CPU MSRs .SH BUGS Please report any bugs at .BR http://tracker.coreboot.org/trac/coreboot/newticket "," or on the coreboot mailing list .RB "(" http://coreboot.org/Mailinglist ")." .SH LICENCE .B inteltool is covered by the GNU General Public License (GPL), version 2 or later. .SH COPYRIGHT (C) 2008 coresystems GmbH .SH AUTHORS Stefan Reinauer <stepan(a)coresystems.de> .PP This manual page was written by Stefan Reinauer <stepan(a)coresystems.de>. It is licensed under the terms of the GNU GPL (version 2). Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners.

6 8

r3333 - trunk/util/inteltool
by svn＠coreboot.org 17 May '08

17 May '08

Author: uwe Date: 2008-05-17 23:33:35 +0200 (Sat, 17 May 2008) New Revision: 3333 Modified: trunk/util/inteltool/inteltool.c Log: Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial). Tested on hardware: Intel Northbridge: 8086:1a30 (i845) Intel Southbridge: 8086:2440 (ICH2) Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-05-17 01:08:58 UTC (rev 3332) +++ trunk/util/inteltool/inteltool.c 2008-05-17 21:33:35 UTC (rev 3333) @@ -36,18 +36,22 @@ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_ICH 0x2410 #define PCI_DEVICE_ID_INTEL_ICH0 0x2420 +#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd + +#define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, @@ -55,6 +59,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } };

1 0

Re: [coreboot] LinuxTag 2008
by Pierre Pronchery 17 May '08

17 May '08

Hi, I am new to the coreboot project, but I live and Berlin and may be able to help with the booth. On wednesday I'd need to leave latest 18:00, and maybe on saturday at 14:00 too. Besides that, I guess we could figure something out if you still need volunteers. I can also bring a 17" CRT screen (it's not so heavy though). Cheers, -- khorben

2 1

v2[PATCH] Initial support for the Thomson IP1000
by Joseph Smith 17 May '08

17 May '08

Hello, Here is a patch to add initial support for the Thomson IP1000. It is a cousin to the RCA RM4100. More info on it can be found here: http://www.settoplinux.org/index.php?title=Thomson_IP1000 Also attached is a coreboot bootlog with full debugging. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

3 13

Re: [coreboot] flashrom and PM49FL004/2
by Nikolay Petukhov 17 May '08

17 May '08

Hi. Patch[] already old. Try this patch. 2008/3/18, malatesh kamatad <malateshkamat(a)gmail.com>: > Hi ..... > > We are working on Coreboot we are trying to flash on the > PM49fl004/SST49lf004B > > but the flashrom has problems with the write and erase operation. > > We have MSI Neo and MSI K9N Ultra mother boards with socketed bios. > > > So we are following the procedure what you have given in the > mailing list (patch) , > > After compiling we are getting the error as bellow > > [malatesh@turtle22 flashrom]$ make > > Checking for pciutils and zlib... found. > gcc -o flashrom chipset_enable.o board_enable.o udelay.o jedec.o > sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o > 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o sst_fwhub.o > layout.o cbtable.o flashchips.o flashrom.o sharplhf00l04.o w29ee011.o spi.o > -lpci -lz -static > sst_fwhub.o: In function `probe_sst_fwhub': > sst_fwhub.c:(.text+0x21a): undefined reference to `probe_49fl00x' > flashchips.o:(.data+0x644): undefined reference to `probe_49fl00x' > flashchips.o:(.data+0x648): undefined reference to `erase_49fl00x' > flashchips.o:(.data+0x64c): undefined reference to `write_49fl00x' > flashchips.o:(.data+0x670): undefined reference to `probe_49fl00x' > flashchips.o:(.data+0x674): undefined reference to `erase_49fl00x' > flashchips.o:(.data+0x678): undefined reference to `write_49fl00x' > collect2: ld returned 1 exit status > make: *** [flashrom] Error 1 > > > I think we have down a mistake in this step , > > we are unable to understand the step i.e > > diff -Nru flashrom/flash.h flashrom-pm49fl00x/flash.h > > --- flashrom/flash.h 2008-02-07 03:07:58.000000000 +0500 > > +++ flashrom-pm49fl00x/flash.h 2008-03-11 13:38:25.000000000 > +0500 > > @@ -373,9 +373,9 @@ > please guide us............. > > with regards , > Malatesh. > > > > > > > > > > > > > -- Nikolay

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coreboot May 2008