coreboot May 2008

coreboot@coreboot.org

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387 discussions

fintek patch for f71805f
by bari 20 May '08

20 May '08

This is a patch for the fintek f71805f. I don't have hardware to test it on. Maybe Corey can check this. It may have been modified by Corey or Urbez as well. There were so many C7 + cn700 + VT8237r trees I've lost track. This will help with many Jetway boards. -Bari

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r3335 - trunk/coreboot-v2/src/superio/fintek/f71805f
by svn＠coreboot.org 20 May '08

20 May '08

Author: uwe Date: 2008-05-20 20:10:24 +0200 (Tue, 20 May 2008) New Revision: 3335 Added: trunk/coreboot-v2/src/superio/fintek/f71805f/Config.lb trunk/coreboot-v2/src/superio/fintek/f71805f/superio.c Log: Add post-RAM init code for the Fintek F71805F Super I/O. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Richard Stellingwerff <remenic(a)gmail.com> Added: trunk/coreboot-v2/src/superio/fintek/f71805f/Config.lb =================================================================== --- trunk/coreboot-v2/src/superio/fintek/f71805f/Config.lb (rev 0) +++ trunk/coreboot-v2/src/superio/fintek/f71805f/Config.lb 2008-05-20 18:10:24 UTC (rev 3335) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object superio.o + Added: trunk/coreboot-v2/src/superio/fintek/f71805f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/fintek/f71805f/superio.c (rev 0) +++ trunk/coreboot-v2/src/superio/fintek/f71805f/superio.c 2008-05-20 18:10:24 UTC (rev 3335) @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheet: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <stdlib.h> +#include <uart8250.h> +#include "chip.h" +#include "f71805f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x87, dev->path.u.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.u.pnp.port); +} + +static void f71805f_init(device_t dev) +{ + struct superio_fintek_f71805f_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) + return; + + switch(dev->path.u.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case F71805F_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case F71805F_SP2: + res1 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + } +} + +void f71805f_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +void f71805f_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +void f71805f_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = f71805f_pnp_set_resources, + .enable_resources = f71805f_pnp_enable_resources, + .enable = f71805f_pnp_enable, + .init = f71805f_init, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F71805F_GPIO, PNP_IRQ0, }, + { &ops, F71805F_PME, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71805f_ops = { + CHIP_NAME("Fintek F71805F Super I/O") + .enable_dev = enable_dev +}; +

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libpayload: payload exec code (repost)
by Jordan Crouse 20 May '08

20 May '08

Here is a repost of the payload execute code for libpayload. The API is described here: http://www.coreboot.org/Payload_API Jordan

2 1

Jetway J7F4K1G2E
by Richard Stellingwerff 20 May '08

20 May '08

The epia-cn patch boots Linux on the Jetway J7F4K1G2E, but both nics don't work. Here's the output from superiotool -dV (omitted everything that failed): Probing for Fintek Super I/O at 0x4e... Found Fintek F71805F/FG (vid=0x3419, id=0x0604) at 0x4e Register dump: idx 07 20 21 23 24 25 26 27 28 29 val 0a 04 06 19 34 00 00 20 08 00 def NA 04 06 19 34 00 00 3f 08 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f2 f4 val 00 00 00 00 04 0e ff 00 def 01 03 f0 06 02 0e 03 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 44 def 01 02 f8 03 00 04 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 val 01 03 78 07 04 00 def 01 03 78 07 03 42 LDN 0x04 (Hardware monitor) idx 30 60 61 70 val 01 02 95 00 def 00 02 95 00 LDN 0x06 (GPIO) idx 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f3 f4 val 00 00 00 60 00 00 00 00 00 00 9f 00 00 00 00 def 00 00 00 NA 00 00 00 00 00 00 00 00 NA 00 NA LDN 0x0a (PME) idx 30 f0 f1 val 01 00 06 def 00 00 00 And from lspci -tvnn: -[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:0314] +-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:1314] +-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:2314] +-00.3 VIA Technologies, Inc. PT890 Host Bridge [1106:3208] +-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:4314] +-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:7314] +-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP [1106:3344] +-09.0 Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet [10ec:8167] +-0b.0 Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet [10ec:8167] +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller [1106:3149] +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] [1106:3227] \-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] irq_tables.c (generated by getpir): /* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * * Contains the IRQ Routing Table dumped directly from your * memory, which BIOS sets up. * * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx */ #ifdef GETPIR #include "pirq_routing.h" #else #include <arch/pirq_routing.h> #endif const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*10, /* There can be total 10 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ 0x1106, /* Vendor */ 0x596, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x50, /* u8 checksum. This has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, {0x00,(0x0c<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, {0x00,(0x0d<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, {0x00,(0x11<<3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x01<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x10<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); }

2 1

buildrom
by qchwu 20 May '08

20 May '08

i want to use the buildrom in my platform (LX800+CS5536),in the first step,i work with the instruction in website: http://www.coreboot.org/Buildrom . the step to get the source code is completed.but,the "make is not successful,the following is the message svn co svn://coreboot.org/buildrom [root@localhost buildrom-devel]# make menuconfig # # using defaults found in .config # .config:24:warning: symbol value '' invalid for COREBOOT_V3_ROM_SIZE .config:95:warning: symbol value '' invalid for LAB_PAUSE *** End of buildrom configuration. *** Execute 'make' to build buildrom or try 'make help'. [root@localhost buildrom-devel]# make make: *** No rule to make target `|', needed by `/root/.Trash/buildrom-devel/work/lzma/stamps/.unpacked'. Stop. [root@localhost buildrom-devel]# [root@localhost buildrom-devel]# after the make,the "deploy" and "work" are not built. what is the matter within this apperance. thank you! chenghu qin

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Re: [coreboot] buildrom
by qchwu 20 May '08

20 May '08

I try to make again,the following is the appearence: ------------------------------------------- [root@localhost buildrom-devel]# make : Unsupported scheme. --04:40:28-- ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.7.tar.gz => `/bios/buildrom/buildrom-devel/sources/mkelfImage-2.7.tar.gz' Resolving ftp.lnxi.com... done. Connecting to ftp.lnxi.com[63.145.151.25]:21... connected. Logging in as anonymous ... Logged in! ==> SYST ... done. ==> PWD ... done. ==> TYPE I ... done. ==> CWD /pub/mkelfImage ... done. ==> PORT ... done. ==> RETR mkelfImage-2.7.tar.gz ... done. Length: 141,456 (unauthoritative) 100%[====================================>] 141,456 19.86K/s ETA 00:00 04:40:42 (19.86 KB/s) - `/bios/buildrom/buildrom-devel/sources/mkelfImage-2.7.tar.gz' saved [141456] FINISHED --04:40:42-- Downloaded: 141,456 bytes in 1 files make: *** No rule to make target `|', needed by `/bios/buildrom/buildrom-devel/work/mkelfimage/stamps/.unpacked'. Stop. [root@localhost buildrom-devel]# --------------------------------- In the make progress,the "buildrom/buildrom-devel/sources/mkelfImage-2.7.tar.gz" was downloaded, but ,it is useless. the GCC is used in my project.

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Gigabyte M57SLI-S4 MAC address
by Fredrik Tolf 20 May '08

20 May '08

Hi list! This mail is justa noteworthy observation I've made. I've got two separate M57SLI-S4 motherboards on which I've installed Coreboot, and I've noticed an interesting thing with the onboard Ethernet chip. It seems it contains one MAC address in hardware, which is changed by the factory-shipped BIOS during boot. The hardwired address begins with 00-E0-81, which seems to be registered to Tyan[1], and the address which it is replaced with begins with 00-1D-7D, which seems to be registered to Gigabyte. This is noteworthy for two reasons: 1. It confused me a lot at first. Since udev assigns a new interface name for every MAC address it discovers, it made my DHCP client fail since it couldn't find the interface it was configured for, so at first I thought that Coreboot couldn't initialize the NIC. I got past that pretty quickly, though. 2. More importantly, the hardwired address is actually the same for both motherboards! More precisely, it is 00-E0-81-54-32-66. Thus, running several of these board on the same physical link is a bad idea if one does not change the address manually. I don't know if anything should (or can) be done about this in Coreboot. I just thought I'd mention it. Fredrik Tolf [1] <http://standards.ieee.org/regauth/oui/oui.txt>

4 5

Building coreboot on 64-bit host
by llandre 20 May '08

20 May '08

I'm experiencing the problem shown below when trying to build coreboot release 3324 for Geode LX evaluation board db800 on 64-bit host. It seems ld is not invoked properly. Anybody can help me? Thanks in advance. [llandre@linuxserver2 targets]$ ./buildtarget amd/db800 build_dir=amd/db800/db800 Configuring TARGET db800 Will place Makefile, crt0.S, etc. in amd/db800/db800 Configuring ROMIMAGE fallback Curimage 0 Curpart is 0 Configuring DIR /config/Config.lb Configuring DIR /lib/Config.lb Configuring DIR /console/Config.lb Configuring DIR /stream/Config.lb Configuring DIR /devices/Config.lb Configuring DIR /pc80/Config.lb Configuring DIR /boot/Config.lb SETTING ARCH i386 Adding init file: init/crt0.S.lb Configuring DIR lib/Config.lb Configuring DIR boot/Config.lb Configuring DIR /pc80/Config.lb ===> WARNING: object/driver mc146818rtc previously defined ===> WARNING: object/driver isa-dma previously defined ===> WARNING: object/driver i8259 previously defined ===> WARNING: object/driver keyboard previously defined Configuring DIR /cpu/x86/tsc/Config.lb Configuring DIR /cpu/x86/fpu/Config.lb Configuring DIR /cpu/x86/mmx/Config.lb Configuring DIR /cpu/x86/lapic/Config.lb Configuring DIR /cpu/x86/cache/Config.lb End ROMIMAGE Build ROM size 487424 Verifying ROMIMAGE fallback Verifing global options Creating amd/db800/db800/fallback/static.c Creating amd/db800/db800/fallback/Makefile.settings Creating amd/db800/db800/fallback/crt0_includes.h Creating amd/db800/db800/fallback/Makefile Creating amd/db800/db800/fallback/ldoptions Creating amd/db800/db800/Makefile.settings Creating amd/db800/db800/Makefile Usage: /usr/bin/ld [options] file... Options: -a KEYWORD Shared library control for HP/UX compatibility -A ARCH, --architecture ARCH Set architecture -b TARGET, --format TARGET Specify target for following input files -c FILE, --mri-script FILE Read MRI format linker script -d, -dc, -dp Force common symbols to be defined -e ADDRESS, --entry ADDRESS Set start address -E, --export-dynamic Export all dynamic symbols -EB Link big-endian objects -EL Link little-endian objects -f SHLIB, --auxiliary SHLIB Auxiliary filter for shared object symbol table -F SHLIB, --filter SHLIB Filter for shared object symbol table -g Ignored -G SIZE, --gpsize SIZE Small data size (if no size, same as --shared) -h FILENAME, -soname FILENAME Set internal name of shared library -I PROGRAM, --dynamic-linker PROGRAM Set PROGRAM as the dynamic linker to use -l LIBNAME, --library LIBNAME Search for library LIBNAME -L DIRECTORY, --library-path DIRECTORY Add DIRECTORY to library search path -m EMULATION Set emulation -M, --print-map Print map file on standard output -n, --nmagic Do not page align data -N, --omagic Do not page align data, do not make text readonly --no-omagic Page align data, make text readonly -o FILE, --output FILE Set output file name -O Optimize output file -Qy Ignored for SVR4 compatibility -q, --emit-relocs Generate relocations in final output -r, -i, --relocatable Generate relocatable output -R FILE, --just-symbols FILE Just link symbols (if directory, same as --rpath) -s, --strip-all Strip all symbols -S, --strip-debug Strip debugging symbols --strip-discarded Strip symbols in discarded sections --no-strip-discarded Do not strip symbols in discarded sections -t, --trace Trace file opens -T FILE, --script FILE Read linker script -u SYMBOL, --undefined SYMBOL Start with undefined reference to SYMBOL --unique [=SECTION] Don't merge input [SECTION | orphan] sections -Ur Build global constructor/destructor tables -v, --version Print version information -V Print version and emulation information -x, --discard-all Discard all local symbols -X, --discard-locals Discard temporary local symbols (default) --discard-none Don't discard any local symbols -y SYMBOL, --trace-symbol SYMBOL Trace mentions of SYMBOL -Y PATH Default search path for Solaris compatibility -(, --start-group Start a group -), --end-group End a group --accept-unknown-input-arch Accept input files whose architecture cannot be determined --no-accept-unknown-input-arch Reject input files whose architecture is unknown -assert KEYWORD Ignored for SunOS compatibility -Bdynamic, -dy, -call_shared Link against shared libraries -Bstatic, -dn, -non_shared, -static Do not link against shared libraries -Bsymbolic Bind global references locally --check-sections Check section addresses for overlaps (default) --no-check-sections Do not check section addresses for overlaps --cref Output cross reference table --defsym SYMBOL=EXPRESSION Define a symbol --demangle [=STYLE] Demangle symbol names [using STYLE] --demangler DSO:FUNCTION Set DSO and demangler function --embedded-relocs Generate embedded relocs -fini SYMBOL Call SYMBOL at unload-time --force-exe-suffix Force generation of file with .exe suffix --gc-sections Remove unused sections (on some targets) --no-gc-sections Don't remove unused sections (default) --hash-size=<NUMBER> Set default hash table size close to <NUMBER> --help Print option help -init SYMBOL Call SYMBOL at load-time -Map FILE Write a map file --no-define-common Do not define Common storage --no-demangle Do not demangle symbol names --no-keep-memory Use less memory and more disk I/O --no-undefined Do not allow unresolved references in object files --allow-shlib-undefined Allow unresolved references in shared libaries --no-allow-shlib-undefined Do not allow unresolved references in shared libs --allow-multiple-definition Allow multiple definitions --no-undefined-version Disallow undefined version --no-warn-mismatch Don't warn about mismatched input files --no-whole-archive Turn off --whole-archive --noinhibit-exec Create an output file even if errors occur -nostdlib Only use library directories specified on the command line --oformat TARGET Specify target of output file -qmagic Ignored for Linux compatibility --reduce-memory-overheads Reduce memory overheads, possibly taking much longer --relax Relax branches on certain targets --retain-symbols-file FILE Keep only symbols listed in FILE -rpath PATH Set runtime shared library search path -rpath-link PATH Set link time shared library search path -shared, -Bshareable Create a shared library -pie, --pic-executable Create a position independent executable --sort-common Sort common symbols by size --spare-dynamic-tags COUNT How many tags to reserve in .dynamic section --split-by-file [=SIZE] Split output sections every SIZE octets --split-by-reloc [=COUNT] Split output sections every COUNT relocs --stats Print memory usage statistics --target-help Display target specific options --task-link SYMBOL Do task level linking --traditional-format Use same format as native linker --section-start SECTION=ADDRESS Set address of named section -Tbss ADDRESS Set address of .bss section -Tdata ADDRESS Set address of .data section -Ttext ADDRESS Set address of .text section --unresolved-symbols=<method> How to handle unresolved symbols. <method> is: ignore-all, report-all, ignore-in-object-files, ignore-in-shared-libs --verbose Output lots of information during link --version-script FILE Read version information script --version-exports-section SYMBOL Take export symbols list from .exports, using SYMBOL as the version. --warn-common Warn about duplicate common symbols --warn-constructors Warn if global constructors/destructors are seen --warn-multiple-gp Warn if the multiple GP values are used --warn-once Warn only once per undefined symbol --warn-section-align Warn if start of section changes due to alignment --warn-unresolved-symbols Report unresolved symbols as warnings --error-unresolved-symbols Report unresolved symbols as errors --fatal-warnings Treat warnings as errors --whole-archive Include all objects from following archives --add-needed Set DT_NEEDED tags for DT_NEEDED entries in following dynamic libs --no-add-needed Do not set DT_NEEDED tags for DT_NEEDED entries in following dynamic libs --as-needed Only set DT_NEEDED for following dynamic libs if used --no-as-needed Always set DT_NEEDED for following dynamic libs --wrap SYMBOL Use wrapper functions for SYMBOL /usr/bin/ld: supported targets: elf64-x86-64 elf32-i386 a.out-i386-linux efi-app-ia32 elf64-little elf64-big elf32-little elf32-big srec symbolsrec tekhex binary ihex /usr/bin/ld: supported emulations: elf_x86_64 elf_i386 i386linux /usr/bin/ld: emulation specific options: elf_x86_64: -Bgroup Selects group name lookup rules for DSO --disable-new-dtags Disable new dynamic tags --enable-new-dtags Enable new dynamic tags --eh-frame-hdr Create .eh_frame_hdr section -z combreloc Merge dynamic relocs into one section and sort -z defs Report unresolved symbols in object files. -z execstack Mark executable as requiring executable stack -z initfirst Mark DSO to be initialized first at runtime -z interpose Mark object to interpose all DSOs but executable -z loadfltr Mark object requiring immediate process -z muldefs Allow multiple definitions -z nocombreloc Don't merge dynamic relocs into one section -z nocopyreloc Don't create copy relocs -z nodefaultlib Mark object not to use default search paths -z nodelete Mark DSO non-deletable at runtime -z nodlopen Mark DSO not available to dlopen -z nodump Mark DSO not available to dldump -z noexecstack Mark executable as not requiring executable stack -z norelro Don't create RELRO program header -z now Mark object non-lazy runtime binding -z origin Mark object requiring immediate $ORIGIN processing at runtime -z relro Create RELRO program header -z KEYWORD Ignored for Solaris compatibility elf_i386: -Bgroup Selects group name lookup rules for DSO --disable-new-dtags Disable new dynamic tags --enable-new-dtags Enable new dynamic tags --eh-frame-hdr Create .eh_frame_hdr section -z combreloc Merge dynamic relocs into one section and sort -z defs Report unresolved symbols in object files. -z execstack Mark executable as requiring executable stack -z initfirst Mark DSO to be initialized first at runtime -z interpose Mark object to interpose all DSOs but executable -z loadfltr Mark object requiring immediate process -z muldefs Allow multiple definitions -z nocombreloc Don't merge dynamic relocs into one section -z nocopyreloc Don't create copy relocs -z nodefaultlib Mark object not to use default search paths -z nodelete Mark DSO non-deletable at runtime -z nodlopen Mark DSO not available to dlopen -z nodump Mark DSO not available to dldump -z noexecstack Mark executable as not requiring executable stack -z norelro Don't create RELRO program header -z now Mark object non-lazy runtime binding -z origin Mark object requiring immediate $ORIGIN processing at runtime -z relro Create RELRO program header -z KEYWORD Ignored for Solaris compatibility Supported demangler style: {none,auto,gnu,lucid,arm,hp,edg,gnu-v3,java,gnat,compaq} Report bugs to <URL:http://www.sourceware.org/bugzilla/> and hjl(a)lucon.org -- llandre DAVE Electronics System House - R&D Department web: http://www.dave.eu email: r&d2(a)dave-tech.it

5 9

Re: [coreboot] Contact Intel
by Richard M Stallman 20 May '08

20 May '08

When I wrote before about writing to Intel, I had considered only part of the issue. So I feel obligated to fill in the part of the picture that was missing. The messages you send to Intel's customer service in favor of free BIOS support are not read or answered by someone who has the authority to change Intel's policy. That's the part I considered before. The part I overlooked is that these messages are part of a campaign. Sending many letters to Intel has the effect of showing Intel that the public is concerned about the issue. So even if the people who read these messages only send back a canned response, they tell people higher up that the public is concerned about the issue. More letters mean more pressure. So it is useful to send the messages.

3 2

alix.2c3 status
by Carl-Daniel Hailfinger 19 May '08

19 May '08

Hi, is the v3 port of Alix.2C3 as stable as the v3 port of Alix.1C? Can I boot from USB/CompactFlash? I prefer to have a broader basis for my Alix.1C LinuxTag workshop, so if anybody with Alix.2C3 shows up, being able to help him as well would be cool. This is especially important because Alix.1C are out of stock at PCEngines. Regards, Carl-Daniel

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coreboot May 2008