coreboot April 2008

coreboot@coreboot.org

75 participants
404 discussions

flashrom + Scenic Mobile 510 Agp
by Markus 05 Apr '08

05 Apr '08

hi, I tried flashrom on the Notebook Scenic Mobile 510 Agp. Unforunal after calibarte loop the nb goes off. I think the read-access goes into apm. The notebook seems nice, because the flash is sockled. superio workes. SMSC sch5317 (id=0x85, rev=0x00,) at 0x370 Regard Markus

1 0

r657 - coreboot-v3/device
by svn＠coreboot.org 05 Apr '08

05 Apr '08

Author: stepan Date: 2008-04-05 22:18:47 +0200 (Sat, 05 Apr 2008) New Revision: 657 Modified: coreboot-v3/device/pci_rom.c Log: retrieve option roms from lar. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/pci_rom.c =================================================================== --- coreboot-v3/device/pci_rom.c 2008-04-05 00:09:29 UTC (rev 656) +++ coreboot-v3/device/pci_rom.c 2008-04-05 20:18:47 UTC (rev 657) @@ -27,6 +27,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> +#include <lar.h> struct rom_header *pci_rom_probe(struct device *dev) { @@ -35,12 +36,30 @@ struct pci_data *rom_data; unsigned int i; unsigned char sum = 0, *rom_bytes; + struct mem_file archive, result; if (dev->on_mainboard) { + int ret; + char pcifile[] = "pci0000,0000.rom"; /* In case some device PCI_ROM_ADDRESS can not be set * or readonly. */ - rom_address = dev->rom_address; + init_archive(&archive); + sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor, + dev->id.u.pci.device); + + ret = find_file(&archive, pcifile, &result); + if (ret) { + printk(BIOS_INFO, "No option rom for onboard device.\n"); + return NULL; + } + + /* FIXME hardcode to 0xc0000 for now because we can only init + * VGA anyways. + */ + process_file(&result, (void *)0xc0000); + rom_address = 0xc0000; + } else { rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); } @@ -140,10 +159,11 @@ if (dev != vga_pri) return NULL; // Only one VGA supported. #endif - printk(BIOS_DEBUG, - "Copying VGA ROM image from %p to 0x%x, 0x%x bytes\n", - rom_header, PCI_VGA_RAM_IMAGE_START, rom_size); - memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); + if (rom_header != (void *)PCI_VGA_RAM_IMAGE_START) { + printk(BIOS_DEBUG, "Copying VGA ROM image from %p to 0x%x, 0x%x bytes\n", + rom_header, PCI_VGA_RAM_IMAGE_START, rom_size); + memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); + } vga_inited = 1; return (struct rom_header *)(PCI_VGA_RAM_IMAGE_START); #endif

1 0

[PATCH] v3: read option roms from lar instead of hard coded address
by Stefan Reinauer 05 Apr '08

05 Apr '08

Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Index: device/pci_rom.c =================================================================== --- device/pci_rom.c (revision 643) +++ device/pci_rom.c (working copy) @@ -27,6 +27,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> +#include <lar.h> struct rom_header *pci_rom_probe(struct device *dev) { @@ -35,12 +36,30 @@ struct pci_data *rom_data; unsigned int i; unsigned char sum = 0, *rom_bytes; + struct mem_file archive, result; if (dev->on_mainboard) { + int ret; + char pcifile[] = "pci0000,0000.rom"; /* In case some device PCI_ROM_ADDRESS can not be set * or readonly. */ - rom_address = dev->rom_address; + init_archive(&archive); + sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor, + dev->id.u.pci.device); + + //rom_address = (unsigned long)load_file(&archive, pcifile); + ret = find_file(&archive, pcifile, &result); + if (ret) { + printk(BIOS_INFO, "No option rom for onboard device.\n"); + return NULL; + } + + // FIXME hardcode to 0xc0000 for now because we can only init + // vga anyways. + process_file(&result, (void *)0xc0000); + rom_address = 0xc0000; + } else { rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); }

2 1

[PATCH] [buildrom] fix alix.1c build for v3
by Ward Vandewege 05 Apr '08

05 Apr '08

-- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

2 2

r141 - in buildrom-devel: . config/platforms packages/coreboot-v3 packages/filo/conf packages/roms
by svn＠coreboot.org 05 Apr '08

05 Apr '08

Author: ward Date: 2008-04-05 06:28:24 +0200 (Sat, 05 Apr 2008) New Revision: 141 Added: buildrom-devel/packages/filo/conf/alix1c-Config Modified: buildrom-devel/Makefile buildrom-devel/config/platforms/alix1c.conf buildrom-devel/packages/coreboot-v3/coreboot-v3.mk buildrom-devel/packages/roms/roms.mk Log: This fixes v3 build for alix.1c. Tested on real hardware. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/Makefile =================================================================== --- buildrom-devel/Makefile 2008-03-29 18:22:02 UTC (rev 140) +++ buildrom-devel/Makefile 2008-04-05 04:28:24 UTC (rev 141) @@ -76,13 +76,25 @@ else LAR_PAYLOAD_FLAGS=-a endif + +ifeq ($(or $(CONFIG_VSA_LEGACY), $(CONFIG_VSA_OPENVSA)),) +else +OPTIONROM_TARGETS+=geodevsa +endif rom: $(HOSTTOOLS-y) payload $(COREBOOT-y) @ cp $(CBV3_OUTPUT) $(TARGET_ROM_FILE) - @ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(PAYLOAD_TARGET):normal/payload + @ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(CBV3_PAYLOAD_TARGET):normal/payload +ifeq ($(CONFIG_VSA_LEGACY),y) + @ $(STAGING_DIR)/bin/lar -a $(TARGET_ROM_FILE) $(SOURCE_DIR)/amd_vsa_lx_1.01.bin:blob/vsa +endif +ifeq ($(CONFIG_VSA_OPENVSA),y) + @ echo "Adding OpenVSA: TODO FIXME - let's actually implement this?" +endif @ for file in `ls $(ROM_DIR)`; do \ $(STAGING_DIR)/bin/lar -a $(TARGET_ROM_FILE) $(ROM_DIR)/$$file:$$file; \ done + @ $(STAGING_DIR)/bin/lar -z $(TARGET_ROM_FILE) endif payload: $(PAYLOAD_TARGET) Modified: buildrom-devel/config/platforms/alix1c.conf =================================================================== --- buildrom-devel/config/platforms/alix1c.conf 2008-03-29 18:22:02 UTC (rev 140) +++ buildrom-devel/config/platforms/alix1c.conf 2008-04-05 04:28:24 UTC (rev 141) @@ -32,6 +32,8 @@ CBV2_TDIR=alix1c CBV2_TAG=3079 +CBV3_TAG=656 + # FILO configuration FILO_CONFIG=alix1c-Config Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk =================================================================== --- buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-03-29 18:22:02 UTC (rev 140) +++ buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-04-05 04:28:24 UTC (rev 141) @@ -32,6 +32,12 @@ CBV3_PATCHES ?= +CBV3_PAYLOAD_TARGET=$(CBV3_DIR)/payload.elf + +$(CBV3_PAYLOAD_TARGET): $(PAYLOAD_TARGET) + @ echo $(PAYLOAD_TARGET) + @ cp $< $@ + $(SOURCE_DIR)/$(CBV3_TARBALL): @ mkdir -p $(SOURCE_DIR)/coreboot-v3 @ $(BIN_DIR)/fetchsvn.sh $(CBV3_URL) \ @@ -62,7 +68,7 @@ endif @ touch $@ -$(CBV3_OUTPUT): $(CBV3_STAMP_DIR)/.configured +$(CBV3_OUTPUT): $(CBV3_STAMP_DIR)/.configured $(CBV3_PAYLOAD_TARGET) @ echo "Building coreboot v3..." @ $(MAKE) -C $(CBV3_SRC_DIR) $(CBV3_ROM_SIZE) > $(CBV3_BUILD_LOG) 2>&1 Added: buildrom-devel/packages/filo/conf/alix1c-Config =================================================================== --- buildrom-devel/packages/filo/conf/alix1c-Config (rev 0) +++ buildrom-devel/packages/filo/conf/alix1c-Config 2008-04-05 04:28:24 UTC (rev 141) @@ -0,0 +1,50 @@ +# Use grub instead of autoboot? +USE_GRUB = 1 +# Grub menu.lst path +MENULST_FILE = "hda1:/boot/grub/menu.lst" +# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus +IDE_DISK = 1 +# Add a short delay when polling status registers +# (required on some broken SATA controllers) +IDE_DISK_POLL_DELAY = 1 +# Driver for USB Storage +USB_DISK = 1 +# VGA text console +VGA_CONSOLE = 1 +PC_KEYBOARD = 1 +# Enable the serial console +SERIAL_CONSOLE = 1 +# Serial console; real external serial port +SERIAL_IOBASE = 0x3f8 +SERIAL_SPEED = 115200 +# Filesystems +FSYS_EXT2FS = 1 +FSYS_ISO9660 = 1 +# Support for boot disk image in bootable CD-ROM (El Torito) +ELTORITO = 1 +# PCI support +SUPPORT_PCI = 1 +# Enable this to scan PCI busses above bus 0 +# AMD64 based boards do need this. +PCI_BRUTE_SCAN = 1 +# Loader for standard Linux kernel image, a.k.a. /vmlinuz +LINUX_LOADER = 1 + +# Debugging +#DEBUG_ALL = 1 +#DEBUG_ELFBOOT = 1 +#DEBUG_ELFNOTE = 1 +#DEBUG_LINUXBIOS = 1 +#DEBUG_MALLOC = 1 +#DEBUG_MULTIBOOT = 1 +#DEBUG_SEGMENT = 1 +#DEBUG_SYS_INFO = 1 +#DEBUG_TIMER = 1 +#DEBUG_BLOCKDEV = 1 +#DEBUG_PCI = 1 +#DEBUG_VIA_SOUND = 1 +#DEBUG_LINUXLOAD = 1 +#DEBUG_IDE = 1 +#DEBUG_USB = 1 +#DEBUG_ELTORITO = 1 + Modified: buildrom-devel/packages/roms/roms.mk =================================================================== --- buildrom-devel/packages/roms/roms.mk 2008-03-29 18:22:02 UTC (rev 140) +++ buildrom-devel/packages/roms/roms.mk 2008-04-05 04:28:24 UTC (rev 141) @@ -2,7 +2,7 @@ # here -OPTIONROM_TARGETS= +OPTIONROM_TARGETS?= OPTIONROM-y = OPTIONROM-$(CONFIG_PLATFORM_NORWICH) += rom-geode.inc

1 0

libpayload: remove uneeded stack structures
by Jordan Crouse 05 Apr '08

05 Apr '08

Following the cleanup of libpayload init, we had some uneeded structures laying about. This removes them. Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

2 1

r3217 - in trunk/payloads/libpayload: . i386
by svn＠coreboot.org 05 Apr '08

05 Apr '08

Author: uwe Date: 2008-04-05 03:07:27 +0200 (Sat, 05 Apr 2008) New Revision: 3217 Modified: trunk/payloads/libpayload/i386/head.S trunk/payloads/libpayload/i386/main.c trunk/payloads/libpayload/libpayload.ldscript Log: libpayload: remove unneeded stack stuff Following on the previous code to streamline the libpayload init code, this removes the now unneeded stack structures. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/i386/head.S =================================================================== --- trunk/payloads/libpayload/i386/head.S 2008-04-04 16:49:09 UTC (rev 3216) +++ trunk/payloads/libpayload/i386/head.S 2008-04-05 01:07:27 UTC (rev 3217) @@ -54,9 +54,9 @@ movl %esp, %esi /* Setup new stack. */ - movl _istack, %ebx + movl $_stack, %ebx - movl (%ebx), %esp + movl %ebx, %esp /* Save old stack pointer. */ pushl %esi Modified: trunk/payloads/libpayload/i386/main.c =================================================================== --- trunk/payloads/libpayload/i386/main.c 2008-04-04 16:49:09 UTC (rev 3216) +++ trunk/payloads/libpayload/i386/main.c 2008-04-05 01:07:27 UTC (rev 3217) @@ -29,23 +29,6 @@ #include <libpayload.h> -/* - * This structure seeds the stack. We provide the return address of our main - * function, and further down, the address of the function that we call when - * we leave and try to restore the original stack. At the very bottom of the - * stack we store the original stack pointer from the calling application. - */ - -extern void _leave(void); - -static struct { - uint32_t esp; -} initial_stack __attribute__ ((section(".istack"))) = { - (uint32_t) &initial_stack, -}; - -void *_istack = &initial_stack; - /** * This is our C entry function - set up the system * and jump into the payload entry point. Modified: trunk/payloads/libpayload/libpayload.ldscript =================================================================== --- trunk/payloads/libpayload/libpayload.ldscript 2008-04-04 16:49:09 UTC (rev 3216) +++ trunk/payloads/libpayload/libpayload.ldscript 2008-04-05 01:07:27 UTC (rev 3217) @@ -73,17 +73,12 @@ . = ALIGN(16); _eheap = .; - _stack = .; + _estack = .; . += STACK_SIZE; . = ALIGN(16); _stack = .; } - /* Put the static bits of our inital stack at the bottom */ - .istack : { - *(.istack) - } - _end = .; /DISCARD/ : { *(.comment) *(.note) *(.note.*) }

1 0

GRUB 2 GSOC 2008 UHCI Support
by joe＠smittys.pointclark.net 05 Apr '08

05 Apr '08

Some exciting news:-) Looks like GRUB is looking at UHCI support for a GSOC 2008 project. Could this be used for coreboot's payload?? http://www.gnu.org/software/grub/grub-soc.html Thanks - Joe

3 5

[PATCH] v3: add defconfig file for alix.1c
by Ward Vandewege 05 Apr '08

05 Apr '08

-- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

2 2

r656 - coreboot-v3/mainboard/pcengines/alix1c
by svn＠coreboot.org 05 Apr '08

05 Apr '08

Author: ward Date: 2008-04-05 02:09:29 +0200 (Sat, 05 Apr 2008) New Revision: 656 Added: coreboot-v3/mainboard/pcengines/alix1c/defconfig Log: We need a defconfig file for the alix.1c under v3. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Added: coreboot-v3/mainboard/pcengines/alix1c/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/defconfig (rev 0) +++ coreboot-v3/mainboard/pcengines/alix1c/defconfig 2008-04-05 00:09:29 UTC (rev 656) @@ -0,0 +1,102 @@ +# +# Automatically generated make config: don't edit +# coreboot version: 3.0.0 +# Sun Feb 24 11:45:09 2008 +# + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="" +# CONFIG_BEEPS is not set + +# +# Mainboard +# +# CONFIG_VENDOR_ADL is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_EMULATION is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_MAINBOARD_NAME="pcengines/alix1c" +CONFIG_BOARD_PCENGINES_ALIX1C=y +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +CONFIG_COREBOOT_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB=480 +CONFIG_ARCH_X86=y +CONFIG_ARCH="x86" +CONFIG_CPU_AMD_GEODELX=y +CONFIG_OPTION_TABLE=y +CONFIG_PIRQ_TABLE=y +CONFIG_CARBASE=0x80000 +CONFIG_CARSIZE=0x8000 + +# +# Compression +# +CONFIG_COMPRESSION_LZMA=y +# CONFIG_COMPRESSION_NRV2B is not set +# CONFIG_DEFAULT_COMPRESSION_LZMA is not set +# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set +CONFIG_DEFAULT_COMPRESSION_NONE=y + +# +# Console +# +CONFIG_CONSOLE=y +CONFIG_CONSOLE_LOGLEVEL_8=y +# CONFIG_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL_COM1=y +# CONFIG_CONSOLE_SERIAL_COM2 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_CONSOLE_USB is not set + +# +# Cosmetic console options +# +# CONFIG_CONSOLE_PREFIX is not set +# CONFIG_CONSOLE_BUFFER is not set + +# +# Devices +# +CONFIG_PCI_OPTION_ROM_RUN=y +# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set +CONFIG_PCI_OPTION_ROM_RUN_VM86=y +# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set +# CONFIG_MULTIPLE_VGA_INIT is not set +# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set + +# +# Power management +# +CONFIG_NORTHBRIDGE_AMD_GEODELX=y +CONFIG_SOUTHBRIDGE_AMD_CS5536=y +CONFIG_SUPERIO_WINBOND_W83627HF=y +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 + +# +# Payload +# +CONFIG_PAYLOAD_PREPARSE_ELF=y +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_FILE="../payload.elf"

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coreboot April 2008