coreboot April 2008

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[patch][v2] fix PCI routing on Geode 5536
by Marc Jones 07 Apr '08

07 Apr '08

This patch fixes the PIR routing setup using the current PIR table for Geode 5536 systems. I think that this is also the v3 db800 and other 5536 Linux booting problems. -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Don't check exclusive IRQ field. This field is rarely used (and not used in the LX tables). There is not a good reason to mask off non-exclusive IRQs. Signed-off-by: Marc Jones(marc.jones(a)amd.com) Index: coreboot-v2/src/arch/i386/boot/pirq_routing.c =================================================================== --- coreboot-v2.orig/src/arch/i386/boot/pirq_routing.c 2008-04-05 12:15:09.000000000 -0600 +++ coreboot-v2/src/arch/i386/boot/pirq_routing.c 2008-04-05 12:15:45.000000000 -0600 @@ -121,7 +121,7 @@ for (j = 0; j < 4; j++) { int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap & pirq_tbl->exclusive_irqs; + int bitmap = pirq_tbl->slots[i].irq[j].bitmap; int irq = 0; printk_debug("INT: %c link: %x bitmap: %x ",

3 2

r3220 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
by svn＠coreboot.org 07 Apr '08

07 Apr '08

Author: mjones Date: 2008-04-07 20:11:03 +0200 (Mon, 07 Apr 2008) New Revision: 3220 Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c Log: Re-add files I deleted by mistake in r3219. They are meant for a different patch. Signed-off-by: Marc Jones (marc.jones(a)amd.com) Acked-by: Marc Jones (marc.jones(a)amd.com) Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c 2008-04-07 18:11:03 UTC (rev 3220) @@ -0,0 +1,312 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cpu/x86/tsc.h> + + +static u32 get_vstime(u32 nodeid, u32 slam) +{ + u32 val; + u32 v; + device_t dev; + +#if defined(__ROMCC__) + dev = NODE_PCI(nodeid, 3); +#else + dev = get_node_pci(nodeid, 3); +#endif + + val = pci_read_config32(dev, 0xd8); + + val >>= slam?0:4; + val &= 7; + + switch (val) { + case 4: v = 60; break; + case 5: v = 100; break; + case 6: v = 200; break; + case 7: v = 500; break; + default: + v = (val+1)*10; // in us + } + + return v; +} + +static void udelay_tsc(u32 us) +{ + /* Use TSC to delay because it is fixed, ie. it will not changed with p-states. + * Also, We use the APIC TIMER register is to hold flags for AP init. + */ + u32 dword; + tsc_t tsc, tsc1, tscd; + u32 d = 0x00000200; //800Mhz or 200Mhz or 1.6G or get the NBFID at first + u32 dn = 0x1000000/2; // howmany us need to use hi + + tscd.hi = us/dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if((dword<tsc1.lo) || (dword<tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi+= tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi>tsc1.hi) || ((tsc.hi==tsc1.hi) && (tsc.lo>tsc1.lo))); + +} + +#ifdef __ROMCC__ +void udelay(u32 usecs) +{ + udelay_tsc(usecs); +} +#endif + +static u32 set_vid(u32 newvid, u32 bit_offset, u32 nodeid, u32 coreid) +{ + u32 val; + msr_t msr; + u32 curvid; + u32 slam; + u32 delay; + u32 count = 3; + device_t dev; + + msr = rdmsr(0xc0010071);//status + curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits + + if(newvid == curvid) return curvid; + +#if defined(__ROMCC__) + dev = NODE_PCI(nodeid, 3); +#else + dev = get_node_pci(nodeid, 3); +#endif + + val = pci_read_config32(dev, 0xa0); + + slam = (val >> 29) & 1; + delay = get_vstime(nodeid, slam); + + if(!slam) { + if(curvid>newvid) { + count = (curvid - newvid) * 2; + } else { + count = (newvid - curvid) * 2; + } + } + + while(count-->0) { + if(slam) { + curvid = newvid; + } + else { //ramp + if(curvid>newvid) { + curvid--; + } else { + curvid++; + } + } + + msr = rdmsr(0xc0010070); //control + msr.lo &= ~(0x7f<<bit_offset); + msr.lo |= (curvid<<bit_offset); + wrmsr(0xc0010070, msr); // how about all copys, APIC or PCI conf space? + + udelay_tsc(delay); + + msr = rdmsr(0xc0010071);//status + curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits + + if(curvid == newvid) break; + + } + + return curvid; +} + + +static u32 set_nb_vid(u32 newvid, u32 nodeid, u32 coreid) +{ + return set_vid(newvid, 25, nodeid, coreid); +} + + +static u32 set_core_vid(u32 newvid, u32 nodeid, u32 coreid) +{ + return set_vid(newvid, 9, nodeid, coreid); +} + + +static unsigned set_cof(u32 val, u32 mask, u32 nodeid, u32 coreid) +{ + msr_t msr; + int count = 3; + + val &= mask; + + // FIXME: What is count for? Why 3 times? What about node and core id? + while(count-- > 0) { + + msr = rdmsr(0xc0010071); + msr.lo &= mask; + if(msr.lo == val) break; + + msr = rdmsr(0xc0010070); + msr.lo &= ~(mask); + msr.lo |= val; + wrmsr(0xc0010070, msr); + } + + return msr.lo; +} + +static u32 set_core_cof(u32 fid, u32 did, u32 nodeid, u32 coreid) +{ + u32 val; + u32 mask; + + mask = (7<<6) | 0x3f; + val = ((did & 7)<<6) | (fid & 0x3f); + + return set_cof(val, mask, nodeid, coreid); + +} + + +static u32 set_nb_cof(u32 did, u32 nodeid, u32 coreid) // fid need warmreset +{ + u32 val; + u32 mask; + + mask = 1<<22; + val = (did & 1)<<22; + + return set_cof(val, mask, nodeid, coreid); + +} + + +/* set vid and cof for core and nb after warm reset is not started by BIOS */ +static void set_core_nb_max_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // P0 +{ + msr_t msr; + u32 val; + u32 vid; + u32 mask; + u32 did; + device_t dev; + + msr = rdmsr(0xc0010064); + +#if defined(__ROMCC__) + dev = NODE_PCI(nodeid, 3); +#else + dev = get_node_pci(nodeid, 3); +#endif + + val = pci_read_config32(dev, 0xa0); + if((val>>8) & 1) { // PVI + vid = (msr.lo >> 25) & 0x7f; + } else { //SVI + vid = (msr.lo >> 9) & 0x7f; + } + set_core_vid(vid, nodeid, coreid); + + mask = (0x7<<6) | 0x3f; + val = msr.lo & mask; + set_cof(val, mask, nodeid, coreid); + + //set nb cof and vid + did = (msr.lo >> 22) & 1; + vid = (msr.lo >> 25) & 0x7f; + if(did) { + set_nb_cof(did, nodeid, coreid); + set_nb_vid(vid, nodeid, coreid); + } else { + set_nb_vid(vid, nodeid, coreid); + set_nb_cof(did, nodeid, coreid); + } + + //set the p state + msr.hi = 0; + msr.lo = 0; + wrmsr(0xc0010062, msr); + +} + + +/* set vid and cof for core and nb after warm reset is not started by BIOS */ +static void set_core_nb_min_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // Px +{ + msr_t msr; + u32 val; + u32 vid; + u32 mask; + u32 did; + u32 pstate; + device_t dev; + +#if defined(__ROMCC__) + dev = NODE_PCI(nodeid, 3); +#else + dev = get_node_pci(nodeid, 3); +#endif + + + val = pci_read_config32(dev, 0xdc); //PstateMaxVal + + pstate = (val >> 8) & 0x7; + + msr = rdmsr(0xc0010064 + pstate); + + mask = (7<<6) | 0x3f; + val = msr.lo & mask; + set_cof(val, mask, nodeid, coreid); + + val = pci_read_config32(dev, 0xa0); + if((val>>8) & 1) { // PVI + vid = (msr.lo>>25) & 0x7f; + } else { //SVI + vid = (msr.lo>>9) & 0x7f; + } + set_core_vid(vid, nodeid, coreid); + + //set nb cof and vid + did = (msr.lo >> 22) & 1; + vid = (msr.lo >> 25) & 0x7f; + if(did) { + set_nb_cof(did, nodeid, coreid); + set_nb_vid(vid, nodeid, coreid); + } else { + set_nb_vid(vid, nodeid, coreid); + set_nb_cof(did, nodeid, coreid); + } + + //set the p state + msr.hi = 0; + msr.lo = pstate; + wrmsr(0xc0010062, msr); +} Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h 2008-04-07 18:11:03 UTC (rev 3220) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2005 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x07, 0x20, 0x08, 0x02, 0x18, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x66, 0x70, 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x44, 0x06, 0x00, 0x00, +0xff, 0xff, 0xff, 0xff, 0xa4, 0x06, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +0x72, 0x09, 0x00, 0x00, 0x70, 0x09, 0x00, 0x00, 0x9b, 0x0b, 0x00, 0x00, +0xff, 0xff, 0xff, 0xff, 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x37, +0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07, +0x37, 0xfc, 0x03, 0xf8, 0xc0, 0xff, 0xf7, 0x00, 0x80, 0xff, 0xc0, 0x3f, +0x9b, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00, +0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0x40, 0x37, 0x6b, +0xff, 0xfb, 0xfd, 0xff, 0x57, 0x7d, 0xf0, 0xcd, 0xff, 0x1f, 0xb7, 0xfe, +0xc0, 0xcf, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h 2008-04-07 18:11:03 UTC (rev 3220) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2005 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x07, 0x20, 0x27, 0x06, 0x33, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h 2008-04-07 18:11:03 UTC (rev 3220) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2005 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x07, 0x20, 0x23, 0x07, 0x35, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include "../../../northbridge/amd/amdfam10/amdfam10.h" + +#include <cpu/amd/model_10xxx_rev.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/mem.h> + +#include <cpu/amd/quadcore.h> + +#include <cpu/amd/model_10xxx_msr.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern device_t get_node_pci(u32 nodeid, u32 fn); + +#include "fidvid_common.c" + +#define PSTATES_DEBUG 0 + + + +static void inline dump_msr_pstates(u32 nodes) +{ +#if PSTATES_DEBUG==1 + int i, j; + for(j=0; j<5; j++) { + printk_debug("P%d:", j); + for(i=0;i<nodes;i++) { + printk_debug(" [%08x %08x] ", sysconf.msr_pstate[i*5+j].hi, sysconf.msr_pstate[i*5+j].lo); + } + printk_debug("\n"); + } +#endif +} + + +static void inline dump_p(const char *p_c, u32 nodes, u32 *p) +{ +#if PSTATES_DEBUG==1 + int i, j; + printk_debug(p_c); + printk_debug("p:"); + for(i=0;i<nodes;i++) { + printk_debug(" %d ", p[i]); + } + printk_debug("\n"); + +#endif +} + + +//according the pstate and make it work conformed to mixed conf system +static u32 get_pwrvalue(u32 val) +{ + u32 times; + switch((val>>8)&3) { + case 0: times = 1000; break; + case 1: times = 100; break; + case 2: times = 10; break; + default: + //error + times = 1; + } + + return (val & 0xff) * times; + +} + + +static u32 get_powerstep(u32 val) +{ + u32 time; + if(val<4) {time = (4 - val)*100;} + else if(val<8) { time = (9+4-val)*10;} + else { time = (10+8-val) * 5; } + + return time; + +} + + +static u32 get_plllocktime(u32 val) +{ + u32 time; + switch(val) { + case 0: + case 1: + case 2: + case 3: + time = val+1; break; + case 4: time = 8; break; + case 5: time = 16; break; + default: + //erro2 + time = 1; + } + return time; +} + + +static void disable_pstate(u32 nodes, u32 *p) +{ + int i; + + for(i=0;i<nodes; i++) { + sysconf.msr_pstate[i*5+p[i]].hi &= ~(1<<(63-32)); + } +} + + +static void match_pstate(u32 nodes, u32 *p) +{ + int i; + u32 corecof_min, pwrvalue_max, pwrval_max; + u32 enable; + enable = (sysconf.msr_pstate[0*5+p[0]].hi >> 31); + if(!enable) { + disable_pstate(nodes, p); + return; + } + corecof_min = ((sysconf.msr_pstate[0*5+p[0]].lo & 0x3f) + 0x10)>>((sysconf.msr_pstate[0*5+p[0]].lo>>6) & 7); + pwrval_max = sysconf.msr_pstate[0*5+p[0]].hi & 0x3ff; + pwrvalue_max = get_pwrvalue(pwrval_max); + + for(i=1; i<nodes; i++) { + enable = (sysconf.msr_pstate[0*5+p[i]].hi >> 31); + if(!enable) { + disable_pstate(nodes, p); + return; + } + + u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7); + u32 corecof = ((sysconf.msr_pstate[i*5+p[i]].lo & 0x3f) + 0x10)>>coredid; + if(corecof<corecof_min) corecof_min = corecof; + u32 pwrval, pwrvalue; + pwrval = sysconf.msr_pstate[i*5+p[i]].hi & 0x3ff; + pwrvalue = get_pwrvalue(pwrval); + if(pwrvalue>pwrvalue_max) { + pwrvalue_max = pwrvalue; + pwrval_max = pwrval; + } + } + + for(i=0; i<nodes; i++) { + u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7); + u32 corefid = (corecof_min<<coredid); + while(corefid<0x10) { + coredid++; + corefid = (corecof_min<<coredid); + } + sysconf.msr_pstate[i*5+p[i]].lo &= ~(0x1ff); + sysconf.msr_pstate[i*5+p[i]].lo |= (corefid - 0x10) | (coredid << 6); + sysconf.msr_pstate[i*5+p[i]].hi &= ~(0x3ff); + sysconf.msr_pstate[i*5+p[i]].hi |= pwrval_max; + } +} + + +static void match_pstates(u32 nodes, u32 *p, u32 *px) +{ + int i; + int j; + u32 p_int[NODE_NUMS]; + + int jj=1; + u32 end = 0; + for(i=0;i<nodes; i++) { + p_int[i] = px[i]; + } + while(1){ + for(i=0;i<nodes; i++) { + if(px[i]<=(p[i]+jj)) { + end = 1; + break; + } + } + if(!end) { + for(i=0; i<nodes; i++) { + p_int[i] = px[i] - jj; + } + match_pstate(nodes, p_int); + dump_p("P int\n", nodes, p_int); + jj++; + } + else { + for(i=0;i<nodes; i++) { + for(j=p[i]+1; j<p_int[i]; j++) { + sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); + } + } + break; + } + } +} + + +void prep_pstates_all(void) +{ + device_t f3_dev[NODE_NUMS], f4_dev[NODE_NUMS]; + u32 p[NODE_NUMS]; + u32 p_htc[NODE_NUMS]; + u32 p_lowest[NODE_NUMS]; + u32 htc_cap = 1; + u32 lowest_htc_equal = 0; + + u32 nodes = sysconf.nodes; + int i; + int j; + u32 val; + u32 nbdid; + u32 nbvid0; + u32 nbvid1; + + for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage... + f3_dev[i] = get_node_pci(i, 3); + f4_dev[i] = get_node_pci(i, 4); + } + + for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage... + val = pci_read_config32(f4_dev[i], 0x1f4); + nbvid0 = val & 0x3f; + nbvid1 = (val>>7) & 0x3f; + for(j=0; j<5; j++) { + val = pci_read_config32(f4_dev[i], 0x1e0 + (j<<2)); + nbdid = ((val>>16) & 1); + sysconf.msr_pstate[i*5+j].lo = (val & 0xffff) | (nbdid<<22) | ((nbdid?nbvid1:nbvid0)<<25); + sysconf.msr_pstate[i*5+j].hi = (((val>>17) & 0x3ff) << (32-32)) | (((val>>27) & 1)<<(63-32)); + } + } + + dump_msr_pstates(nodes); + + sysconf.needs_update_pstate_msrs = 0; // normal case for all sockets are installed same conf CPU + + for(i=1; (i<nodes) && (!sysconf.needs_update_pstate_msrs); i++) { + for(j=0; j<5; j++) { + if((sysconf.msr_pstate[i*5+j].lo != sysconf.msr_pstate[0*5+j].lo) || (sysconf.msr_pstate[i*5+j].hi != sysconf.msr_pstate[0*5+j].hi)) { + sysconf.needs_update_pstate_msrs = 1; + break; + } + } + } + + if(sysconf.needs_update_pstate_msrs) { + + // update msr_pstate for mixed conf + + //P0 + /* Match P0 cpu cof for all cpu cores to the lowest P0 cpu cof value in the coherent fabric, and match P0 power for all cpu cores to the highest P0 power value */ + for(i=0;i<nodes; i++) p[i] = 0; + match_pstate(nodes, p); + dump_p("P0\n", nodes, p); + dump_msr_pstates(nodes); + + + //p_htc + for(i=0;i<nodes; i++) { + val = pci_read_config32(f3_dev[i], 0xe8); //htc cap + if(!(val & (1<<10))) { + htc_cap = 0; + break; + } + + //HtcPstateLimit + val = pci_read_config32(f3_dev[i], 0x64); + p_htc[i] = (((val>>28) & 7)); + if(p_htc[i] == 0) { + val |= 1<<28; + pci_write_config32(f3_dev[i], 0x64, val); + val = pci_read_config32(f3_dev[i], 0x68); //stc + val &= ~(7<<28); + val |= (1<<28); + pci_write_config32(f3_dev[i], 0x68, val); + + p_htc[i] = 1; + } + } + if(htc_cap) { + match_pstate(nodes, p_htc); + + dump_p("P_htc\n", nodes, p_htc); + dump_msr_pstates(nodes); + } + + //p_lowest + for(i=0;i<nodes; i++) { + p_lowest[i] = 0; + for(j=1; j<5; j++) { + if(sysconf.msr_pstate[i*5+j].hi & (1<<(63-32))) { + p_lowest[i] = j; + } + } + // PstateMaxVal + val = pci_read_config32(f3_dev[i], 0xdc); + if(p_lowest[i]>((val>>8) & 7)) { + val &= ~(7<<8); + val |= (p_lowest[i])<<8; + pci_write_config32(f3_dev[i], 0xdc, val); + } + else { + p_lowest[i] = (val>>8) & 7; + } + } + if(htc_cap) { + for(i=0;i<nodes; i++) { + if(p_lowest[i]==p_htc[i]){ + lowest_htc_equal = 1; + break; + } + } + } + if(lowest_htc_equal) { + for(i=0;i<nodes; i++) { + // PstateMaxVal + val = pci_read_config32(f3_dev[i], 0xdc); + val &= ~(7<<8); + val |= p_htc[i]; + pci_write_config32(f3_dev[i], 0xdc, val); + for(j=p_htc[i]+1; j<5; j++) { + sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); + } + } + } else { + match_pstate(nodes, p_lowest); + for(i=0; i<nodes; i++) { + for(j=p_lowest[i]+1; j<5; j++) { + sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); + } + } + + } + + dump_p("Px\n", nodes, p_lowest); + dump_msr_pstates(nodes); + + + if(htc_cap) { + //p_up_int + match_pstates(nodes, p, p_htc); + + dump_msr_pstates(nodes); + + //p_lower_int + match_pstates(nodes, p_htc, p_lowest); + } else { + match_pstates(nodes, p, p_lowest); + } + + dump_msr_pstates(nodes); + + } + + // fill data into p_state + for(i=0; i<nodes; i++) { + sysconf.p_state_num = 0; + u32 corefid_equal = 1; + u32 corefid; + corefid = (sysconf.msr_pstate[i*5+0].lo & 0x3f); + for(j=1; j<5; j++) { + msr_t *msr_pstate; + msr_pstate = &(sysconf.msr_pstate[i*5+j]); + if(!(msr_pstate->hi & (1<<(63-32)) )) continue; + if((msr_pstate->lo & 0x3f) != corefid) { + corefid_equal = 0; + break; + } + } + for(j=0; j<5; j++) { + struct p_state_t *p_state; + msr_t *msr_pstate; + msr_pstate = &sysconf.msr_pstate[i*5+j]; + if(!(msr_pstate->hi & (1<<(63-32)) )) continue; + p_state = &sysconf.p_state[i*5+sysconf.p_state_num]; + u32 coredid = ((msr_pstate->lo>>6) & 7); + u32 corecof = ((msr_pstate->lo & 0x3f) + 0x10)>>coredid; + p_state->corefreq = corecof; + + u32 pwrval, pwrvalue; + pwrval = msr_pstate->hi & 0x3ff; + pwrvalue = get_pwrvalue(pwrval); + p_state->power = pwrvalue; + + u32 lat; + val = pci_read_config32(f3_dev[i], 0xd4); + lat = 15 * (get_powerstep((val>>24)& 0xf)+get_powerstep((val>>20)& 0xf)) /1000; + if(!corefid_equal) { + val = pci_read_config32(f3_dev[i], 0xa0); + lat += get_plllocktime((val >> 11 ) & 7); + } + p_state->transition_lat = lat; + p_state->busmaster_lat = lat; + + p_state->control = j; + p_state->status = j; + + sysconf.p_state_num++; + } + // don't need look at other nodes + if(!sysconf.p_state_num) break; + } +} + + +//it will update pstates info from ram into MSR +void init_pstates(device_t dev, u32 nodeid, u32 coreid) +{ + int j; + msr_t msr; + + if(sysconf.needs_update_pstate_msrs) { + for(j=0; j < 5; j++) { + wrmsr(0xC0010064 + j, sysconf.msr_pstate[nodeid * 5 + j]); + } + } + + /* Set TSC Freq Select: TSC increments at the rate of the core P-state 0 */ + msr = rdmsr(0xC0010015); + msr.lo |= 1 << 24; + wrmsr(0xC0010015, msr); + + // Enter the state P0 + //FIXME I don't think that this works correctly. May depend on early fid/vid setup. + if(sysconf.p_state_num) + set_core_nb_max_pstate_after_other_warm_reset(nodeid, coreid); + +}

1 0

Re: [coreboot] r3219 - in trunk/coreboot-v2/src: arch/i386/boot cpu/amd/model_10xxx
by Marc Jones 07 Apr '08

07 Apr '08

svn(a)coreboot.org wrote: > Author: mjones > Date: 2008-04-07 19:49:57 +0200 (Mon, 07 Apr 2008) > New Revision: 3219 > > Removed: > trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c > trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h > trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h > trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h > trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c > Modified: > trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c > Log: > Don't check exclusive IRQ fieldin the PIR table. > This field is rarely used (and not used in the LX tables). > There is not a good reason to mask off non-exclusive IRQs. > > Signed-off-by: Marc Jones(marc.jones(a)amd.com) > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > > Ah! Sorry, I removed files that go with a different patch. Fixing.... Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

1 0

r3219 - in trunk/coreboot-v2/src: arch/i386/boot cpu/amd/model_10xxx
by svn＠coreboot.org 07 Apr '08

07 Apr '08

Author: mjones Date: 2008-04-07 19:49:57 +0200 (Mon, 07 Apr 2008) New Revision: 3219 Removed: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c Log: Don't check exclusive IRQ fieldin the PIR table. This field is rarely used (and not used in the LX tables). There is not a good reason to mask off non-exclusive IRQs. Signed-off-by: Marc Jones(marc.jones(a)amd.com) Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2008-04-06 04:26:19 UTC (rev 3218) +++ trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2008-04-07 17:49:57 UTC (rev 3219) @@ -121,7 +121,7 @@ for (j = 0; j < 4; j++) { int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap & pirq_tbl->exclusive_irqs; + int bitmap = pirq_tbl->slots[i].irq[j].bitmap; int irq = 0; printk_debug("INT: %c link: %x bitmap: %x ", Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c 2008-04-06 04:26:19 UTC (rev 3218) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c 2008-04-07 17:49:57 UTC (rev 3219) @@ -1,312 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <cpu/x86/tsc.h> - - -static u32 get_vstime(u32 nodeid, u32 slam) -{ - u32 val; - u32 v; - device_t dev; - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - val = pci_read_config32(dev, 0xd8); - - val >>= slam?0:4; - val &= 7; - - switch (val) { - case 4: v = 60; break; - case 5: v = 100; break; - case 6: v = 200; break; - case 7: v = 500; break; - default: - v = (val+1)*10; // in us - } - - return v; -} - -static void udelay_tsc(u32 us) -{ - /* Use TSC to delay because it is fixed, ie. it will not changed with p-states. - * Also, We use the APIC TIMER register is to hold flags for AP init. - */ - u32 dword; - tsc_t tsc, tsc1, tscd; - u32 d = 0x00000200; //800Mhz or 200Mhz or 1.6G or get the NBFID at first - u32 dn = 0x1000000/2; // howmany us need to use hi - - tscd.hi = us/dn; - tscd.lo = (us - tscd.hi * dn) * d; - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if((dword<tsc1.lo) || (dword<tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi+= tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi>tsc1.hi) || ((tsc.hi==tsc1.hi) && (tsc.lo>tsc1.lo))); - -} - -#ifdef __ROMCC__ -void udelay(u32 usecs) -{ - udelay_tsc(usecs); -} -#endif - -static u32 set_vid(u32 newvid, u32 bit_offset, u32 nodeid, u32 coreid) -{ - u32 val; - msr_t msr; - u32 curvid; - u32 slam; - u32 delay; - u32 count = 3; - device_t dev; - - msr = rdmsr(0xc0010071);//status - curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits - - if(newvid == curvid) return curvid; - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - val = pci_read_config32(dev, 0xa0); - - slam = (val >> 29) & 1; - delay = get_vstime(nodeid, slam); - - if(!slam) { - if(curvid>newvid) { - count = (curvid - newvid) * 2; - } else { - count = (newvid - curvid) * 2; - } - } - - while(count-->0) { - if(slam) { - curvid = newvid; - } - else { //ramp - if(curvid>newvid) { - curvid--; - } else { - curvid++; - } - } - - msr = rdmsr(0xc0010070); //control - msr.lo &= ~(0x7f<<bit_offset); - msr.lo |= (curvid<<bit_offset); - wrmsr(0xc0010070, msr); // how about all copys, APIC or PCI conf space? - - udelay_tsc(delay); - - msr = rdmsr(0xc0010071);//status - curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits - - if(curvid == newvid) break; - - } - - return curvid; -} - - -static u32 set_nb_vid(u32 newvid, u32 nodeid, u32 coreid) -{ - return set_vid(newvid, 25, nodeid, coreid); -} - - -static u32 set_core_vid(u32 newvid, u32 nodeid, u32 coreid) -{ - return set_vid(newvid, 9, nodeid, coreid); -} - - -static unsigned set_cof(u32 val, u32 mask, u32 nodeid, u32 coreid) -{ - msr_t msr; - int count = 3; - - val &= mask; - - // FIXME: What is count for? Why 3 times? What about node and core id? - while(count-- > 0) { - - msr = rdmsr(0xc0010071); - msr.lo &= mask; - if(msr.lo == val) break; - - msr = rdmsr(0xc0010070); - msr.lo &= ~(mask); - msr.lo |= val; - wrmsr(0xc0010070, msr); - } - - return msr.lo; -} - -static u32 set_core_cof(u32 fid, u32 did, u32 nodeid, u32 coreid) -{ - u32 val; - u32 mask; - - mask = (7<<6) | 0x3f; - val = ((did & 7)<<6) | (fid & 0x3f); - - return set_cof(val, mask, nodeid, coreid); - -} - - -static u32 set_nb_cof(u32 did, u32 nodeid, u32 coreid) // fid need warmreset -{ - u32 val; - u32 mask; - - mask = 1<<22; - val = (did & 1)<<22; - - return set_cof(val, mask, nodeid, coreid); - -} - - -/* set vid and cof for core and nb after warm reset is not started by BIOS */ -static void set_core_nb_max_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // P0 -{ - msr_t msr; - u32 val; - u32 vid; - u32 mask; - u32 did; - device_t dev; - - msr = rdmsr(0xc0010064); - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - val = pci_read_config32(dev, 0xa0); - if((val>>8) & 1) { // PVI - vid = (msr.lo >> 25) & 0x7f; - } else { //SVI - vid = (msr.lo >> 9) & 0x7f; - } - set_core_vid(vid, nodeid, coreid); - - mask = (0x7<<6) | 0x3f; - val = msr.lo & mask; - set_cof(val, mask, nodeid, coreid); - - //set nb cof and vid - did = (msr.lo >> 22) & 1; - vid = (msr.lo >> 25) & 0x7f; - if(did) { - set_nb_cof(did, nodeid, coreid); - set_nb_vid(vid, nodeid, coreid); - } else { - set_nb_vid(vid, nodeid, coreid); - set_nb_cof(did, nodeid, coreid); - } - - //set the p state - msr.hi = 0; - msr.lo = 0; - wrmsr(0xc0010062, msr); - -} - - -/* set vid and cof for core and nb after warm reset is not started by BIOS */ -static void set_core_nb_min_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // Px -{ - msr_t msr; - u32 val; - u32 vid; - u32 mask; - u32 did; - u32 pstate; - device_t dev; - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - - val = pci_read_config32(dev, 0xdc); //PstateMaxVal - - pstate = (val >> 8) & 0x7; - - msr = rdmsr(0xc0010064 + pstate); - - mask = (7<<6) | 0x3f; - val = msr.lo & mask; - set_cof(val, mask, nodeid, coreid); - - val = pci_read_config32(dev, 0xa0); - if((val>>8) & 1) { // PVI - vid = (msr.lo>>25) & 0x7f; - } else { //SVI - vid = (msr.lo>>9) & 0x7f; - } - set_core_vid(vid, nodeid, coreid); - - //set nb cof and vid - did = (msr.lo >> 22) & 1; - vid = (msr.lo >> 25) & 0x7f; - if(did) { - set_nb_cof(did, nodeid, coreid); - set_nb_vid(vid, nodeid, coreid); - } else { - set_nb_vid(vid, nodeid, coreid); - set_nb_cof(did, nodeid, coreid); - } - - //set the p state - msr.hi = 0; - msr.lo = pstate; - wrmsr(0xc0010062, msr); -} Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h 2008-04-06 04:26:19 UTC (rev 3218) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h 2008-04-07 17:49:57 UTC (rev 3219) @@ -1,163 +0,0 @@ -/* - ============================================================ - (c) Advanced Micro Devices, Inc., 2004-2005 - - The enclosed microcode is intended to be used with AMD - Microprocessors. You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - -0x07, 0x20, 0x08, 0x02, 0x18, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0x66, 0x70, 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x44, 0x06, 0x00, 0x00, -0xff, 0xff, 0xff, 0xff, 0xa4, 0x06, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, -0x72, 0x09, 0x00, 0x00, 0x70, 0x09, 0x00, 0x00, 0x9b, 0x0b, 0x00, 0x00, -0xff, 0xff, 0xff, 0xff, 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x37, -0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07, -0x37, 0xfc, 0x03, 0xf8, 0xc0, 0xff, 0xf7, 0x00, 0x80, 0xff, 0xc0, 0x3f, -0x9b, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00, -0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0x40, 0x37, 0x6b, -0xff, 0xfb, 0xfd, 0xff, 0x57, 0x7d, 0xf0, 0xcd, 0xff, 0x1f, 0xb7, 0xfe, -0xc0, 0xcf, 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - -0x07, 0x20, 0x27, 0x06, 0x33, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00, -0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - -0x07, 0x20, 0x23, 0x07, 0x35, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00, -0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c 2008-04-06 04:26:19 UTC (rev 3218) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c 2008-04-07 17:49:57 UTC (rev 3219) @@ -1,456 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/pae.h> -#include <pc80/mc146818rtc.h> -#include <cpu/x86/lapic.h> - -#include "../../../northbridge/amd/amdfam10/amdfam10.h" - -#include <cpu/amd/model_10xxx_rev.h> -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/mem.h> - -#include <cpu/amd/quadcore.h> - -#include <cpu/amd/model_10xxx_msr.h> -#include <cpu/amd/amdfam10_sysconf.h> - -extern device_t get_node_pci(u32 nodeid, u32 fn); - -#include "fidvid_common.c" - -#define PSTATES_DEBUG 0 - - - -static void inline dump_msr_pstates(u32 nodes) -{ -#if PSTATES_DEBUG==1 - int i, j; - for(j=0; j<5; j++) { - printk_debug("P%d:", j); - for(i=0;i<nodes;i++) { - printk_debug(" [%08x %08x] ", sysconf.msr_pstate[i*5+j].hi, sysconf.msr_pstate[i*5+j].lo); - } - printk_debug("\n"); - } -#endif -} - - -static void inline dump_p(const char *p_c, u32 nodes, u32 *p) -{ -#if PSTATES_DEBUG==1 - int i, j; - printk_debug(p_c); - printk_debug("p:"); - for(i=0;i<nodes;i++) { - printk_debug(" %d ", p[i]); - } - printk_debug("\n"); - -#endif -} - - -//according the pstate and make it work conformed to mixed conf system -static u32 get_pwrvalue(u32 val) -{ - u32 times; - switch((val>>8)&3) { - case 0: times = 1000; break; - case 1: times = 100; break; - case 2: times = 10; break; - default: - //error - times = 1; - } - - return (val & 0xff) * times; - -} - - -static u32 get_powerstep(u32 val) -{ - u32 time; - if(val<4) {time = (4 - val)*100;} - else if(val<8) { time = (9+4-val)*10;} - else { time = (10+8-val) * 5; } - - return time; - -} - - -static u32 get_plllocktime(u32 val) -{ - u32 time; - switch(val) { - case 0: - case 1: - case 2: - case 3: - time = val+1; break; - case 4: time = 8; break; - case 5: time = 16; break; - default: - //erro2 - time = 1; - } - return time; -} - - -static void disable_pstate(u32 nodes, u32 *p) -{ - int i; - - for(i=0;i<nodes; i++) { - sysconf.msr_pstate[i*5+p[i]].hi &= ~(1<<(63-32)); - } -} - - -static void match_pstate(u32 nodes, u32 *p) -{ - int i; - u32 corecof_min, pwrvalue_max, pwrval_max; - u32 enable; - enable = (sysconf.msr_pstate[0*5+p[0]].hi >> 31); - if(!enable) { - disable_pstate(nodes, p); - return; - } - corecof_min = ((sysconf.msr_pstate[0*5+p[0]].lo & 0x3f) + 0x10)>>((sysconf.msr_pstate[0*5+p[0]].lo>>6) & 7); - pwrval_max = sysconf.msr_pstate[0*5+p[0]].hi & 0x3ff; - pwrvalue_max = get_pwrvalue(pwrval_max); - - for(i=1; i<nodes; i++) { - enable = (sysconf.msr_pstate[0*5+p[i]].hi >> 31); - if(!enable) { - disable_pstate(nodes, p); - return; - } - - u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7); - u32 corecof = ((sysconf.msr_pstate[i*5+p[i]].lo & 0x3f) + 0x10)>>coredid; - if(corecof<corecof_min) corecof_min = corecof; - u32 pwrval, pwrvalue; - pwrval = sysconf.msr_pstate[i*5+p[i]].hi & 0x3ff; - pwrvalue = get_pwrvalue(pwrval); - if(pwrvalue>pwrvalue_max) { - pwrvalue_max = pwrvalue; - pwrval_max = pwrval; - } - } - - for(i=0; i<nodes; i++) { - u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7); - u32 corefid = (corecof_min<<coredid); - while(corefid<0x10) { - coredid++; - corefid = (corecof_min<<coredid); - } - sysconf.msr_pstate[i*5+p[i]].lo &= ~(0x1ff); - sysconf.msr_pstate[i*5+p[i]].lo |= (corefid - 0x10) | (coredid << 6); - sysconf.msr_pstate[i*5+p[i]].hi &= ~(0x3ff); - sysconf.msr_pstate[i*5+p[i]].hi |= pwrval_max; - } -} - - -static void match_pstates(u32 nodes, u32 *p, u32 *px) -{ - int i; - int j; - u32 p_int[NODE_NUMS]; - - int jj=1; - u32 end = 0; - for(i=0;i<nodes; i++) { - p_int[i] = px[i]; - } - while(1){ - for(i=0;i<nodes; i++) { - if(px[i]<=(p[i]+jj)) { - end = 1; - break; - } - } - if(!end) { - for(i=0; i<nodes; i++) { - p_int[i] = px[i] - jj; - } - match_pstate(nodes, p_int); - dump_p("P int\n", nodes, p_int); - jj++; - } - else { - for(i=0;i<nodes; i++) { - for(j=p[i]+1; j<p_int[i]; j++) { - sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); - } - } - break; - } - } -} - - -void prep_pstates_all(void) -{ - device_t f3_dev[NODE_NUMS], f4_dev[NODE_NUMS]; - u32 p[NODE_NUMS]; - u32 p_htc[NODE_NUMS]; - u32 p_lowest[NODE_NUMS]; - u32 htc_cap = 1; - u32 lowest_htc_equal = 0; - - u32 nodes = sysconf.nodes; - int i; - int j; - u32 val; - u32 nbdid; - u32 nbvid0; - u32 nbvid1; - - for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage... - f3_dev[i] = get_node_pci(i, 3); - f4_dev[i] = get_node_pci(i, 4); - } - - for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage... - val = pci_read_config32(f4_dev[i], 0x1f4); - nbvid0 = val & 0x3f; - nbvid1 = (val>>7) & 0x3f; - for(j=0; j<5; j++) { - val = pci_read_config32(f4_dev[i], 0x1e0 + (j<<2)); - nbdid = ((val>>16) & 1); - sysconf.msr_pstate[i*5+j].lo = (val & 0xffff) | (nbdid<<22) | ((nbdid?nbvid1:nbvid0)<<25); - sysconf.msr_pstate[i*5+j].hi = (((val>>17) & 0x3ff) << (32-32)) | (((val>>27) & 1)<<(63-32)); - } - } - - dump_msr_pstates(nodes); - - sysconf.needs_update_pstate_msrs = 0; // normal case for all sockets are installed same conf CPU - - for(i=1; (i<nodes) && (!sysconf.needs_update_pstate_msrs); i++) { - for(j=0; j<5; j++) { - if((sysconf.msr_pstate[i*5+j].lo != sysconf.msr_pstate[0*5+j].lo) || (sysconf.msr_pstate[i*5+j].hi != sysconf.msr_pstate[0*5+j].hi)) { - sysconf.needs_update_pstate_msrs = 1; - break; - } - } - } - - if(sysconf.needs_update_pstate_msrs) { - - // update msr_pstate for mixed conf - - //P0 - /* Match P0 cpu cof for all cpu cores to the lowest P0 cpu cof value in the coherent fabric, and match P0 power for all cpu cores to the highest P0 power value */ - for(i=0;i<nodes; i++) p[i] = 0; - match_pstate(nodes, p); - dump_p("P0\n", nodes, p); - dump_msr_pstates(nodes); - - - //p_htc - for(i=0;i<nodes; i++) { - val = pci_read_config32(f3_dev[i], 0xe8); //htc cap - if(!(val & (1<<10))) { - htc_cap = 0; - break; - } - - //HtcPstateLimit - val = pci_read_config32(f3_dev[i], 0x64); - p_htc[i] = (((val>>28) & 7)); - if(p_htc[i] == 0) { - val |= 1<<28; - pci_write_config32(f3_dev[i], 0x64, val); - val = pci_read_config32(f3_dev[i], 0x68); //stc - val &= ~(7<<28); - val |= (1<<28); - pci_write_config32(f3_dev[i], 0x68, val); - - p_htc[i] = 1; - } - } - if(htc_cap) { - match_pstate(nodes, p_htc); - - dump_p("P_htc\n", nodes, p_htc); - dump_msr_pstates(nodes); - } - - //p_lowest - for(i=0;i<nodes; i++) { - p_lowest[i] = 0; - for(j=1; j<5; j++) { - if(sysconf.msr_pstate[i*5+j].hi & (1<<(63-32))) { - p_lowest[i] = j; - } - } - // PstateMaxVal - val = pci_read_config32(f3_dev[i], 0xdc); - if(p_lowest[i]>((val>>8) & 7)) { - val &= ~(7<<8); - val |= (p_lowest[i])<<8; - pci_write_config32(f3_dev[i], 0xdc, val); - } - else { - p_lowest[i] = (val>>8) & 7; - } - } - if(htc_cap) { - for(i=0;i<nodes; i++) { - if(p_lowest[i]==p_htc[i]){ - lowest_htc_equal = 1; - break; - } - } - } - if(lowest_htc_equal) { - for(i=0;i<nodes; i++) { - // PstateMaxVal - val = pci_read_config32(f3_dev[i], 0xdc); - val &= ~(7<<8); - val |= p_htc[i]; - pci_write_config32(f3_dev[i], 0xdc, val); - for(j=p_htc[i]+1; j<5; j++) { - sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); - } - } - } else { - match_pstate(nodes, p_lowest); - for(i=0; i<nodes; i++) { - for(j=p_lowest[i]+1; j<5; j++) { - sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); - } - } - - } - - dump_p("Px\n", nodes, p_lowest); - dump_msr_pstates(nodes); - - - if(htc_cap) { - //p_up_int - match_pstates(nodes, p, p_htc); - - dump_msr_pstates(nodes); - - //p_lower_int - match_pstates(nodes, p_htc, p_lowest); - } else { - match_pstates(nodes, p, p_lowest); - } - - dump_msr_pstates(nodes); - - } - - // fill data into p_state - for(i=0; i<nodes; i++) { - sysconf.p_state_num = 0; - u32 corefid_equal = 1; - u32 corefid; - corefid = (sysconf.msr_pstate[i*5+0].lo & 0x3f); - for(j=1; j<5; j++) { - msr_t *msr_pstate; - msr_pstate = &(sysconf.msr_pstate[i*5+j]); - if(!(msr_pstate->hi & (1<<(63-32)) )) continue; - if((msr_pstate->lo & 0x3f) != corefid) { - corefid_equal = 0; - break; - } - } - for(j=0; j<5; j++) { - struct p_state_t *p_state; - msr_t *msr_pstate; - msr_pstate = &sysconf.msr_pstate[i*5+j]; - if(!(msr_pstate->hi & (1<<(63-32)) )) continue; - p_state = &sysconf.p_state[i*5+sysconf.p_state_num]; - u32 coredid = ((msr_pstate->lo>>6) & 7); - u32 corecof = ((msr_pstate->lo & 0x3f) + 0x10)>>coredid; - p_state->corefreq = corecof; - - u32 pwrval, pwrvalue; - pwrval = msr_pstate->hi & 0x3ff; - pwrvalue = get_pwrvalue(pwrval); - p_state->power = pwrvalue; - - u32 lat; - val = pci_read_config32(f3_dev[i], 0xd4); - lat = 15 * (get_powerstep((val>>24)& 0xf)+get_powerstep((val>>20)& 0xf)) /1000; - if(!corefid_equal) { - val = pci_read_config32(f3_dev[i], 0xa0); - lat += get_plllocktime((val >> 11 ) & 7); - } - p_state->transition_lat = lat; - p_state->busmaster_lat = lat; - - p_state->control = j; - p_state->status = j; - - sysconf.p_state_num++; - } - // don't need look at other nodes - if(!sysconf.p_state_num) break; - } -} - - -//it will update pstates info from ram into MSR -void init_pstates(device_t dev, u32 nodeid, u32 coreid) -{ - int j; - msr_t msr; - - if(sysconf.needs_update_pstate_msrs) { - for(j=0; j < 5; j++) { - wrmsr(0xC0010064 + j, sysconf.msr_pstate[nodeid * 5 + j]); - } - } - - /* Set TSC Freq Select: TSC increments at the rate of the core P-state 0 */ - msr = rdmsr(0xC0010015); - msr.lo |= 1 << 24; - wrmsr(0xC0010015, msr); - - // Enter the state P0 - //FIXME I don't think that this works correctly. May depend on early fid/vid setup. - if(sysconf.p_state_num) - set_core_nb_max_pstate_after_other_warm_reset(nodeid, coreid); - -}

1 0

patch: dbe62 boots to FILO!
by ron minnich 07 Apr '08

07 Apr '08

now how do we get a disk to boot? All we have is USB :-) ron

10 14

grub2 with corebootv2
by Mikhail Savchenko 07 Apr '08

07 Apr '08

Does anybody have success experience running corebootv2 with grub2 as payload? I'm build and trying to run grun2 from repo on coreboot site which, as I see, already have phdr patch for running with corebootv2, but I doesn't have any success.

1 0

Offtopic - Request for opinions...
by Nathanael D. Noblet 07 Apr '08

07 Apr '08

Hello, Long time lurker, and old time attempter... (waay back in v1 with an sis 535 or something like that)... Anyway, I have a project that our company may be undertaking and some of it relies on instant on / small form factor computers. Think kiosk type system. We'll be running linux, custom built or one of the super small distros, built to run off a CF card or boot off the network. Here's where I've got some questions that I imagine people on this list may have some expertise. We'd hope to have something that has hardware accelerated graphics capabilities (likely using DirectFB for graphics) so something that has linux drivers would be a major plus. We'd potentially like to use more than one monitor per device. We don't need many of the common parts on a regular PC or mini-ITX type boards, but are wondering what kind of company you would approach to get something like that built. We'd like to have coreboot as the bios to help with boot times etc. If you were looking for something like that, where would you go? Most of the miniITX boards don't quite fit the need. I'm wondering what volumes you'd need for a custom board to reach that same price, considering we'd really have very little on the device, cpu, ram, cf, video and a network. Which I guess describes almost all computers... Anyway, pointers on where to purchase, or get a board developed that could do stuff like this. We've initially contemplated the Via boards, but have seen that there are more and more offerings out there. The Geode based systems could be fine if there was hardware assistance for the graphics we imagine... Anyway, any pointers on a stuff like this would be appreciated. -- Nathanael D. Noblet

3 2

Re: [coreboot] lifebook b-2175 working with coreboot?
by Countzero786＠gmx.de 06 Apr '08

06 Apr '08

Here's dmidecode and lspci -n for the sake of completeness =) lspci -n 00:00.0 0600: 8086:7194 (rev 01) 00:00.1 0401: 8086:7195 00:00.2 0703: 8086:7196 00:07.0 0680: 8086:7198 (rev 01) 00:07.1 0101: 8086:7199 00:07.2 0c03: 8086:719a 00:07.3 0680: 8086:719b 00:12.0 0200: 8086:1229 (rev 09) 00:13.0 0607: 1217:6933 (rev 02) 00:13.1 0607: 1217:6933 (rev 02) 00:14.0 0300: 1002:4c52 (rev 64) # dmidecode 2.9 SMBIOS 2.3 present. 41 structures occupying 1106 bytes. Table at 0x07FF0000. Handle 0x0000, DMI type 0, 20 bytes BIOS Information Vendor: Phoenix/FUJITSU Version: Version 1.06 Release Date: 11/13/2000 Address: 0xE4000 Runtime Size: 112 kB ROM Size: 512 kB Characteristics: PCI is supported PC Card (PCMCIA) is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed Selectable boot is supported EDD is supported 3.5"/720 KB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported BIOS boot specification is supported Function key-initiated network boot is supported Handle 0x0001, DMI type 1, 25 bytes System Information Manufacturer: FUJITSU SIEMENS Product Name: LIFEBOOK B Series Version: Serial Number: YBTT002429 UUID: A3D31AFD-CC5F-11D4-8B14-00000E210935 Wake-up Type: Power Switch Handle 0x0002, DMI type 2, 8 bytes Base Board Information Manufacturer: FUJITSU Product Name: QUILT Version: Serial Number: Handle 0x0003, DMI type 3, 13 bytes Chassis Information Manufacturer: FUJITSU SIEMENS Type: Notebook Lock: Not Present Version: Serial Number: YBTT002429 Asset Tag: <BAD INDEX> Boot-up State: Unknown Power Supply State: Unknown Thermal State: Unknown Security Status: Unknown Handle 0x0004, DMI type 4, 32 bytes Processor Information Socket Designation: Onboard Type: Central Processor Family: Celeron Manufacturer: Intel Corporation ID: 86 06 00 00 FF F9 83 03 Signature: Type 0, Family 6, Model 8, Stepping 6 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) SSE (Streaming SIMD extensions) Version: Intel(R) Celeron(TM) processor Voltage: 1.3 V External Clock: 100 MHz Max Speed: 500 MHz Current Speed: 500 MHz Status: Unpopulated Upgrade: None L1 Cache Handle: 0x0007 L2 Cache Handle: 0x0008 L3 Cache Handle: Not Provided Handle 0x0005, DMI type 5, 18 bytes Memory Controller Information Error Detecting Method: None Error Correcting Capabilities: None Supported Interleave: One-way Interleave Current Interleave: One-way Interleave Maximum Memory Module Size: 256 MB Maximum Total Memory Size: 256 MB Supported Speeds: Other Supported Memory Types: DIMM SDRAM Memory Module Voltage: 3.3 V Associated Memory Slots: 1 0x0006 Enabled Error Correcting Capabilities: None Handle 0x0006, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM1 Bank Connections: 0 1 Current Speed: Unknown Type: DIMM SDRAM Installed Size: 128 MB (Double-bank Connection) Enabled Size: 128 MB (Double-bank Connection) Error Status: OK Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: None System Type: Other Associativity: 4-way Set-associative Handle 0x0008, DMI type 7, 19 bytes Cache Information Socket Designation: L2 Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 128 KB Maximum Size: 128 KB Supported SRAM Types: Pipeline Burst Synchronous Installed SRAM Type: Pipeline Burst Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0009, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Parallel External Connector Type: DB-25 female Port Type: Parallel Port PS/2 Handle 0x000A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Serial External Connector Type: DB-9 male Port Type: Serial Port 16550A Compatible Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Infrared External Connector Type: Infrared Port Type: Serial Port 16550A Compatible Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Mouse External Connector Type: PS/2 Port Type: Mouse Port Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: USB-1 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: USB-2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Modem External Connector Type: RJ-11 Port Type: Modem Port Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: LAN External Connector Type: RJ-45 Port Type: Network Port Handle 0x0011, DMI type 126, 9 bytes Inactive Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: CardBus-1 External Connector Type: 68 Pin Dual Inline Port Type: Cardbus Handle 0x0013, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: CardBus-2 External Connector Type: 68 Pin Dual Inline Port Type: Cardbus Handle 0x0014, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Mic In External Connector Type: Mini Jack (headphones) Port Type: Audio Port Handle 0x0015, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Headphone External Connector Type: Mini Jack (headphones) Port Type: Audio Port Handle 0x0016, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Monitor External Connector Type: DB-15 female Port Type: Video Port Handle 0x0017, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Floppy Disk External Connector Type: Other Port Type: Other Handle 0x0018, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: Connector Box External Connector Type: Other Port Type: Other Handle 0x0019, DMI type 9, 13 bytes System Slot Information Designation: CardBus-1 Type: 32-bit PC Card (PCMCIA) Current Usage: Unknown Length: Other ID: Adapter 0, Socket 0 Characteristics: 5.0 V is provided 3.3 V is provided PC Card-16 is supported Cardbus is supported Modem ring resume is supported PME signal is supported Handle 0x001A, DMI type 9, 13 bytes System Slot Information Designation: CardBus-2 Type: 32-bit PC Card (PCMCIA) Current Usage: Unknown Length: Other ID: Adapter 1, Socket 0 Characteristics: 5.0 V is provided 3.3 V is provided PC Card-16 is supported Cardbus is supported Modem ring resume is supported PME signal is supported Handle 0x001B, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 2 enUS jaJP Currently Installed Language: enUS Handle 0x001C, DMI type 15, 35 bytes System Event Log Area Length: 48 bytes Header Start Offset: 0x0000 Header Length: 16 bytes Data Start Offset: 0x0010 Access Method: Memory-mapped physical 32-bit address Access Address: 0xFFF80000 Status: Valid, Not Full Change Token: 0x00000059 Header Format: Type 1 Supported Log Type Descriptors: 6 Descriptor 1: POST memory resize Data Format 1: None Descriptor 2: POST error Data Format 2: POST results bitmap Descriptor 3: System reconfigured Data Format 3: None Descriptor 4: Log area reset/cleared Data Format 4: None Descriptor 5: System boot Data Format 5: None Descriptor 6: OEM-specific Data Format 6: None Handle 0x001D, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 256 MB Error Information Handle: Not Provided Number Of Devices: 1 Handle 0x001E, DMI type 17, 23 bytes Memory Device Array Handle: 0x001D Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 128 MB Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: Bank 0/1 Type: SDRAM Type Detail: Synchronous Speed: 100 MHz (10.0 ns) Handle 0x001F, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x00007FFFFFF Range Size: 128 MB Physical Array Handle: 0x001D Partition Width: 0 Handle 0x0020, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x00007FFFFFF Range Size: 128 MB Physical Device Handle: 0x001E Memory Array Mapped Address Handle: 0x001F Partition Row Position: 1 Handle 0x0021, DMI type 21, 7 bytes Built-in Pointing Device Type: Other Interface: PS/2 Buttons: 2 Handle 0x0022, DMI type 126, 26 bytes Inactive Handle 0x0023, DMI type 126, 26 bytes Inactive Handle 0x0024, DMI type 24, 5 bytes Hardware Security Power-On Password Status: Disabled Keyboard Password Status: Disabled Administrator Password Status: Enabled Front Panel Reset Status: Not Implemented Handle 0x0025, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0x0026, DMI type 143, 16 bytes OEM-specific Type Header and Data: 8F 10 26 00 00 5F 46 4A 5F 4F 45 4D 5F 10 00 00 Strings: ..' .. Handle 0x0027, DMI type 143, 8 bytes OEM-specific Type Header and Data: 8F 08 27 00 01 03 00 00 Strings: ..( Handle 0x0028, DMI type 127, 4 bytes End Of Table -- Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! Ideal für Modem und ISDN: http://www.gmx.net/de/go/smartsurfer

1 0

v2[PATCH]ICH series halt tco timer
by joe＠smittys.pointclark.net 06 Apr '08

06 Apr '08

This patch halts the tco timer early in the boot process on all ICH series southbridges. It also keeps the boot processes from rebooting through out the coreboot process. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Thanks - Joe

2 6

r3218 - in trunk/coreboot-v2/src: mainboard/rca/rm4100 southbridge/intel/i82801xx
by svn＠coreboot.org 06 Apr '08

06 Apr '08

Author: linux_junkie Date: 2008-04-06 06:26:19 +0200 (Sun, 06 Apr 2008) New Revision: 3218 Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c Log: This patch halts the tco timer early in the boot process on all ICH series southbridges. It also keeps the boot processes from rebooting through out the coreboot process. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c 2008-04-05 01:07:27 UTC (rev 3217) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c 2008-04-06 04:26:19 UTC (rev 3218) @@ -42,6 +42,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c" /** * The onboard 128MB PC133 memory does not have a SPD EEPROM so the @@ -69,24 +70,6 @@ #include "sdram/generic_sdram.c" /** - * We have to disable the TCO Timer system reboot feature - * or we get several reboots through out the boot processes. - */ -static void disable_tco_timer(void) -{ - device_t dev; - u8 reg8; - - /* Set the LPC device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Disable the TCO Timer system reboot feature. */ - reg8 = pci_read_config8(dev, 0xd4); - reg8 |= (1 << 1); - pci_write_config8(dev, 0xd4, reg8); -} - -/** * The AC'97 Audio Controller I/O space registers are read only by default * so we need to enable them by setting register 0x41 to 0x01. */ @@ -131,6 +114,6 @@ /* ram_check(0, 640 * 1024); */ /* ram_check(130048 * 1024, 131072 * 1024); */ - disable_tco_timer(); + i82801xx_halt_tco_timer(); ac97_io_enable(); } Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h 2008-04-05 01:07:27 UTC (rev 3217) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h 2008-04-06 04:26:19 UTC (rev 3218) @@ -34,6 +34,7 @@ #define GEN_PMCON_3 0xa4 #define PMBASE 0x40 +#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */ #define ACPI_CNTL 0x44 #define BIOS_CNTL 0x4E #define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ @@ -68,6 +69,9 @@ #define MTT 0x70 #define PCI_MAST_STS 0x82 +#define TCOBASE 0x60 /* TCO Base Address Register */ +#define TCO1_CNT 0x08 /* TCO1 Control Register */ + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c 2008-04-06 04:26:19 UTC (rev 3218) @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +static void i82801xx_halt_tco_timer(void) +{ + device_t dev; + uint16_t halt_tco_timer; + + /* Set the LPC device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Temporarily set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + + /* Temporarily enable ACPI I/O. */ + pci_write_config8(dev, ACPI_CNTL, 0x10); + + /* Halt the TCO timer, preventing SMI and automatic reboot */ + outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT); + + /* Disable ACPI I/O. */ + pci_write_config8(dev, ACPI_CNTL, 0x00); +} Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2008-04-05 01:07:27 UTC (rev 3217) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2008-04-06 04:26:19 UTC (rev 3218) @@ -32,7 +32,6 @@ #include <arch/io.h> #include "i82801xx.h" -#define PMBASE_ADDR 0x00000400 /* ACPI Base Address Register */ #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ #define NMI_OFF 0

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coreboot April 2008