coreboot April 2008

coreboot@coreboot.org

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r3222 - in trunk/payloads/libpayload: . include libc
by svn＠coreboot.org 07 Apr '08

07 Apr '08

Author: uwe Date: 2008-04-08 01:33:50 +0200 (Tue, 08 Apr 2008) New Revision: 3222 Added: trunk/payloads/libpayload/libc/rand.c Modified: trunk/payloads/libpayload/LICENSES trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/libc/Makefile.inc Log: Add rand/rand_r/srand functions for generating pseudo-random bytes. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/LICENSES =================================================================== --- trunk/payloads/libpayload/LICENSES 2008-04-07 22:33:33 UTC (rev 3221) +++ trunk/payloads/libpayload/LICENSES 2008-04-07 23:33:50 UTC (rev 3222) @@ -66,6 +66,12 @@ Original files: lib/libalias/alias_util.c, function LibAliasInternetChecksum() Current version we use: CVS revision 1.15 2004/07/06 12:13:28 +* libc/rand.c: 3-clause BSD license + Source: OpenBSD + http://www.openbsd.org/cgi-bin/cvsweb/src/lib/libc/stdlib/rand.c + Original files: src/lib/libc/stdlib/rand.c + Current version we use: CVS revision 1.9 2005/8/8 08:05:37 + * libc/memory.c: 3-clause BSD license Source: HelenOS, http://www.helenos.eu svn checkout svn://svn.helenos.eu/HelenOS/trunk HelenOS Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-04-07 22:33:33 UTC (rev 3221) +++ trunk/payloads/libpayload/include/libpayload.h 2008-04-07 23:33:50 UTC (rev 3222) @@ -53,6 +53,8 @@ #define BYTE_ORDER BIG_ENDIAN #endif +#define RAND_MAX 0x7fffffff + /* Some NVRAM byte definitions */ #define NVRAM_RTC_SECONDS 0 #define NVRAM_RTC_MINUTES 2 Modified: trunk/payloads/libpayload/libc/Makefile.inc =================================================================== --- trunk/payloads/libpayload/libc/Makefile.inc 2008-04-07 22:33:33 UTC (rev 3221) +++ trunk/payloads/libpayload/libc/Makefile.inc 2008-04-07 23:33:50 UTC (rev 3222) @@ -29,3 +29,4 @@ TARGETS-y += libc/malloc.o libc/printf.o libc/console.o libc/string.o TARGETS-y += libc/memory.o libc/ctype.o libc/ipchecksum.o libc/lib.o +TARGETS-y += libc/rand.o Added: trunk/payloads/libpayload/libc/rand.c =================================================================== --- trunk/payloads/libpayload/libc/rand.c (rev 0) +++ trunk/payloads/libpayload/libc/rand.c 2008-04-07 23:33:50 UTC (rev 3222) @@ -0,0 +1,52 @@ +/* + * This file is part of the libpayload project. + * + * It was originally taken from the OpenBSD project. + * + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +static unsigned int next = 1; + +int rand_r(unsigned int *seed) +{ + *seed = *seed * 1103515245 + 12345; + return (*seed % ((unsigned int)RAND_MAX + 1)); +} + +int rand(void) +{ + return (rand_r(&next)); +} + +void srand(unsigned int seed) +{ + next = seed; +}

1 0

libpayload: gcc wrappers
by Jordan Crouse 07 Apr '08

07 Apr '08

Continuing the parade of Denver patches, here is an implementation for gcc wrappers for libpayload. Jordan Crouse -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

2 2

r3221 - trunk/util/flashrom
by svn＠coreboot.org 07 Apr '08

07 Apr '08

Author: eswierk Date: 2008-04-08 00:33:33 +0200 (Tue, 08 Apr 2008) New Revision: 3221 Modified: trunk/util/flashrom/flashchips.c Log: ST M50FW016 and ST M50FW040 support the 82802ab command set, not jedec. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Joseph Smith <joe(a)smittys.pointclark.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-04-07 18:11:03 UTC (rev 3220) +++ trunk/util/flashrom/flashchips.c 2008-04-07 22:33:33 UTC (rev 3221) @@ -106,8 +106,8 @@ {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, - {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, - {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, + {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002},

1 0

Re: [coreboot] r3213 - trunk/payloads/libpayload/include
by Segher Boessenkool 07 Apr '08

07 Apr '08

> +#define BIN2HEX(b) ("0123456789abcdef"[b & 15]) > +#define HEX2BIN(h) (('0' <= h && h <= '9') ? (h - '0') : \ > + ('a' <= h && h <= 'f') ? (h - 'a' + 10) : 0) These macros are unsafe: lack of parentheses around the uses of the parameters, and multiple evaluation in the second macro. Please consider using an inline function instead (or a "real" function, to make code size smaller). Btw, could the SVN checkin list be set up with a followup-to: header? Segher

3 6

lifebook b-2175 working with coreboot?
by Countzero786＠gmx.de 07 Apr '08

07 Apr '08

Greetings, I'd like to know if there's a chance I can get coreboot to run on an old Fujitsu-Siemens Lifebook B-2175 I own. As it uses the Intel 440mx chipset, here are links to the (complete I think?) official documentation: http://www.intel.com/design/chipsets/designex/273504.htm http://www.intel.com/design/chipsets/specupdt/245051.htm http://www.intel.com/design/chipsets/datashts/440MX-66DSPub.htm http://www.intel.com/design/chipsets/embedded/docs/440mx.htm And the data I got from probing with the tools I found on your site, lspci and dmesg. Thanks for your time in advance. Said. ./flashrom -------------------- Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel 440MX", enabling flash write... OK. MBM29F400TC found at physical address 0xfff80000. Flash part is MBM29F400TC (512 KB). No operations were specified. ./superiotool -d -------------------- superiotool r3194 Found SMSC FDC37N769 (id=0x28, rev=0x01) at 0x3f0 Register dump: idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 20 90 00 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 00 03 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00 lspci -v -v -v -------------------- 00:00.0 Host bridge: Intel Corporation 82440MX Host Bridge (rev 01) Subsystem: Fujitsu Limited. Unknown device 107f Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 64 00:00.1 Multimedia audio controller: Intel Corporation 82440MX AC'97 Audio Controller Subsystem: Fujitsu Limited. QSound_SigmaTel Stac97 PCI Audio Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 9 Region 0: I/O ports at 1000 [size=256] Region 1: I/O ports at 1400 [size=64] 00:00.2 Modem: Intel Corporation 82440MX AC'97 Modem Controller (prog-if 00 [Generic]) Subsystem: Fujitsu Limited. Unknown device 10d1 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 9 Region 0: I/O ports at 2000 [size=256] Region 1: I/O ports at 1800 [size=128] 00:07.0 Bridge: Intel Corporation 82440MX ISA Bridge (rev 01) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00:07.1 IDE interface: Intel Corporation 82440MX EIDE Controller (prog-if 80 [Master]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at 1480 [size=16] 00:07.2 USB Controller: Intel Corporation 82440MX USB Universal Host Controller (prog-if 00 [UHCI]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin D routed to IRQ 15 Region 4: I/O ports at 14a0 [size=32] 00:07.3 Bridge: Intel Corporation 82440MX Power Management Controller Control: I/O+ Mem+ BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:12.0 Ethernet controller: Intel Corporation 82557/8/9 Ethernet Pro 100 (rev 09) Subsystem: Fujitsu Limited. Unknown device 1070 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 66 (2000ns min, 14000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at fc020000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at 1440 [size=64] Region 2: Memory at fc000000 (32-bit, non-prefetchable) [size=128K] Capabilities: <access denied> 00:13.0 CardBus bridge: O2 Micro, Inc. OZ6933/711E1 CardBus/SmartCardBus Controller (rev 02) Subsystem: Fujitsu Limited. Unknown device 10e6 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 168 Interrupt: pin A routed to IRQ 9 Region 0: Memory at 20020000 (32-bit, non-prefetchable) [size=4K] Bus: primary=00, secondary=01, subordinate=04, sec-latency=176 Memory window 0: 10000000-13fff000 (prefetchable) Memory window 1: 14000000-17fff000 I/O window 0: 00001c00-00001cff I/O window 1: 00002800-000028ff BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt+ PostWrite+ 16-bit legacy interface ports at 0001 00:13.1 CardBus bridge: O2 Micro, Inc. OZ6933/711E1 CardBus/SmartCardBus Controller (rev 02) Subsystem: Fujitsu Limited. Unknown device 10e6 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 168 Interrupt: pin B routed to IRQ 9 Region 0: Memory at 20021000 (32-bit, non-prefetchable) [size=4K] Bus: primary=00, secondary=05, subordinate=08, sec-latency=176 Memory window 0: 18000000-1bfff000 (prefetchable) Memory window 1: 1c000000-1ffff000 I/O window 0: 00002c00-00002cff I/O window 1: 00003000-000030ff BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt+ PostWrite+ 16-bit legacy interface ports at 0001 00:14.0 VGA compatible controller: ATI Technologies Inc Rage Mobility P/M (rev 64) (prog-if 00 [VGA controller]) Subsystem: Fujitsu Limited. Unknown device 1103 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 66 (2000ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at fd000000 (32-bit, non-prefetchable) [size=16M] Region 1: I/O ports at 2400 [size=256] Region 2: Memory at fc021000 (32-bit, non-prefetchable) [size=4K] [virtual] Expansion ROM at 20000000 [disabled] [size=128K] Capabilities: <access denied> dmesg -------------------- Linux version 2.6.24-WDC (root(a)wdc.inc) (gcc version 4.3.0 (GCC) ) #1 Fri Apr 4 09:50:06 CEST 2008 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 000000000009fc00 (usable) BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved) BIOS-e820: 00000000000e7800 - 0000000000100000 (reserved) BIOS-e820: 0000000000100000 - 0000000007fe0000 (usable) BIOS-e820: 0000000007fe0000 - 0000000007fefc00 (ACPI data) BIOS-e820: 0000000007fefc00 - 0000000007ff0000 (ACPI NVS) BIOS-e820: 0000000007ff0000 - 0000000007ff2000 (reserved) BIOS-e820: 0000000007ff2000 - 0000000008000000 (usable) BIOS-e820: 00000000fff00000 - 0000000100000000 (reserved) 128MB LOWMEM available. Entering add_active_range(0, 0, 32768) 0 entries of 256 used Zone PFN ranges: DMA 0 -> 4096 Normal 4096 -> 32768 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0 -> 32768 On node 0 totalpages: 32768 DMA zone: 32 pages used for memmap DMA zone: 0 pages reserved DMA zone: 4064 pages, LIFO batch:0 Normal zone: 224 pages used for memmap Normal zone: 28448 pages, LIFO batch:7 Movable zone: 0 pages used for memmap DMI 2.3 present. ACPI: RSDP 000F64D0, 0014 (r0 FUJ ) ACPI: RSDT 07FEC74F, 0028 (r1 FUJ QUILT 1060000 FUJ 1000) ACPI: FACP 07FEFB8C, 0074 (r1 FUJ QUILT 1060000 FUJ 1000) ACPI: DSDT 07FEC777, 3415 (r1 FUJ QUILT 1060000 MSFT 1000007) ACPI: FACS 07FEFFC0, 0040 ACPI: DMI detected: Fujitsu Siemens ACPI: PM-Timer IO Port: 0xff08 Allocating PCI resources starting at 10000000 (gap: 08000000:f7f00000) swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000 swsusp: Registered nosave memory region: 00000000000a0000 - 00000000000e8000 swsusp: Registered nosave memory region: 00000000000e8000 - 0000000000100000 swsusp: Registered nosave memory region: 0000000007fe0000 - 0000000007fef000 swsusp: Registered nosave memory region: 0000000007fef000 - 0000000007ff0000 swsusp: Registered nosave memory region: 0000000007ff0000 - 0000000007ff2000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 Kernel command line: root=/dev/hda3 ro vga=6 Local APIC disabled by BIOS -- you can enable it with "lapic" mapped APIC to ffffb000 (01102000) Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 PID hash table entries: 512 (order: 9, 2048 bytes) Detected 497.575 MHz processor. Console: colour VGA+ 80x60 console [tty0] enabled Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 125144k/131072k available (2200k kernel code, 5316k reserved, 720k data, 284k init, 0k highmem) virtual kernel memory layout: fixmap : 0xfffb5000 - 0xfffff000 ( 296 kB) vmalloc : 0xc8800000 - 0xfffb3000 ( 887 MB) lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) .init : 0xc03de000 - 0xc0425000 ( 284 kB) .data : 0xc03260b7 - 0xc03da39c ( 720 kB) .text : 0xc0100000 - 0xc03260b7 (2200 kB) Checking if this processor honours the WP bit even in supervisor mode... Ok. Calibrating delay using timer specific routine.. 995.54 BogoMIPS (lpj=497774) Mount-cache hash table entries: 512 CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000 00000000 00000000 00000000 00000000 CPU: L1 I cache: 16K, L1 D cache: 16K CPU: L2 cache: 128K CPU: After all inits, caps: 0383f9ff 00000000 00000000 00000040 00000000 00000000 00000000 00000000 Intel machine check architecture supported. Intel machine check reporting enabled on CPU#0. Compat vDSO mapped to ffffe000. CPU: Intel Celeron (Coppermine) stepping 06 Checking 'hlt' instruction... OK. Freeing SMP alternatives: 0k freed Early unpacking initramfs... done ACPI: Core revision 20070126 ACPI: Looking for DSDT in initramfs... error, file /DSDT.aml not found. ACPI: setting ELCR to 0200 (from 8200) net_namespace: 64 bytes NET: Registered protocol family 16 EISA bus registered ACPI: bus type pci registered PCI: PCI BIOS revision 2.10 entry at 0xfd9ce, last bus=2 PCI: Using configuration type 1 Setting up standard PCI resources ACPI: EC: Look up EC in DSDT ACPI: Interpreter enabled ACPI: (supports S0 S3 S4 S5) ACPI: Using PIC for interrupt routing ACPI: EC: GPE = 0x2c, I/O: command/status = 0x66, data = 0x62 ACPI: EC: driver started in poll mode ACPI: PCI Root Bridge [PCI0] (0000:00) PCI quirk: region ff00-ff3f claimed by PIIX4 ACPI PCI quirk: region ff80-ff8f claimed by PIIX4 SMB PIIX4 devres C PIO at fd60-fd67 ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 7 *9 10 11) ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 7 *9 10 11) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 7 *9 10 11) ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 7 10 11 *15) ACPI: Power Resource [USBP] (on) Linux Plug and Play Support v0.97 (c) Adam Belay pnp: PnP ACPI init ACPI: bus type pnp registered pnp: PnP ACPI: found 8 devices ACPI: ACPI bus type pnp unregistered SCSI subsystem initialized PCI: Using ACPI for IRQ routing PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report Time: tsc clocksource has been installed. system 00:01: ioport range 0x4d0-0x4d1 has been reserved system 00:01: ioport range 0xff00-0xff3f has been reserved system 00:01: ioport range 0xf800-0xf87f has been reserved system 00:01: ioport range 0xfd60-0xfd67 has been reserved system 00:01: ioport range 0xfe00-0xfe00 has been reserved system 00:01: ioport range 0xff80-0xff8f has been reserved PCI: Bus 1, cardbus bridge: 0000:00:13.0 IO window: 00001c00-00001cff IO window: 00002800-000028ff PREFETCH window: 10000000-13ffffff MEM window: 14000000-17ffffff PCI: Bus 5, cardbus bridge: 0000:00:13.1 IO window: 00002c00-00002cff IO window: 00003000-000030ff PREFETCH window: 18000000-1bffffff MEM window: 1c000000-1fffffff ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 9 PCI: setting IRQ 9 as level-triggered ACPI: PCI Interrupt 0000:00:13.0[A] -> Link [LNKA] -> GSI 9 (level, low) -> IRQ 9 PCI: Setting latency timer of device 0000:00:13.0 to 64 ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 9 ACPI: PCI Interrupt 0000:00:13.1[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9 PCI: Setting latency timer of device 0000:00:13.1 to 64 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table entries: 4096 (order: 2, 16384 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered Unpacking initramfs... done Freeing initrd memory: 749k freed IA-32 Microcode Update Driver: v1.14a <tigran(a)aivazian.fsnet.co.uk> apm: BIOS version 1.2 Flags 0x03 (Driver version 1.16ac) apm: overridden by ACPI. Installing knfsd (copyright (C) 1996 okir(a)monad.swb.de). io scheduler noop registered io scheduler anticipatory registered (default) PCI: Firmware left 0000:00:12.0 e100 interrupts enabled, disabling Boot video device is 0000:00:14.0 isapnp: Scanning for PnP cards... Switched to high resolution mode on CPU 0 isapnp: No Plug & Play device found Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled PCI: Enabling device 0000:00:00.2 (0000 -> 0001) ACPI: PCI Interrupt 0000:00:00.2[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9 ACPI: PCI interrupt for device 0000:00:00.2 disabled loop: module loaded PNP: PS/2 Controller [PNP0303:KBC,PNP0f13:PS2M] at 0x60,0x64 irq 1,12 serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mice: PS/2 mouse device common for all mice EISA: Probing bus 0 at eisa.0 cpuidle: using governor ladder cpuidle: using governor menu TCP cubic registered NET: Registered protocol family 1 NET: Registered protocol family 17 RPC: Registered udp transport module. RPC: Registered tcp transport module. Using IPI Shortcut mode Freeing unused kernel memory: 284k freed Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX4: IDE controller (0x8086:0x7199 rev 0x00) at PCI slot 0000:00:07.1 PIIX4: not 100% native mode: will probe irqs later ide0: BM-DMA at 0x1480-0x1487, BIOS settings: hda:DMA, hdb:pio PIIX4: IDE port disabled Probing IDE interface ide0... input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0 hda: TOSHIBA MK1016GAP, ATA DISK drive hda: host max PIO4 wanted PIO255(auto-tune) selected PIO4 hda: UDMA/33 mode selected ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 hda: max request size: 128KiB hda: 19640880 sectors (10056 MB), CHS=19485/16/63 hda: cache flushes not supported hda: hda1 hda2 < hda5 > hda3 hda4 SGI XFS with ACLs, security attributes, realtime, no debug enabled SGI XFS Quota Management subsystem Filesystem "hda3": Disabling barriers, not supported by the underlying device XFS mounting filesystem hda3 Ending clean XFS mount for filesystem: hda3 usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0 rtc0: alarms up to one month, y3k floppy0: no floppy controllers found ide-floppy driver 0.99.newide ACPI: AC Adapter [AC] (on-line) ACPI: Battery Slot [CMB1] (battery absent) input: Power Button (FF) as /devices/virtual/input/input1 ACPI: Power Button (FF) [PWRF] input: Power Button (CM) as /devices/virtual/input/input2 ACPI: Power Button (CM) [PWRB] input: Lid Switch as /devices/virtual/input/input3 ACPI: Lid Switch [LID] ACPI: CPU0 (power states: C1[C1] C2[C2]) ACPI: Processor [CPU0] (supports 8 throttling states) Marking TSC unstable due to: TSC halts in idle. Time: acpi_pm clocksource has been installed. USB Universal Host Controller Interface driver v3.0 PCI: Enabling device 0000:00:07.2 (0000 -> 0001) ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 15 PCI: setting IRQ 15 as level-triggered ACPI: PCI Interrupt 0000:00:07.2[D] -> Link [LNKD] -> GSI 15 (level, low) -> IRQ 15 uhci_hcd 0000:00:07.2: UHCI Host Controller uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1 uhci_hcd 0000:00:07.2: irq 15, io base 0x000014a0 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected eepro100.c:v1.09j-t 9/29/99 Donald Becker eepro100.c: $Revision: 1.36 $ 2000/11/17 Modified by Andrey V. Savochkin <saw(a)saw.sw.com.sg> and others ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 9 ACPI: PCI Interrupt 0000:00:12.0[A] -> Link [LNKC] -> GSI 9 (level, low) -> IRQ 9 eth0: OEM i82557/i82558 10/100 Ethernet, 00:00:0e:21:09:35, IRQ 9. Board assembly 000000-000, Physical connectors present: RJ45 Primary interface chip i82555 PHY #1. General self-test: passed. Serial sub-system self-test: passed. Internal registers self-test: passed. ROM checksum self-test: passed (0xdbd8681d). input: PC Speaker as /devices/platform/pcspkr/input/input4 input: PS/2 Touchpad as /devices/platform/i8042/serio1/input/input5 piix4_smbus 0000:00:07.3: Found 0000:00:07.3 device usb 1-1: new low speed USB device using uhci_hcd and address 2 e100: Intel(R) PRO/100 Network Driver, 3.5.23-k4-NAPI e100: Copyright(c) 1999-2006 Intel Corporation Yenta: CardBus bridge found at 0000:00:13.0 [10cf:10e6] Yenta O2: res at 0x94/0xD4: ea/00 Yenta O2: enabling read prefetch/write burst usb 1-1: configuration #1 chosen from 1 choice input: LBPS/2 Fujitsu Lifebook TouchScreen as /devices/platform/i8042/serio1/input/input6 Yenta: ISA IRQ mask 0x0cb8, PCI irq 9 Socket status: 30000006 Yenta: CardBus bridge found at 0000:00:13.1 [10cf:10e6] Yenta: ISA IRQ mask 0x0cb8, PCI irq 9 Socket status: 30000006 ACPI: PCI Interrupt 0000:00:00.1[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9 PCI: Setting latency timer of device 0000:00:00.1 to 64 intel8x0_measure_ac97_clock: measured 50106 usecs intel8x0: clocking to 48000 usbcore: registered new interface driver hiddev input: Logitech USB-PS/2 Optical Mouse as /devices/pci0000:00/0000:00:07.2/usb1/1-1/1-1:1.0/input/input7 input,hidraw0: USB HID v1.10 Mouse [Logitech USB-PS/2 Optical Mouse] on usb-0000:00:07.2-1 usbcore: registered new interface driver usbhid drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver cs: IO port probe 0x100-0x3af: clean. cs: IO port probe 0x3e0-0x4ff: clean. cs: IO port probe 0x820-0x8ff: clean. cs: IO port probe 0xc00-0xcf7: clean. cs: IO port probe 0xa00-0xaff: clean. cs: IO port probe 0x100-0x3af: clean. cs: IO port probe 0x3e0-0x4ff: clean. cs: IO port probe 0x820-0x8ff: clean. cs: IO port probe 0xc00-0xcf7: clean. cs: IO port probe 0xa00-0xaff: clean. Filesystem "hda3": Disabling barriers, not supported by the underlying device Filesystem "hda3": Disabling barriers, not supported by the underlying device JFS: nTxBlock = 986, nTxLock = 7895 Filesystem "hda4": Disabling barriers, not supported by the underlying device XFS mounting filesystem hda4 Ending clean XFS mount for filesystem: hda4 Adding 248968k swap on /dev/hda5. Priority:-1 extents:1 across:248968k hda: cache flushes not supported ip_tables: (C) 2000-2006 Netfilter Core Team nf_conntrack version 0.5.0 (2048 buckets, 8192 max) spurious 8259A interrupt: IRQ7. -- GMX startet ShortView.de. Hier findest Du Leute mit Deinen Interessen! Jetzt dabei sein: http://www.shortview.de/?mc=sv_ext_mf@gmx

3 3

lzma compression
by Mikhail Savchenko 07 Apr '08

07 Apr '08

AS I Know 7zip algorithm using for this compression is paid for commercial use. Are there any special license issues about it's using during coreboot?

2 1

Flashing problem with SST49LF004B
by malatesh kamatad 07 Apr '08

07 Apr '08

Hi all.. I have worked with PM49fl00x.diff patch ,its worked fine and i got the output as below [root@localhost ~]# flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). No operations were specified. [root@localhost ~]# flashrom -r backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Reading Flash...done [root@localhost ~]# flashrom -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Erasing flash chip Erasing page: 0007 at address: 0x00070000 [root@localhost ~]# flashrom -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 [root@localhost ~]# flashrom -v backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. ************************************************************************************************************************************** Now i am working on SST49LF004B 33-4C-NHE 0710022-CA with the motherboard K8Upgrade-VM800 The flashrom detect flash device on this board, But the erasing and writting operation is not happening properly hier flashrom output : [root@localhost ~]# flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). No operations were specified. [root@localhost ~]# flashrom -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). Erasing flash chip [root@localhost ~]# flashrom -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 [root@localhost ~]# flashrom -v backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... FAILED! Now we are analysing the code but we are not getting idea... please guide us how to change the code ..we are ready to fix the things. Thanks in advance........ with regards, Malatesh kamatad..

4 16

r3220 build service
by coreboot information 07 Apr '08

07 Apr '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3220 to the coreboot source repository and caused the following changes: Change Log: Re-add files I deleted by mistake in r3219. They are meant for a different patch. Signed-off-by: Marc Jones (marc.jones(a)amd.com) Acked-by: Marc Jones (marc.jones(a)amd.com) Build Log: Compilation of amd:serengeti_cheetah_fam10 has been fixed If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Re: [coreboot] r3220 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
by Carl-Daniel Hailfinger 07 Apr '08

07 Apr '08

On 07.04.2008 20:11, svn(a)coreboot.org wrote: > Author: mjones > Date: 2008-04-07 20:11:03 +0200 (Mon, 07 Apr 2008) > New Revision: 3220 > > Added: > trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c > trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h > trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h > trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h > trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c > Log: > Re-add files I deleted by mistake in r3219. They are meant for a different > patch. > > Signed-off-by: Marc Jones (marc.jones(a)amd.com) > Acked-by: Marc Jones (marc.jones(a)amd.com) > By the way, it is possible to undelete files and keep svn history intact. The process is a bit awkward, but doable. Use svn cp to make a copy of the file in a revision where it still exists. Regards, Carl-Daniel

1 0

r3219 build service
by coreboot information 07 Apr '08

07 Apr '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3219 to the coreboot source repository and caused the following changes: Change Log: Don't check exclusive IRQ fieldin the PIR table. This field is rarely used (and not used in the LX tables). There is not a good reason to mask off non-exclusive IRQs. Signed-off-by: Marc Jones(marc.jones(a)amd.com) Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3219&device=serengeti_chee… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

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