coreboot April 2008

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Trac reminder: list of new ticket(s)
by coreboot tracker 16 Apr '08

16 Apr '08

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Re: [coreboot] Trac reminder: list of new ticket(s)
by a a 16 Apr '08

16 Apr '08

the links dont work ? http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/28 get me Environment not found LinuxBIOS tracker wrote: > Ticket Owner Status Description > #95 > somebody new Run coreboot in VirtualBox > #94 jcrouse > new Need getch_timeout() function in libpayload > #93 > somebody new Add a gcc wrapper script > #88 new Add > UHCI/OHCI/EHCI support to GRUB2 > #85 > somebody new fix milli/mega and 1000/1024 ambiguities > #82 oxygene > new Fix the memory map in LinuxBIOSv3 > #77 > somebody new hang on the "Jumping to LinuxBIOS" step on via epia-m > with 4-chip 128Mbyte ddr module > #76 > rminnich new coreboot messages should be accessible in dmesg > #73 > somebody new Merge NVIDIA MCP55 and CK804 code? > #66 > somebody new Merge all debug.c instances > #65 > somebody new Unify SuperIO code? > #64 > somebody new Epia-M COM2 does not work > #49 > somebody new TPM support for LinuxBIOS > #46 > somebody new Clarify LinuxBIOS vs. OpenBIOS vs. Open Firmware vs. EFI > vs. GNUFI etc. > #45 > somebody new Enforce consistent coding style > #43 > somebody new Add graphics memory hole to e820 map > #35 new Make > it possible to boot Windows using LinuxBIOS > #28 > somebody new Finish Intel 440BX port > #25 > somebody new Clean up x86 emulator in the tree? > #24 > somebody new Remove all files which have a GPL-incompatible license > #23 > somebody new Use Doxygen-style comments > #18 > somebody new autoprobe apic cluster and application processors on K8 > systems > #17 stepan > new clean up linuxbios table handling > #16 ollie > new I2C driver and mainboard Config.lb > #14 > somebody new Rename "stream" to "payload" > #12 > somebody new Make LinuxBIOS work on a laptop > #11 yhlu new > pirq table automation > #8 uwe new > Fully support all components of the ITE Super I/Os > #7 uwe new > Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards > #5 somebody > new Add license header to all source files > #2 somebody > new Complete tables of supported motherboards > _________________________________________________________________ Express yourself instantly with MSN Messenger! Download today it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/

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supermicro x7dwt-inf (esb2) lspci -v
by rob larkin 16 Apr '08

16 Apr '08

[root@mcneil1 ~]# lspci -v 00:00.0 Host bridge: Intel Corporation Memory Controller Hub (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, fast devsel, latency 0, IRQ 11 Capabilities: [50] Power Management version 3 Capabilities: [58] Message Signalled Interrupts: 64bit- Queue=0/1 Enable- Capabilities: [6c] Express Root Port (Slot-) IRQ 0 Capabilities: [100] Advanced Error Reporting 00:01.0 PCI bridge: Intel Corporation PCI Express Port 1 (rev 20) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Capabilities: [50] Power Management version 3 Capabilities: [58] Message Signalled Interrupts: 64bit- Queue=0/1 Enable+ Capabilities: [6c] Express Root Port (Slot+) IRQ 0 Capabilities: [b0] #0d [0000] Capabilities: [100] Advanced Error Reporting 00:05.0 PCI bridge: Intel Corporation PCI Express Port 5 (rev 20) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=06, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: d8000000-d81fffff Prefetchable memory behind bridge: 00000000d8300000-00000000d8300000 Capabilities: [50] Power Management version 3 Capabilities: [58] Message Signalled Interrupts: 64bit- Queue=0/1 Enable+ Capabilities: [6c] Express Root Port (Slot-) IRQ 0 Capabilities: [b0] #0d [0000] Capabilities: [100] Advanced Error Reporting 00:07.0 PCI bridge: Intel Corporation PCI Express Port 7 (rev 20) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 Capabilities: [50] Power Management version 3 Capabilities: [58] Message Signalled Interrupts: 64bit- Queue=0/1 Enable+ Capabilities: [6c] Express Root Port (Slot+) IRQ 0 Capabilities: [b0] #0d [0000] Capabilities: [100] Advanced Error Reporting 00:0f.0 System peripheral: Intel Corporation DMA/DCA Engine (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, fast devsel, latency 0, IRQ 11 Memory at fe700000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Capabilities: [58] MSI-X: Enable- Mask- TabSize=4 Capabilities: [6c] Express Unknown type IRQ 0 00:10.0 Host bridge: Intel Corporation FSB Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:10.1 Host bridge: Intel Corporation FSB Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:10.2 Host bridge: Intel Corporation FSB Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:10.3 Host bridge: Intel Corporation FSB Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:10.4 Host bridge: Intel Corporation FSB Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:11.0 Host bridge: Intel Corporation Unknown device 4031 (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:15.0 Host bridge: Intel Corporation FBD Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:15.1 Host bridge: Intel Corporation FBD Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:16.0 Host bridge: Intel Corporation FBD Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:16.1 Host bridge: Intel Corporation FBD Registers (rev 20) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: fast devsel 00:1d.0 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #1 (rev 09) (prog-if 00 [UHCI]) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, medium devsel, latency 0, IRQ 58 I/O ports at 1800 [size=32] 00:1d.1 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #2 (rev 09) (prog-if 00 [UHCI]) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, medium devsel, latency 0, IRQ 66 I/O ports at 1820 [size=32] 00:1d.2 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #3 (rev 09) (prog-if 00 [UHCI]) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, medium devsel, latency 0, IRQ 74 I/O ports at 1840 [size=32] 00:1d.7 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 Controller (rev 09) (prog-if 20 [EHCI]) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, medium devsel, latency 0, IRQ 82 Memory at d8504000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev d9) (prog-if 01 [Subtractive decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 00003000-00003fff Memory behind bridge: d8200000-d82fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d7f00000 Capabilities: [50] #0d [0000] 00:1f.0 ISA bridge: Intel Corporation 631xESB/632xESB/3100 Chipset LPC Interface Controller (rev 09) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, medium devsel, latency 0 00:1f.2 SATA controller: Intel Corporation 631xESB/632xESB SATA AHCI Controller (rev 09) (prog-if 01 [AHCI 1.0]) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 90 I/O ports at 1890 [size=8] I/O ports at 1884 [size=4] I/O ports at 1888 [size=8] I/O ports at 1880 [size=4] I/O ports at 1860 [size=32] Memory at d8504400 (32-bit, non-prefetchable) [size=1K] Capabilities: [70] Power Management version 2 Capabilities: [a8] #12 [0010] 00:1f.3 SMBus: Intel Corporation 631xESB/632xESB/3100 Chipset SMBus Controller (rev 09) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: medium devsel, IRQ 106 I/O ports at 1100 [size=32] 02:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Upstream Port (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=02, secondary=03, subordinate=05, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: d8000000-d80fffff Prefetchable memory behind bridge: 00000000d8300000-00000000d8300000 Capabilities: [44] Express Upstream Port IRQ 0 Capabilities: [70] Power Management version 2 Capabilities: [80] #0d [0000] Capabilities: [100] Advanced Error Reporting 02:00.3 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express to PCI-X Bridge (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=02, secondary=06, subordinate=06, sec-latency=64 Capabilities: [44] Express PCI/PCI-X Bridge IRQ 0 Capabilities: [6c] Power Management version 2 Capabilities: [80] #0d [0000] Capabilities: [d8] PCI-X bridge device Capabilities: [100] Advanced Error Reporting 03:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream Port E1 (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=03, secondary=04, subordinate=04, sec-latency=0 Capabilities: [44] Express Downstream Port (Slot-) IRQ 0 Capabilities: [60] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable+ Capabilities: [70] Power Management version 2 Capabilities: [80] #0d [0000] Capabilities: [100] Advanced Error Reporting 03:02.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream Port E3 (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=03, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: d8000000-d80fffff Prefetchable memory behind bridge: 00000000d8300000-00000000d8300000 Capabilities: [44] Express Downstream Port (Slot-) IRQ 0 Capabilities: [60] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable+ Capabilities: [70] Power Management version 2 Capabilities: [80] #0d [0000] Capabilities: [100] Advanced Error Reporting 05:00.0 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01) Subsystem: Super Micro Computer Inc Unknown device 1096 Flags: bus master, fast devsel, latency 0, IRQ 114 Memory at d8020000 (32-bit, non-prefetchable) [size=128K] Memory at d8000000 (32-bit, non-prefetchable) [size=128K] I/O ports at 2000 [size=32] [virtual] Expansion ROM at d8300000 [disabled] [size=64K] Capabilities: [c8] Power Management version 2 Capabilities: [d0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable+ Capabilities: [e0] Express Endpoint IRQ 0 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number bc-86-7d-ff-ff-48-30-00 05:00.1 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01) Subsystem: Super Micro Computer Inc Unknown device 1096 Flags: bus master, fast devsel, latency 0, IRQ 98 Memory at d8060000 (32-bit, non-prefetchable) [size=128K] Memory at d8040000 (32-bit, non-prefetchable) [size=128K] I/O ports at 2020 [size=32] [virtual] Expansion ROM at d8310000 [disabled] [size=64K] Capabilities: [c8] Power Management version 2 Capabilities: [d0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Capabilities: [e0] Express Endpoint IRQ 0 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number bc-86-7d-ff-ff-48-30-00 08:01.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) (prog-if 00 [VGA]) Subsystem: Super Micro Computer Inc Unknown device bc80 Flags: bus master, stepping, fast Back2Back, medium devsel, latency 66, IRQ 11 Memory at d0000000 (32-bit, prefetchable) [size=128M] I/O ports at 3000 [size=256] Memory at d8200000 (32-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at d8220000 [disabled] [size=128K] Capabilities: [50] Power Management version 2

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r3241 - trunk/coreboot-v2/targets/asus/a8v-e_se
by svn＠coreboot.org 16 Apr '08

16 Apr '08

Author: uwe Date: 2008-04-16 02:46:08 +0200 (Wed, 16 Apr 2008) New Revision: 3241 Modified: trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb Log: Change default payload location for easier buildrom support (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb 2008-04-15 17:24:08 UTC (rev 3240) +++ trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb 2008-04-16 00:46:08 UTC (rev 3241) @@ -25,14 +25,14 @@ option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Normal" - payload /tmp/filo.elf + payload ../payload.elf end romimage "fallback" option USE_FALLBACK_IMAGE = 1 option ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Fallback" - payload /tmp/filo.elf + payload ../payload.elf end buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

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[PATCH] CN10K patch, FILO ide discover patch.
by Urbez Santana Roma 15 Apr '08

15 Apr '08

Note: for install this patch, you must download the last coreboot SVN, and install first the patch posted by Corey Osgood, that includes CN700/C7 and jetway mainboard. The filo patch is for correct a problem with FILO when tries to find the IDE disk, if more that one IDE interface is on, and no all IDE's are in native Mode. The count of compatibility interfaces are wrong, and not finds the interface that is marked as a IDE 0x0101 or SATA 0x0180 and not all are native, the search of the io base and control, are wrong. If this is not correct sorry :))) If in VT8237R have SATA as an 0101 and the IDE too 0101 class, with this patch, works, because counts corectly the unique non native interface IDE, as the first. NOTE1: in the epia-cn/Config.lb the IDE and SATA are enabled. NOTE2: in epia-cn/auto.c the values of PCI_DEV(0,0x11,0) 0x50 and 0x51 are different, for have IDE and SATA enableds at function enable_mainboard_devices NOTE3: Here is a file base.c that haves a udelay with use of rtdsc NOTE4: another function via_cn_fixup, fixes the use of PCI devices access to the memory. Must be improved, and not use a fixed value. NOTE5: have a change in cn700/raminit.c for configure in CN the memory. NOTE6: vt8237r configures the SATA device as an IDE class 0x0101 must be 0x0180????? Urbez Santana.

3 2

Missing f71805f.c in fintek/f71805f for V2
by bari 15 Apr '08

15 Apr '08

Corey, Do you have a V2 patch for the Fintek f71805f? There is no f71805f.c in the current svn. When trying to build the jetway we get error: make[1]: *** No rule to make target /f71805f.c', needed by `f71805f.o'. Stop. -Bari

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r3240 - in trunk/payloads/libpayload: curses drivers
by svn＠coreboot.org 15 Apr '08

15 Apr '08

Author: uwe Date: 2008-04-15 19:24:08 +0200 (Tue, 15 Apr 2008) New Revision: 3240 Added: trunk/payloads/libpayload/drivers/speaker.c Removed: trunk/payloads/libpayload/curses/speaker.c Modified: trunk/payloads/libpayload/curses/Makefile.inc trunk/payloads/libpayload/drivers/Makefile.inc Log: Move curses/speaker.c to drivers/ as it's not curses-specific (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/curses/Makefile.inc =================================================================== --- trunk/payloads/libpayload/curses/Makefile.inc 2008-04-15 16:47:20 UTC (rev 3239) +++ trunk/payloads/libpayload/curses/Makefile.inc 2008-04-15 17:24:08 UTC (rev 3240) @@ -29,5 +29,4 @@ TARGETS-$(CONFIG_TINYCURSES) += curses/keyboard.o TARGETS-$(CONFIG_TINYCURSES) += curses/tinycurses.o -TARGETS-$(CONFIG_TINYCURSES) += curses/speaker.o TARGETS-$(CONFIG_TINYCURSES) += curses/colors.o Deleted: trunk/payloads/libpayload/curses/speaker.c =================================================================== --- trunk/payloads/libpayload/curses/speaker.c 2008-04-15 16:47:20 UTC (rev 3239) +++ trunk/payloads/libpayload/curses/speaker.c 2008-04-15 17:24:08 UTC (rev 3240) @@ -1,100 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Datasheet: - * - Name: 82C54 CHMOS Programmable Interval Timer - * - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf - * - Order number: 231244-006 - */ - -#include "local.h" - -#define I82C54_CONTROL_WORD_REGISTER 0x43 /* Write-only. */ - -#define I82C54_COUNTER0 0x40 -#define I82C54_COUNTER1 0x41 -#define I82C54_COUNTER2 0x42 - -#define PC_SPEAKER_PORT 0x61 - -/** - * Use the PC speaker to create a tone/sound of the specified frequency. - * - * The Intel 82C54 CHMOS Programmable Interval Timer (PIT) provides a - * superset of the functions of the original Intel 8253/8254 PIT. It has - * three programmable counters/timers (counter 0, 1, and 2). Counter 2 can - * be used to generate tones/sounds of various frequencies and duration. - * - * See also: - * - http://en.wikipedia.org/wiki/Pc_speaker - * - http://en.wikipedia.org/wiki/Intel_8253 - * - * @param freq The frequency of the tone. - */ -void speaker_enable(u16 freq) -{ - /* Select counter 2. Read/write LSB first, then MSB. Use mode 3 - (square wave generator). Use a 16bit binary counter. */ - outb(0xb6, I82C54_CONTROL_WORD_REGISTER); - - /* Set the desired tone frequency. */ - outb((u8)(freq & 0x00ff), I82C54_COUNTER2); /* LSB. */ - outb((u8)(freq >> 8), I82C54_COUNTER2); /* MSB. */ - - /* Enable the PC speaker (set bits 0 and 1). */ - outb(inb(PC_SPEAKER_PORT) | 0x03, PC_SPEAKER_PORT); -} - -/** - * Disable the PC speaker. - */ -void speaker_disable(void) -{ - /* Disable the PC speaker (clear bits 0 and 1). */ - outb(inb(PC_SPEAKER_PORT) & 0xfc, PC_SPEAKER_PORT); -} - -/** - * Use the PC speaker to create a tone/beep of the specified frequency - * and duration. - * - * Wait for a short amount of time after the beep to make it distinguishable - * from the next beep (if any). - * - * @param freq The frequency of the tone/beep. - * @param duration The duration of the tone/beep in milliseconds. - */ -void speaker_tone(u16 freq, unsigned int duration) -{ - speaker_enable(freq); - mdelay(duration); - speaker_disable(); - mdelay(100); -} Modified: trunk/payloads/libpayload/drivers/Makefile.inc =================================================================== --- trunk/payloads/libpayload/drivers/Makefile.inc 2008-04-15 16:47:20 UTC (rev 3239) +++ trunk/payloads/libpayload/drivers/Makefile.inc 2008-04-15 17:24:08 UTC (rev 3240) @@ -27,7 +27,9 @@ ## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ## SUCH DAMAGE. ## + TARGETS-y += drivers/pci.o +TARGETS-y += drivers/speaker.o TARGETS-$(CONFIG_SERIAL_CONSOLE) += drivers/serial.o TARGETS-$(CONFIG_PC_KEYBOARD) += drivers/keyboard.o Copied: trunk/payloads/libpayload/drivers/speaker.c (from rev 3239, trunk/payloads/libpayload/curses/speaker.c) =================================================================== --- trunk/payloads/libpayload/drivers/speaker.c (rev 0) +++ trunk/payloads/libpayload/drivers/speaker.c 2008-04-15 17:24:08 UTC (rev 3240) @@ -0,0 +1,100 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Datasheet: + * - Name: 82C54 CHMOS Programmable Interval Timer + * - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf + * - Order number: 231244-006 + */ + +#include <libpayload.h> + +#define I82C54_CONTROL_WORD_REGISTER 0x43 /* Write-only. */ + +#define I82C54_COUNTER0 0x40 +#define I82C54_COUNTER1 0x41 +#define I82C54_COUNTER2 0x42 + +#define PC_SPEAKER_PORT 0x61 + +/** + * Use the PC speaker to create a tone/sound of the specified frequency. + * + * The Intel 82C54 CHMOS Programmable Interval Timer (PIT) provides a + * superset of the functions of the original Intel 8253/8254 PIT. It has + * three programmable counters/timers (counter 0, 1, and 2). Counter 2 can + * be used to generate tones/sounds of various frequencies and duration. + * + * See also: + * - http://en.wikipedia.org/wiki/Pc_speaker + * - http://en.wikipedia.org/wiki/Intel_8253 + * + * @param freq The frequency of the tone. + */ +void speaker_enable(u16 freq) +{ + /* Select counter 2. Read/write LSB first, then MSB. Use mode 3 + (square wave generator). Use a 16bit binary counter. */ + outb(0xb6, I82C54_CONTROL_WORD_REGISTER); + + /* Set the desired tone frequency. */ + outb((u8)(freq & 0x00ff), I82C54_COUNTER2); /* LSB. */ + outb((u8)(freq >> 8), I82C54_COUNTER2); /* MSB. */ + + /* Enable the PC speaker (set bits 0 and 1). */ + outb(inb(PC_SPEAKER_PORT) | 0x03, PC_SPEAKER_PORT); +} + +/** + * Disable the PC speaker. + */ +void speaker_disable(void) +{ + /* Disable the PC speaker (clear bits 0 and 1). */ + outb(inb(PC_SPEAKER_PORT) & 0xfc, PC_SPEAKER_PORT); +} + +/** + * Use the PC speaker to create a tone/beep of the specified frequency + * and duration. + * + * Wait for a short amount of time after the beep to make it distinguishable + * from the next beep (if any). + * + * @param freq The frequency of the tone/beep. + * @param duration The duration of the tone/beep in milliseconds. + */ +void speaker_tone(u16 freq, unsigned int duration) +{ + speaker_enable(freq); + mdelay(duration); + speaker_disable(); + mdelay(100); +}

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[PATCH] tint: Add libpayload/tint patch + README
by Uwe Hermann 15 Apr '08

15 Apr '08

See patch. I've added the patch and a small README (which should be extended later) into payloads/external/tint, in order to separate external payloads which we simply port to libpayload from "native" coreboot payloads such as coreinfo. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3239 - in trunk/payloads: . external external/tint
by svn＠coreboot.org 15 Apr '08

15 Apr '08

Author: uwe Date: 2008-04-15 18:47:20 +0200 (Tue, 15 Apr 2008) New Revision: 3239 Added: trunk/payloads/external/ trunk/payloads/external/tint/ trunk/payloads/external/tint/README trunk/payloads/external/tint/libpayload_tint.patch Log: Add the patch for building tint as payload, as well as a small README, into the payloads/external/tint directory. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Added: trunk/payloads/external/tint/README =================================================================== --- trunk/payloads/external/tint/README (rev 0) +++ trunk/payloads/external/tint/README 2008-04-15 16:47:20 UTC (rev 3239) @@ -0,0 +1,9 @@ +------------------------------------------------------------------------------- +tint +------------------------------------------------------------------------------- + +For instructions on how to download, patch, and build tint as a coreboot +payload, please see + + http://www.coreboot.org/Tint + Added: trunk/payloads/external/tint/libpayload_tint.patch =================================================================== --- trunk/payloads/external/tint/libpayload_tint.patch (rev 0) +++ trunk/payloads/external/tint/libpayload_tint.patch 2008-04-15 16:47:20 UTC (rev 3239) @@ -0,0 +1,325 @@ +Patch tint 0.03b to be usable as coreboot payload, linked against +the libpayload library. + +Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> + +diff -Naur tint-0.03b.orig/config.h tint-0.03b/config.h +--- tint-0.03b.orig/config.h 2001-12-08 00:03:24.000000000 +0100 ++++ tint-0.03b/config.h 2008-04-11 22:19:35.000000000 +0200 +@@ -29,7 +29,16 @@ + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#include <libpayload.h> ++#include <curses.h> ++#define random(x) rand(x) ++#define srandom(x) srand(x) ++#define curs_set(x) ++typedef int time_t; ++ + /* Score file */ ++#if 0 + const char scorefile[] = SCOREFILE; ++#endif + + #endif /* #ifndef CONFIG_H */ +diff -Naur tint-0.03b.orig/engine.c tint-0.03b/engine.c +--- tint-0.03b.orig/engine.c 2005-07-17 13:26:22.000000000 +0200 ++++ tint-0.03b/engine.c 2008-04-11 22:19:35.000000000 +0200 +@@ -27,8 +27,12 @@ + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#include "config.h" ++ ++#if 0 + #include <stdlib.h> + #include <string.h> ++#endif + + #include "typedefs.h" + #include "utils.h" +diff -Naur tint-0.03b.orig/io.c tint-0.03b/io.c +--- tint-0.03b.orig/io.c 2001-12-07 16:48:20.000000000 +0100 ++++ tint-0.03b/io.c 2008-04-11 22:19:35.000000000 +0200 +@@ -27,9 +27,13 @@ + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#include "config.h" ++ ++#if 0 + #include <stdarg.h> /* va_list(), va_start(), va_end() */ + #include <sys/time.h> /* gettimeofday() */ + #include <unistd.h> /* gettimeofday() */ ++#endif + + #include <curses.h> + +@@ -70,7 +74,11 @@ + /* Initialize screen */ + void io_init () + { ++ curses_enable_serial(0); ++ curses_enable_vga(1); + initscr (); ++ halfdelay(1); ++ timeout(1); + start_color (); + curs_set (CURSOR_INVISIBLE); + out_attr = A_NORMAL; +@@ -176,11 +184,17 @@ + /* Read a character. Please note that you MUST call in_timeout() before in_getch() */ + int in_getch () + { ++#if 0 + struct timeval starttv,endtv; ++#endif + int ch; ++#if 0 + timeout (in_timeleft / 1000); + gettimeofday (&starttv,NULL); ++#endif + ch = getch (); ++ mdelay(150); ++#if 0 + gettimeofday (&endtv,NULL); + /* Timeout? */ + if (ch == ERR) +@@ -198,6 +212,7 @@ + in_timeleft -= endtv.tv_usec; + if (in_timeleft <= 0) in_timeleft = in_timetotal; + } ++#endif + return ch; + } + +diff -Naur tint-0.03b.orig/Makefile tint-0.03b/Makefile +--- tint-0.03b.orig/Makefile 2005-07-17 13:30:54.000000000 +0200 ++++ tint-0.03b/Makefile 2008-04-11 22:19:35.000000000 +0200 +@@ -28,6 +28,36 @@ + # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ++LIBPAYLOAD_DIR := ../libpayload ++CC := $(LIBPAYLOAD_DIR)/bin/lpgcc ++AS := $(LIBPAYLOAD_DIR)/bin/lpas ++# CFLAGS := -Wall -Werror -Os ++CFLAGS := -Wall -Os ++TARGET := tint ++OBJS := $(TARGET).o engine.o io.o utils.o ++ ++all: $(TARGET).elf ++ ++$(TARGET).elf: $(OBJS) ++ $(CC) -o $@ $(OBJS) ++ ++%.o: %.c ++ $(CC) $(CFLAGS) -c -o $@ $< ++ ++%.S.o: %.S ++ $(AS) --32 -o $@ $< ++ ++clean: ++ rm -f $(TARGET).elf *.o ++ ++distclean: clean ++ ++ ++ ++ ++ ++ifdef $(UNUSED) ++ + #CROSS = arm-linux- + + bindir = $(DESTDIR)/usr/games +@@ -110,3 +140,4 @@ + distclean: clean + $(MAKE) -C debian clean + ++endif +diff -Naur tint-0.03b.orig/tint.c tint-0.03b/tint.c +--- tint-0.03b.orig/tint.c 2005-07-17 13:26:43.000000000 +0200 ++++ tint-0.03b/tint.c 2008-04-11 22:19:35.000000000 +0200 +@@ -27,6 +27,7 @@ + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#if 0 + #include <stdlib.h> + #include <stdio.h> + #include <string.h> +@@ -34,6 +35,7 @@ + #include <pwd.h> + #include <sys/types.h> + #include <unistd.h> ++#endif + + #include "typedefs.h" + #include "utils.h" +@@ -321,6 +323,7 @@ + time_t timestamp; + } score_t; + ++#if 0 + static void getname (char *name) + { + struct passwd *pw = getpwuid (geteuid ()); +@@ -337,7 +340,9 @@ + name[NAMELEN - 1] = '\0'; + } + } ++#endif + ++#if 0 + static void err1 () + { + fprintf (stderr,"Error creating %s\n",scorefile); +@@ -349,10 +354,11 @@ + fprintf (stderr,"Error writing to %s\n",scorefile); + exit (EXIT_FAILURE); + } ++#endif + + void showplayerstats (engine_t *engine) + { +- fprintf (stderr, ++ printf ( + "\n\t PLAYER STATISTICS\n\n\t" + "Score %11d\n\t" + "Efficiency %11d\n\t" +@@ -360,6 +366,7 @@ + GETSCORE (engine->score),engine->status.efficiency,GETSCORE (engine->score) / getsum ()); + } + ++#if 0 + static void createscores (int score) + { + FILE *handle; +@@ -394,7 +401,9 @@ + fprintf (stderr,"%s",scoretitle); + fprintf (stderr,"\t 1* %7d %s\n\n",score,scores[0].name); + } ++#endif + ++#if 0 + static int cmpscores (const void *a,const void *b) + { + int result; +@@ -412,7 +421,9 @@ + /* timestamps is equal */ + return 0; + } ++#endif + ++#if 0 + static void savescores (int score) + { + FILE *handle; +@@ -490,11 +501,13 @@ + } + fprintf (stderr,"\n"); + } ++#endif + + /***************************************************************************/ + /***************************************************************************/ + /***************************************************************************/ + ++#if 0 + static void showhelp () + { + fprintf (stderr,"USAGE: tint [-h] [-l level] [-n]\n"); +@@ -504,9 +517,11 @@ + fprintf (stderr," -d Draw vertical dotted lines\n"); + exit (EXIT_FAILURE); + } ++#endif + + static void parse_options (int argc,char *argv[]) + { ++#if 0 + int i = 1; + while (i < argc) + { +@@ -536,10 +551,12 @@ + } + i++; + } ++#endif + } + + static void choose_level () + { ++#if 0 + char buf[NAMELEN]; + + do +@@ -549,6 +566,8 @@ + buf[strlen (buf) - 1] = '\0'; + } + while (!str2int (&level,buf) || level < MINLEVEL || level > MAXLEVEL); ++#endif ++ level = 1; + } + + /***************************************************************************/ +@@ -663,8 +682,15 @@ + if (ch != 'q') + { + showplayerstats (&engine); ++#if 0 + savescores (GETSCORE (engine.score)); ++#endif + } ++ mvprintw(10, 10, "Bye."); ++ refresh(); ++ halt(); ++#if 0 + exit (EXIT_SUCCESS); ++#endif + } + +diff -Naur tint-0.03b.orig/utils.c tint-0.03b/utils.c +--- tint-0.03b.orig/utils.c 2001-12-07 16:49:19.000000000 +0100 ++++ tint-0.03b/utils.c 2008-04-11 22:19:35.000000000 +0200 +@@ -27,9 +27,13 @@ + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#include "config.h" ++ ++#if 0 + #include <stdlib.h> + #include <time.h> + #include <limits.h> ++#endif + + #include "typedefs.h" + +@@ -41,8 +45,11 @@ + #ifdef USE_RAND + srand (time (NULL)); + #else ++#if 0 + srandom (time (NULL)); + #endif ++ srandom (123); ++#endif + } + + /* +@@ -61,6 +68,7 @@ + * Convert an str to long. Returns TRUE if successful, + * FALSE otherwise. + */ ++#if 0 + bool str2int (int *i,const char *str) + { + char *endptr; +@@ -69,3 +77,4 @@ + return TRUE; + } + ++#endif

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#94: Need getch_timeout() function in libpayload
by coreboot 15 Apr '08

15 Apr '08

#94: Need getch_timeout() function in libpayload ---------------------------------+------------------------------------------ Reporter: jcrouse | Owner: jcrouse Type: defect | Status: new Priority: major | Milestone: Component: libpayload | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ libpayload needs a getch_timeout() function that will gracefully return after a certain amount of time if a keypress isn't received. This is used to update the screen at constant intervals. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/94> coreboot <http://www.coreboot.org/>

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coreboot April 2008