coreboot April 2008

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404 discussions

[PATCH] artecgroup/dbe62: Set up 4MB mode for LPC dongle
by Mart Raudsepp 16 Apr '08

16 Apr '08

artecgroup/dbe62: Set up 4MB mode for LPC dongle This way we can fit a kernel and initramfs on the dongle's free ~3.75MB space and have a debug system bootable right from inside the dongle. The start address of the dongle is mem@0xffc00000 for FILO with 4MB minus ROM area available. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- For your consideration of suitability for stage1 mainboard setup. mainboard/artecgroup/dbe62/stage1.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/mainboard/artecgroup/dbe62/stage1.c b/mainboard/artecgroup/dbe62/stage1.c index 45a7c1c..45609ce 100644 --- a/mainboard/artecgroup/dbe62/stage1.c +++ b/mainboard/artecgroup/dbe62/stage1.c @@ -59,6 +59,9 @@ void hardware_stage1(void) * early MSR setup for the CS5536. */ cs5536_setup_onchipuart(2); + + /* Set up 4MB mode for Artec LPC Dongle */ + outb(0xf4,0x88); } void mainboard_pre_payload(void) -- 1.5.4.5

2 2

r660 - coreboot-v3/mainboard/artecgroup/dbe62
by svn＠coreboot.org 16 Apr '08

16 Apr '08

Author: ward Date: 2008-04-16 23:34:56 +0200 (Wed, 16 Apr 2008) New Revision: 660 Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c Log: artecgroup/dbe62: Set up 4MB mode for LPC dongle This way we can fit a kernel and initramfs on the dongle's free ~3.75MB space and have a debug system bootable right from inside the dongle. The start address of the dongle is mem@0xffc00000 for FILO with 4MB minus ROM area available. This should be a no-op when not booting from the dongle. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-04-16 16:40:45 UTC (rev 659) +++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-04-16 21:34:56 UTC (rev 660) @@ -59,6 +59,9 @@ * early MSR setup for the CS5536. */ cs5536_setup_onchipuart(2); + + /* Set up 4MB mode for Artec LPC Dongle (this should be a no-op when not booting from the dongle) */ + outb(0xf4,0x88); } void mainboard_pre_payload(void)

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coreboot AGESA support
by Tom Sylla 16 Apr '08

16 Apr '08

This is mostly for the AMD guys, but is probably relevant to many on the list. Is anyone working on getting AGESA working in coreboot again? Back when we were deciding on a firmware solution for our platform, the plan for LinuxBIOS AGESA support was a very good advantage for coreboot. After seeing the path for AGESA support languish for a few months, as well as Opteron support in general, we decided to use AMI instead (for various other reasons too). With AMI, every month or so, we get new AGESA drop, plop it in our build, and get various errata fixes, HT support, Barcelona fixes, etc. Is there any plan for this?

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r659 - in coreboot-v3: arch/x86/geodelx northbridge/amd/geodelx
by svn＠coreboot.org 16 Apr '08

16 Apr '08

Author: hailfinger Date: 2008-04-16 18:40:45 +0200 (Wed, 16 Apr 2008) New Revision: 659 Modified: coreboot-v3/arch/x86/geodelx/geodelx.c coreboot-v3/northbridge/amd/geodelx/raminit.c Log: northbridge/amd/geodelx/raminit.c:auto_size_dimm() checks for the mathematically impossible condition of a value being above and below the specified range at the same time. Change it to check for out-of-range. arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it will keep going and mess up DRAM timings. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Both changes look right to me. Acked-by: Marc Jones <marc.jones(a)amd.com> The raminit in v2 was fixed in r2899 | rminnich | 2007-10-26 with this log: > The lxraminit change fixes a bug (&& used instead of ||) [...] > Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> > Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/geodelx/geodelx.c =================================================================== --- coreboot-v3/arch/x86/geodelx/geodelx.c 2008-04-14 14:19:09 UTC (rev 658) +++ coreboot-v3/arch/x86/geodelx/geodelx.c 2008-04-16 16:40:45 UTC (rev 659) @@ -386,6 +386,7 @@ msr.hi |= delay_control_table[i].fast_hi; msr.lo |= delay_control_table[i].fast_low; } + break; } } wrmsr(GLCP_DELAY_CONTROLS, msr); Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-04-14 14:19:09 UTC (rev 658) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-04-16 16:40:45 UTC (rev 659) @@ -113,7 +113,7 @@ /* EEPROM byte usage: (5) Number of DIMM Banks */ banner(BIOS_DEBUG, "MODBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); - if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { + if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) { printk(BIOS_EMERG, "Number of module banks not compatible\n"); post_code(ERROR_BANK_SET); hlt(); @@ -124,7 +124,7 @@ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ banner(BIOS_DEBUG, "FIELDBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); - if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { + if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) { printk(BIOS_EMERG, "Number of device banks not compatible\n"); post_code(ERROR_BANK_SET); hlt();

1 0

localizing resets
by Jeremy Jackson 16 Apr '08

16 Apr '08

Slightly related to the TCO timer issue, is that of shotgun approach vs localized resets. TCO timer is just a subset of the "bigiron" features vendors put on their boards. Is global reset an obstacle to using them? I'm reminded of the Machine Check registers. Linux has a boot option, mce=bootlog, to enable reading these when linux starts, to get info regarding the last reboot, if caused by a machine check, since it's likely that the previous generation couldn't log (to disk) in the MCE handler. Linux's mce= defaults to ignoring the register contents at startup, since many BIOS are reset-happy. I bet there's places in Coreboot that do this, like the hypertransport (but I don't know of registers that matter) for example. There are other registers that survive localized (CPU only or other scopes) resets vs power on reset (global), The Intel 845 datasheet mentions that this depends on the board being wired correctly. The common practice of OR-ing the power-on reset (power-good) signals with the front panel reset, defeats many of these features. Power management has made fixing some of that a requirement, dividing a system up into many power wells and reset domains, but there's bound to be boards made that just don't care. (I hope mine isn't one of them) I'm eyeing Cisco's feature that tells you the source of the last reset, power-on, vs firmware monitor cmd, vs others. Does anyone's hareware flag a TCO reset so the next generation can tell that's why it was booted? -- Jeremy Jackson Coplanar Networks (519)489-4903 http://www.coplanar.net jerj(a)coplanar.net

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[PATCH] Halt TCO timer on Intel 3100 chipset
by Ed Swierk 16 Apr '08

16 Apr '08

Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots the system automatically unless software resets the timer periodically. The extra reboot extends boot time by several seconds. The attached patch adds a function to the Intel 3100 southbridge code that halts the TCO timer, thus preventing this extra reboot, and calls the function early in the boot process on the Mt. Arvon board. It also fixes a bug in the LPC device initialization--the ACPI BAR enable flag is bit 7, not bit 4. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

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Re: [coreboot] #88: Add UHCI/OHCI/EHCI support to GRUB2
by coreboot 16 Apr '08

16 Apr '08

#88: Add UHCI/OHCI/EHCI support to GRUB2 ----------------------------+----------------------------------------------- Reporter: uwe | Owner: oxygene Type: enhancement | Status: new Priority: critical | Milestone: Port GRUB2 to coreboot Component: grub2 | Version: Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by stepan): * component: filo => grub2 -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/88#comment:3> coreboot <http://www.coreboot.org/>

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Re: [coreboot] #64: Epia-M COM2 does not work
by coreboot 16 Apr '08

16 Apr '08

#64: Epia-M COM2 does not work -------------------------+-------------------------------------------------- Reporter: stepan | Owner: stepan Type: defect | Status: assigned Priority: major | Milestone: Component: coreboot | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by stepan): * owner: somebody => stepan * status: new => assigned -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/64#comment:1> coreboot <http://www.coreboot.org/>

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Re: [coreboot] #35: Make it possible to boot Windows using coreboot
by coreboot 16 Apr '08

16 Apr '08

#35: Make it possible to boot Windows using coreboot ----------------------------+----------------------------------------------- Reporter: uwe | Owner: Type: enhancement | Status: new Priority: critical | Milestone: Going mainstream Component: adlo | Version: Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by stepan): * summary: Make it possible to boot Windows using LinuxBIOS => Make it possible to boot Windows using coreboot Old description: > From > http://www.linuxbios.org/pipermail/linuxbios/2006-November/016793.html: > > {{{ > The issue of booting XP just will not go away. > > So, there are two options I see, in order of preference: > 1. find some way, using kexec etc., to boot XP under Linux, then put > Linux > in FLASH; done > 2. revive ADLO > > there have been a number of suggestions for how to do the first one. > 1. freeldr (vapor?) > 2. tinyldr (vapor?) > > any non-vaporous ones out there? This note is an attempt to start a > discussion and discovery on this subject. > }}} New description: From http://www.linuxbios.org/pipermail/linuxbios/2006-November/016793.html: {{{ The issue of booting XP just will not go away. So, there are two options I see, in order of preference: 1. find some way, using kexec etc., to boot XP under Linux, then put Linux in FLASH; done 2. revive ADLO there have been a number of suggestions for how to do the first one. 1. freeldr 2. tinyldr any other usable ones out there? This note is an attempt to start a discussion and discovery on this subject. }}} -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/35#comment:8> coreboot <http://www.coreboot.org/>

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Re: [coreboot] #66: Merge all debug.c instances
by coreboot 16 Apr '08

16 Apr '08

#66: Merge all debug.c instances -------------------------+-------------------------------------------------- Reporter: uwe | Owner: somebody Type: defect | Status: closed Priority: major | Milestone: Cosmetic fixes Component: coreboot | Version: v2 Resolution: wontfix | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by stepan): * status: new => closed * resolution: => wontfix Comment: Let's focus on v3 with cleanup issues. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/66#comment:1> coreboot <http://www.coreboot.org/>

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coreboot April 2008