Author: ward
Date: 2008-04-17 19:27:13 +0200 (Thu, 17 Apr 2008)
New Revision: 663
Added:
coreboot-v3/mainboard/pcengines/alix2c3/
Modified:
coreboot-v3/mainboard/pcengines/Kconfig
coreboot-v3/mainboard/pcengines/alix2c3/Kconfig
coreboot-v3/mainboard/pcengines/alix2c3/defconfig
coreboot-v3/mainboard/pcengines/alix2c3/dts
coreboot-v3/mainboard/pcengines/alix2c3/initram.c
coreboot-v3/mainboard/pcengines/alix2c3/irq_tables.h
coreboot-v3/mainboard/pcengines/alix2c3/stage1.c
Log:
Add pcengines alix.2c3 support.
There is still one outstanding issue - eth2 and the USB ports fight over IRQs.
Signed-off-by: Ward Vandewege <ward(a)gnu.org>
Acked-by: Marc Jones <marc.jones(a)amd.com>
Modified: coreboot-v3/mainboard/pcengines/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/Kconfig 2008-04-17 16:30:27 UTC (rev 662)
+++ coreboot-v3/mainboard/pcengines/Kconfig 2008-04-17 17:27:13 UTC (rev 663)
@@ -35,7 +35,19 @@
help
PC Engines ALIX1.C.
+config BOARD_PCENGINES_ALIX2C3
+ bool "ALIX.2C3"
+ select ARCH_X86
+ select CPU_AMD_GEODELX
+ select OPTION_TABLE
+ select NORTHBRIDGE_AMD_GEODELX
+ select SOUTHBRIDGE_AMD_CS5536
+ select PIRQ_TABLE
+ help
+ PC Engines ALIX.2C3.
+
endchoice
source "mainboard/pcengines/alix1c/Kconfig"
+source "mainboard/pcengines/alix2c3/Kconfig"
Modified: coreboot-v3/mainboard/pcengines/alix2c3/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Kconfig 2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/mainboard/pcengines/alix2c3/Kconfig 2008-04-17 17:27:13 UTC (rev 663)
@@ -22,7 +22,7 @@
config MAINBOARD_NAME
string
- default pcengines/alix1c
- depends BOARD_PCENGINES_ALIX1C
+ default pcengines/alix2c3
+ depends BOARD_PCENGINES_ALIX2C3
help
This is the default mainboard name.
Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/defconfig 2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-04-17 17:27:13 UTC (rev 663)
@@ -1,16 +1,15 @@
#
# Automatically generated make config: don't edit
-# coreboot version: 3.0.0
-# Sun Feb 24 11:45:09 2008
+# coreboot version: 3.0."656"'
+# Wed Apr 9 20:59:03 2008
#
#
# General setup
#
-CONFIG_EXPERIMENTAL=y
-CONFIG_EXPERT=y
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_EXPERT is not set
CONFIG_LOCALVERSION=""
-# CONFIG_BEEPS is not set
#
# Mainboard
@@ -20,14 +19,15 @@
# CONFIG_VENDOR_ARTECGROUP is not set
# CONFIG_VENDOR_EMULATION is not set
CONFIG_VENDOR_PCENGINES=y
-CONFIG_MAINBOARD_NAME="pcengines/alix1c"
-CONFIG_BOARD_PCENGINES_ALIX1C=y
+CONFIG_MAINBOARD_NAME="pcengines/alix2c3"
+# CONFIG_BOARD_PCENGINES_ALIX1C is not set
+CONFIG_BOARD_PCENGINES_ALIX2C3=y
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
CONFIG_COREBOOT_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=480
+CONFIG_COREBOOT_ROMSIZE_KB=512
CONFIG_ARCH_X86=y
CONFIG_ARCH="x86"
CONFIG_CPU_AMD_GEODELX=y
@@ -41,9 +41,9 @@
#
CONFIG_COMPRESSION_LZMA=y
# CONFIG_COMPRESSION_NRV2B is not set
-# CONFIG_DEFAULT_COMPRESSION_LZMA is not set
+CONFIG_DEFAULT_COMPRESSION_LZMA=y
# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set
-CONFIG_DEFAULT_COMPRESSION_NONE=y
+# CONFIG_DEFAULT_COMPRESSION_NONE is not set
#
# Console
@@ -67,15 +67,9 @@
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
-# CONFIG_CONSOLE_USB is not set
+CONFIG_CONSOLE_BUFFER=y
#
-# Cosmetic console options
-#
-# CONFIG_CONSOLE_PREFIX is not set
-# CONFIG_CONSOLE_BUFFER is not set
-
-#
# Devices
#
CONFIG_PCI_OPTION_ROM_RUN=y
@@ -90,13 +84,13 @@
#
CONFIG_NORTHBRIDGE_AMD_GEODELX=y
CONFIG_SOUTHBRIDGE_AMD_CS5536=y
-CONFIG_SUPERIO_WINBOND_W83627HF=y
CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32
#
# Payload
#
-CONFIG_PAYLOAD_PREPARSE_ELF=y
-# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_ELF_LOADER is not set
+CONFIG_PAYLOAD_ELF=y
# CONFIG_PAYLOAD_NONE is not set
CONFIG_PAYLOAD_FILE="../payload.elf"
+# CONFIG_ZERO_AFTER_PAYLOAD is not set
Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-04-17 17:27:13 UTC (rev 663)
@@ -20,15 +20,13 @@
/{
mainboard-vendor = "PC Engines";
- mainboard-name = "ALIX1.C";
+ mainboard-name = "ALIX.2C3";
cpus { };
apic@0 {
/config/("northbridge/amd/geodelx/apic");
};
domain@0 {
/config/("northbridge/amd/geodelx/domain");
- /* Video RAM has to be in 2MB chunks. */
- geode_video_mb = "8";
pci@1,0 {
/config/("northbridge/amd/geodelx/pci");
};
@@ -45,10 +43,12 @@
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
+ /* COM1 settings */
+ com1_enable = "1";
+ com1_address = "0x3f8";
+ com1_irq = "4";
+ /* this board does not really have vga; disable it (pci device 00:01.1) */
+ unwanted_vpci = < 80000900 0 >;
};
- ioport@46 {
- /config/("superio/winbond/w83627hf/dts");
- com1enable = "1";
- };
};
};
Modified: coreboot-v3/mainboard/pcengines/alix2c3/initram.c
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/mainboard/pcengines/alix2c3/initram.c 2008-04-17 17:27:13 UTC (rev 663)
@@ -71,7 +71,7 @@
{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
{SPD_NUM_BANKS_PER_SDRAM, 4},
{SPD_PRIMARY_SDRAM_WIDTH, 8},
- {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */
+ {SPD_NUM_DIMM_BANKS, 1}, /* ALIX.2C3 is 1 bank. */
{SPD_NUM_COLUMNS, 0xa},
{SPD_NUM_ROWS, 3},
{SPD_REFRESH, 0x3a},
@@ -126,16 +126,13 @@
}
/**
- * main for initram for the PC Engines Alix 1C. It might seem that you
+ * main for initram for the PC Engines Alix.2c3. It might seem that you
* could somehow do these functions in, e.g., the cpu code, but the
* order of operations and what those operations are is VERY strongly
* mainboard dependent. It's best to leave it in the mainboard code.
*/
int main(void)
{
- u8 smb_devices[] = {
- DIMM0, DIMM1
- };
printk(BIOS_DEBUG, "Hi there from stage1\n");
post_code(POST_START_OF_MAIN);
Modified: coreboot-v3/mainboard/pcengines/alix2c3/irq_tables.h
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h 2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/mainboard/pcengines/alix2c3/irq_tables.h 2008-04-17 17:27:13 UTC (rev 663)
@@ -20,13 +20,13 @@
#include <pirq_routing.h>
/* Number of slots and devices in the PIR table */
-#define IRQ_SLOT_COUNT 5
+#define IRQ_SLOT_COUNT 6
/* Platform IRQs */
-#define PIRQA 11
+#define PIRQA 9
#define PIRQB 10
#define PIRQC 11
-#define PIRQD 9
+#define PIRQD 12
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
@@ -41,14 +41,15 @@
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
/*
- * ALIX1.C interrupt wiring.
+ * ALIX.2C3 interrupt wiring.
*
* Devices are:
*
- * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
+ * 00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31)
* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
- * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
- * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
+ * 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
+ * 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
+ * 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
@@ -56,18 +57,18 @@
* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
*
* The only devices that interrupt are:
- *
+
* What Device IRQ PIN PIN WIRED TO
* -------------------------------------------------
- * AES 00:01.2 0a 01 A A
- * 3VPCI 00:0c.0 0a 01 A A
- * eth0 00:0d.0 0b 01 A B
- * mpci 00:0e.0 0a 01 A A
- * usb 00:0f.3 0b 02 B B
- * usb 00:0f.4 0b 04 D D
- * usb 00:0f.5 0b 04 D D
+ * AES 00:01.2 09 01 A A
+ * eth0 00:09.0 09 01 A B
+ * eth1 00:0a.0 10 01 A C
+ * eth2 00:0b.0 11 01 A D
+ * minipci 00:0c.0 09 01 A A
+ * audio 00:0f.3 05 02 B internal
+ * usb (ohci) 00:0f.4 15 04 D internal
+ * usb (ehci) 00:0f.5 15 04 D internal
*
- * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
*/
const struct irq_routing_table intel_irq_routing_table = {
@@ -90,16 +91,19 @@
/* CPU */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
- /* PCI (slot 1) */
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
+ /* On-board eth0 */
+ {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
- /* On-board ethernet */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+ /* On-board eth1 */
+ {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
- /* Mini PCI (slot 2) */
- {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
+ /* On-board eth2 */
+ {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
- /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+ /* Mini PCI (slot 1) */
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
+
+ /* Chipset slots */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
}
};
Modified: coreboot-v3/mainboard/pcengines/alix2c3/stage1.c
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/stage1.c 2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/mainboard/pcengines/alix2c3/stage1.c 2008-04-17 17:27:13 UTC (rev 663)
@@ -28,14 +28,11 @@
#include <io.h>
#include <amd_geodelx.h>
#include <southbridge/amd/cs5536/cs5536.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#define SERIAL_DEV W83627HF_SP1
#define SERIAL_IOBASE 0x3f8
void hardware_stage1(void)
{
- void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase);
post_code(POST_START_OF_MAIN);
geodelx_msr_init();
@@ -45,9 +42,7 @@
* it is counting on some early MSR setup
* for cs5536.
*/
- cs5536_disable_internal_uart();
- w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
-
+ cs5536_setup_onchipuart(1);
}
void mainboard_pre_payload(void)
