coreboot April 2008

coreboot@coreboot.org

75 participants
404 discussions

RTC
by Jordan Crouse 20 Apr '08

20 Apr '08

I'm puttering about in libpayload doing silly things with the real time clock, and it occurred to me to figure out if coreboot knows how to set the clock to a sane value if CMOS had been cleared or something similar. I looked in v2 at pc80/mc146818rtc.c, and the code that writes to the clock appears to be #if 0ed out. I couldn't find any where else where the clock would be set. The same thing is disabled on v3. According to svn blame, it has been like that ever since ebiderm checked in v2. is there an interesting story as to why this is disabled? IMHO, we should be setting the clock to a sane value if it is determined to be bad, especially since we'll probably have some payloads soon that will care what time it is. Not so much that they need to be accurate down to the microsecond, but more that I want to be sure that if I read the clock, its not bogus. Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

5 4

how embarassing
by ron minnich 20 Apr '08

20 Apr '08

my wife just called me and said "how do I know what version of LB I have on this machine? I just run dtidump on the other nodes". well, I had no answer. At least not a good one. how embarassing! I guess dti just got more important to me. ron

7 10

[PATCH] v3: fix bugs in Geode LX RAMinit
by Carl-Daniel Hailfinger 20 Apr '08

20 Apr '08

Marc? It would be nice if you could read through the code and verify the things I did. northbridge/amd/geodelx/raminit.c:auto_size_dimm() checks for the mathematically impossible condition of a value being above and below the specified range at the same time. Change it to check for out-of-range. arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it will keep going and mess up DRAM timings. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-geodelx_dram_fixes/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3-geodelx_dram_fixes/northbridge/amd/geodelx/raminit.c (Revision 638) +++ LinuxBIOSv3-geodelx_dram_fixes/northbridge/amd/geodelx/raminit.c (Arbeitskopie) @@ -79,7 +79,7 @@ /* EEPROM byte usage: (5) Number of DIMM Banks */ banner(BIOS_DEBUG, "MODBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); - if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { + if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) { printk(BIOS_EMERG, "Number of module banks not compatible\n"); post_code(ERROR_BANK_SET); hlt(); @@ -90,7 +90,7 @@ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ banner(BIOS_DEBUG, "FIELDBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); - if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { + if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) { printk(BIOS_EMERG, "Number of device banks not compatible\n"); post_code(ERROR_BANK_SET); hlt(); Index: LinuxBIOSv3-geodelx_dram_fixes/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3-geodelx_dram_fixes/arch/x86/geodelx/geodelx.c (Revision 638) +++ LinuxBIOSv3-geodelx_dram_fixes/arch/x86/geodelx/geodelx.c (Arbeitskopie) @@ -386,6 +386,7 @@ msr.hi |= delay_control_table[i].fast_hi; msr.lo |= delay_control_table[i].fast_low; } + break; } } wrmsr(GLCP_DELAY_CONTROLS, msr); -- http://www.hailfinger.org/

6 11

r150 - in buildrom-devel/packages: coreboot-v3 roms
by svn＠coreboot.org 19 Apr '08

19 Apr '08

Author: ward Date: 2008-04-19 16:52:31 +0200 (Sat, 19 Apr 2008) New Revision: 150 Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk buildrom-devel/packages/roms/roms.mk Log: Remove some gratuitous echos. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk =================================================================== --- buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-04-19 13:51:50 UTC (rev 149) +++ buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-04-19 14:52:31 UTC (rev 150) @@ -35,7 +35,6 @@ CBV3_PAYLOAD_TARGET=$(CBV3_DIR)/payload.elf $(CBV3_PAYLOAD_TARGET): $(PAYLOAD_TARGET) - @ echo $(PAYLOAD_TARGET) @ cp $< $@ $(SOURCE_DIR)/$(CBV3_TARBALL): Modified: buildrom-devel/packages/roms/roms.mk =================================================================== --- buildrom-devel/packages/roms/roms.mk 2008-04-19 13:51:50 UTC (rev 149) +++ buildrom-devel/packages/roms/roms.mk 2008-04-19 14:52:31 UTC (rev 150) @@ -12,7 +12,7 @@ endif $(ROM_DIR): - mkdir -p $(ROM_DIR) + @ mkdir -p $(ROM_DIR) roms: $(ROM_DIR) $(OPTIONROM_TARGETS)

1 0

r665 - coreboot-v3/mainboard/pcengines/alix2c3
by svn＠coreboot.org 19 Apr '08

19 Apr '08

Author: ward Date: 2008-04-19 16:29:56 +0200 (Sat, 19 Apr 2008) New Revision: 665 Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig Log: The default config (used by buildrom) should not have a payload defined. Buildrom handles that. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-04-18 07:37:43 UTC (rev 664) +++ coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-04-19 14:29:56 UTC (rev 665) @@ -90,7 +90,5 @@ # Payload # # CONFIG_PAYLOAD_ELF_LOADER is not set -CONFIG_PAYLOAD_ELF=y -# CONFIG_PAYLOAD_NONE is not set -CONFIG_PAYLOAD_FILE="../payload.elf" -# CONFIG_ZERO_AFTER_PAYLOAD is not set +# CONFIG_PAYLOAD_ELF is not set +CONFIG_PAYLOAD_NONE=y

1 0

r149 - buildrom-devel
by svn＠coreboot.org 19 Apr '08

19 Apr '08

Author: ward Date: 2008-04-19 15:51:50 +0200 (Sat, 19 Apr 2008) New Revision: 149 Modified: buildrom-devel/Makefile Log: Revert erroneous change from my last patch; we really *do* want a payload in the lar file... Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/Makefile =================================================================== --- buildrom-devel/Makefile 2008-04-18 16:07:53 UTC (rev 148) +++ buildrom-devel/Makefile 2008-04-19 13:51:50 UTC (rev 149) @@ -84,6 +84,7 @@ rom: $(HOSTTOOLS-y) payload $(COREBOOT-y) @ cp $(CBV3_OUTPUT) $(TARGET_ROM_FILE) + @ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(CBV3_PAYLOAD_TARGET):normal/payload ifeq ($(CONFIG_VSA_LEGACY),y) @ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(SOURCE_DIR)/amd_vsa_lx_1.01.bin:blob/vsa endif

1 0

[v2][patch] add SMSC SCH3112 superio
by Chris Kilgour 19 Apr '08

19 Apr '08

This trivial patch adds the SMSC SCH3112 superio chip ID to the generic SMSC support, and corrects a small typo. With this patch, coreboot v2 on a mainboard with SCH3112 has been demonstrated to correctly use the serial port. No other chip functions were tested. Signed-off-by: Christopher Kilgour <techie(a)whiterocker.com>

3 2

r3244 - trunk/coreboot-v2/src/superio/smsc/smscsuperio
by svn＠coreboot.org 19 Apr '08

19 Apr '08

Author: uwe Date: 2008-04-19 15:32:19 +0200 (Sat, 19 Apr 2008) New Revision: 3244 Modified: trunk/coreboot-v2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c Log: This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the generic SMSC support, and corrects a small typo. With this patch, coreboot v2 on a mainboard with SCH3112 has been demonstrated to correctly use the serial port. No other chip functions were tested. Signed-off-by: Christopher Kilgour <techie(a)whiterocker.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c 2008-04-18 20:48:22 UTC (rev 3243) +++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c 2008-04-19 13:32:19 UTC (rev 3244) @@ -30,7 +30,7 @@ * Enable the specified serial port. * * @param dev The device to use. - * @param dev The I/O base of the serial port (usually 0x3f8/0x2f8). + * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ static inline void smscsuperio_enable_serial(device_t dev, uint16_t iobase) { Modified: trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c 2008-04-18 20:48:22 UTC (rev 3243) +++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c 2008-04-19 13:32:19 UTC (rev 3244) @@ -56,6 +56,7 @@ #define LPC47B397 0x6f #define A8000 0x77 /* ASUS A8000, a rebranded DME1737(?) */ #define DME1737 0x78 +#define SCH3112 0x7c #define SCH5307 0x81 /* Rebranded LPC47B397(?) */ /* Register defines */ @@ -127,6 +128,7 @@ {LPC47B397,{0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, {A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, + {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, };

1 0

problem about ioapic
by aaron lwe 19 Apr '08

19 Apr '08

hello, I'm trying to make vt8237r ioapic work, but kernel cannot boot. Kernel seems to have problems about 8254 timer: ENABLING IO-APIC IRQs ..TIMER: vector=0x31 apic1=0 pin1=2 apic2=0 pin2=0 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found pin 0) ... failed. ...trying to set up timer as Virtual Wire IRQ... works. Using local APIC timer interrupts. And kernel hangs at: scsi0 : pata_via scsi1 : pata_via ata1: PATA max UDMA/133 cmd 0x000101f0 ctl 0x000103f6 bmdma 0x00011ce0 irq 14 ata2: PATA max UDMA/133 cmd 0x00010170 ctl 0x00010376 bmdma 0x00011ce8 irq 15 usb 1-2: configuration #1 chosen from 1 choice input: HID 04d9:0499 as /class/input/input1 input: USB HID v1.10 Mouse [HID 04d9:0499] on usb-0000:00:10.0-2 ata1.00: qc timeout (cmd 0x27) ata1.00: ata_hpa_resize 1: hpa sectors (0) is smaller than sectors (156301488) ata1.00: failed to set xfermode (err_mask=0x40) ata1.00: limiting speed to UDMA/33:PIO3 ata1: failed to recover some devices, retrying in 5 secs ata1.00: qc timeout (cmd 0x27) ata1.00: ata_hpa_resize 1: hpa sectors (0) is smaller than sectors (156301488) ata1.00: failed to set xfermode (err_mask=0x40) ata1.00: disabled ata1: EH pending after completion, repeating EH (cnt=4) ata1: soft resetting port ata1: EH complete Waiting for driver initialization. Loading ata_generic.ko module Trying to resume from /dev/sda7 Unable to access resume device (/dev/sda7) CreKernel panic - not syncing: Attempted to kill init! I've created floating table in mptable.c and tried both factory bios config table and the one created by mptable in util directory. same result. the kernel parameter I passed is acpi=off apic=debug. local apic should be setup in lapic.c, this is a c7 cpu and CONFIG_IOAPIC is set to1. so what's left to be setup? thanks.

2 2

Re: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
by joe＠settoplinux.org 19 Apr '08

19 Apr '08

On Tue, 2008-04-08 at 01:13 +0200, Peter Stuge wrote: > True, but it's not very easy to regularly poke the timer without an > interrupt - or the code will be full of try_poke() every other line. What about the mostly existing code that pokes port 0x80? make it a macro that also pokes the WDT? If there are "long" sections for a single POST code, (like clearing 4GB ECC ram), having a bit toggling would be less boring to watch anyhow. I was reading datasheet for Intel 845 chipset, there seems to be a lot of registers outside the reset domain of the processor. Adding in a 3rd poke of the POST code to a scratch register like that, would mean that the last POST code before the WDT resets the CPU would be available to the next incarnation (perhaps fallback). Hmm, very interesting. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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coreboot April 2008