coreboot April 2008

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r3252 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
by svn＠coreboot.org 23 Apr '08

23 Apr '08

Author: mjones Date: 2008-04-23 01:32:56 +0200 (Wed, 23 Apr 2008) New Revision: 3252 Removed: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb trunk/coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c Log: Clean up and remove late initialization code that is no longer needed. Pstate intialization has moved to early init because it requires a warm reset. Add CPUID setup and disable SMM access to late initialization. Much of this code is leftover from porting from K8. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb 2008-04-22 23:27:53 UTC (rev 3251) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb 2008-04-22 23:32:56 UTC (rev 3252) @@ -37,4 +37,3 @@ driver model_10xxx_init.o object update_microcode.o object apic_timer.o -object pstate.o Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c 2008-04-22 23:27:53 UTC (rev 3251) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c 2008-04-22 23:32:56 UTC (rev 3252) @@ -1,312 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <cpu/x86/tsc.h> - - -static u32 get_vstime(u32 nodeid, u32 slam) -{ - u32 val; - u32 v; - device_t dev; - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - val = pci_read_config32(dev, 0xd8); - - val >>= slam?0:4; - val &= 7; - - switch (val) { - case 4: v = 60; break; - case 5: v = 100; break; - case 6: v = 200; break; - case 7: v = 500; break; - default: - v = (val+1)*10; // in us - } - - return v; -} - -static void udelay_tsc(u32 us) -{ - /* Use TSC to delay because it is fixed, ie. it will not changed with p-states. - * Also, We use the APIC TIMER register is to hold flags for AP init. - */ - u32 dword; - tsc_t tsc, tsc1, tscd; - u32 d = 0x00000200; //800Mhz or 200Mhz or 1.6G or get the NBFID at first - u32 dn = 0x1000000/2; // howmany us need to use hi - - tscd.hi = us/dn; - tscd.lo = (us - tscd.hi * dn) * d; - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if((dword<tsc1.lo) || (dword<tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi+= tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi>tsc1.hi) || ((tsc.hi==tsc1.hi) && (tsc.lo>tsc1.lo))); - -} - -#ifdef __ROMCC__ -void udelay(u32 usecs) -{ - udelay_tsc(usecs); -} -#endif - -static u32 set_vid(u32 newvid, u32 bit_offset, u32 nodeid, u32 coreid) -{ - u32 val; - msr_t msr; - u32 curvid; - u32 slam; - u32 delay; - u32 count = 3; - device_t dev; - - msr = rdmsr(0xc0010071);//status - curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits - - if(newvid == curvid) return curvid; - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - val = pci_read_config32(dev, 0xa0); - - slam = (val >> 29) & 1; - delay = get_vstime(nodeid, slam); - - if(!slam) { - if(curvid>newvid) { - count = (curvid - newvid) * 2; - } else { - count = (newvid - curvid) * 2; - } - } - - while(count-->0) { - if(slam) { - curvid = newvid; - } - else { //ramp - if(curvid>newvid) { - curvid--; - } else { - curvid++; - } - } - - msr = rdmsr(0xc0010070); //control - msr.lo &= ~(0x7f<<bit_offset); - msr.lo |= (curvid<<bit_offset); - wrmsr(0xc0010070, msr); // how about all copys, APIC or PCI conf space? - - udelay_tsc(delay); - - msr = rdmsr(0xc0010071);//status - curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits - - if(curvid == newvid) break; - - } - - return curvid; -} - - -static u32 set_nb_vid(u32 newvid, u32 nodeid, u32 coreid) -{ - return set_vid(newvid, 25, nodeid, coreid); -} - - -static u32 set_core_vid(u32 newvid, u32 nodeid, u32 coreid) -{ - return set_vid(newvid, 9, nodeid, coreid); -} - - -static unsigned set_cof(u32 val, u32 mask, u32 nodeid, u32 coreid) -{ - msr_t msr; - int count = 3; - - val &= mask; - - // FIXME: What is count for? Why 3 times? What about node and core id? - while(count-- > 0) { - - msr = rdmsr(0xc0010071); - msr.lo &= mask; - if(msr.lo == val) break; - - msr = rdmsr(0xc0010070); - msr.lo &= ~(mask); - msr.lo |= val; - wrmsr(0xc0010070, msr); - } - - return msr.lo; -} - -static u32 set_core_cof(u32 fid, u32 did, u32 nodeid, u32 coreid) -{ - u32 val; - u32 mask; - - mask = (7<<6) | 0x3f; - val = ((did & 7)<<6) | (fid & 0x3f); - - return set_cof(val, mask, nodeid, coreid); - -} - - -static u32 set_nb_cof(u32 did, u32 nodeid, u32 coreid) // fid need warmreset -{ - u32 val; - u32 mask; - - mask = 1<<22; - val = (did & 1)<<22; - - return set_cof(val, mask, nodeid, coreid); - -} - - -/* set vid and cof for core and nb after warm reset is not started by BIOS */ -static void set_core_nb_max_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // P0 -{ - msr_t msr; - u32 val; - u32 vid; - u32 mask; - u32 did; - device_t dev; - - msr = rdmsr(0xc0010064); - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - val = pci_read_config32(dev, 0xa0); - if((val>>8) & 1) { // PVI - vid = (msr.lo >> 25) & 0x7f; - } else { //SVI - vid = (msr.lo >> 9) & 0x7f; - } - set_core_vid(vid, nodeid, coreid); - - mask = (0x7<<6) | 0x3f; - val = msr.lo & mask; - set_cof(val, mask, nodeid, coreid); - - //set nb cof and vid - did = (msr.lo >> 22) & 1; - vid = (msr.lo >> 25) & 0x7f; - if(did) { - set_nb_cof(did, nodeid, coreid); - set_nb_vid(vid, nodeid, coreid); - } else { - set_nb_vid(vid, nodeid, coreid); - set_nb_cof(did, nodeid, coreid); - } - - //set the p state - msr.hi = 0; - msr.lo = 0; - wrmsr(0xc0010062, msr); - -} - - -/* set vid and cof for core and nb after warm reset is not started by BIOS */ -static void set_core_nb_min_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // Px -{ - msr_t msr; - u32 val; - u32 vid; - u32 mask; - u32 did; - u32 pstate; - device_t dev; - -#if defined(__ROMCC__) - dev = NODE_PCI(nodeid, 3); -#else - dev = get_node_pci(nodeid, 3); -#endif - - - val = pci_read_config32(dev, 0xdc); //PstateMaxVal - - pstate = (val >> 8) & 0x7; - - msr = rdmsr(0xc0010064 + pstate); - - mask = (7<<6) | 0x3f; - val = msr.lo & mask; - set_cof(val, mask, nodeid, coreid); - - val = pci_read_config32(dev, 0xa0); - if((val>>8) & 1) { // PVI - vid = (msr.lo>>25) & 0x7f; - } else { //SVI - vid = (msr.lo>>9) & 0x7f; - } - set_core_vid(vid, nodeid, coreid); - - //set nb cof and vid - did = (msr.lo >> 22) & 1; - vid = (msr.lo >> 25) & 0x7f; - if(did) { - set_nb_cof(did, nodeid, coreid); - set_nb_vid(vid, nodeid, coreid); - } else { - set_nb_vid(vid, nodeid, coreid); - set_nb_cof(did, nodeid, coreid); - } - - //set the p state - msr.hi = 0; - msr.lo = pstate; - wrmsr(0xc0010062, msr); -} Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c 2008-04-22 23:27:53 UTC (rev 3251) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c 2008-04-22 23:32:56 UTC (rev 3252) @@ -35,28 +35,13 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/mem.h> - #include <cpu/amd/quadcore.h> - #include <cpu/amd/model_10xxx_msr.h> -extern void prep_pstates_all(void); -extern void init_pstates(device_t dev, u32 nodeid, u32 coreid); extern device_t get_node_pci(u32 nodeid, u32 fn); -void cpus_ready_for_init(void) -{ - prep_pstates_all(); -#if MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); - // wait for ap memory to trained - wait_all_core0_mem_trained(sysinfox); -#endif -} - - #define MCI_STATUS 0x401 @@ -82,304 +67,18 @@ } -#define MTRR_COUNT 8 -#define ZERO_CHUNK_KB 0x800UL /* 2M */ -#define TOLM_KB 0x400000UL - -struct mtrr { - msr_t base; - msr_t mask; -}; - - -struct mtrr_state { - struct mtrr mtrrs[MTRR_COUNT]; - msr_t top_mem, top_mem2; - msr_t def_type; -}; - - -static void save_mtrr_state(struct mtrr_state *state) -{ - int i; - for(i = 0; i < MTRR_COUNT; i++) { - state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i)); - state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i)); - } - state->top_mem = rdmsr(TOP_MEM); - state->top_mem2 = rdmsr(TOP_MEM2); - state->def_type = rdmsr(MTRRdefType_MSR); -} - - -static void restore_mtrr_state(struct mtrr_state *state) -{ - int i; - disable_cache(); - - for(i = 0; i < MTRR_COUNT; i++) { - wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base); - wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask); - } - wrmsr(TOP_MEM, state->top_mem); - wrmsr(TOP_MEM2, state->top_mem2); - wrmsr(MTRRdefType_MSR, state->def_type); - - enable_cache(); -} - - -#if 0 -static void print_mtrr_state(struct mtrr_state *state) -{ - int i; - for(i = 0; i < MTRR_COUNT; i++) { - printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n", - i, - state->mtrrs[i].base.hi, state->mtrrs[i].base.lo, - state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo); - } - printk_debug("top_mem: %08x%08x\n", - state->top_mem.hi, state->top_mem.lo); - printk_debug("top_mem2: %08x%08x\n", - state->top_mem2.hi, state->top_mem2.lo); - printk_debug("def_type: %08x%08x\n", - state->def_type.hi, state->def_type.lo); -} -#endif - - -static void set_init_ecc_mtrrs(void) -{ - msr_t msr; - int i; - disable_cache(); - - /* First clear all of the msrs to be safe */ - for(i = 0; i < MTRR_COUNT; i++) { - msr_t zero; - zero.lo = zero.hi = 0; - wrmsr(MTRRphysBase_MSR(i), zero); - wrmsr(MTRRphysMask_MSR(i), zero); - } - - /* Write back cache the first 1MB */ - msr.hi = 0x00000000; - msr.lo = 0x00000000 | MTRR_TYPE_WRBACK; - wrmsr(MTRRphysBase_MSR(0), msr); - msr.hi = 0x000000ff; - msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800; - wrmsr(MTRRphysMask_MSR(0), msr); - - /* Set the default type to write combining */ - msr.hi = 0x00000000; - msr.lo = 0xc00 | MTRR_TYPE_WRCOMB; - wrmsr(MTRRdefType_MSR, msr); - - /* Set TOP_MEM to 4G */ - msr.hi = 0x00000001; - msr.lo = 0x00000000; - wrmsr(TOP_MEM, msr); - - enable_cache(); -} - - -static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state) -{ - unsigned long limitk; - unsigned long size; - void *addr; - - /* Report every 64M */ - if ((basek % (64*1024)) == 0) { - - /* Restore the normal state */ - map_2M_page(0); - restore_mtrr_state(mtrr_state); - enable_lapic(); - - /* Print a status message */ - printk_debug("%c", (basek >= TOLM_KB)?'+':'-'); - - /* Return to the initialization state */ - set_init_ecc_mtrrs(); - disable_lapic(); - - } - - limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1); - - size = (limitk - basek) << 10; - addr = map_2M_page(basek >> 11); - if (addr == MAPPING_ERROR) { - printk_err("Cannot map page: %x\n", basek >> 11); - return; - } - - /* clear memory 2M (limitk - basek) */ - addr = (void *)(((u32)addr) | ((basek & 0x7ff) << 10)); - clear_memory(addr, size); -} - - -static void init_ecc_memory(u32 node_id) -{ - unsigned long startk, begink, endk; - unsigned long hole_startk = 0; - unsigned long basek; - struct mtrr_state mtrr_state; - - device_t f1_dev, f2_dev, f3_dev; - int enable_scrubbing; - u32 dcl; - - f1_dev = get_node_pci(node_id, 1); - - if (!f1_dev) { - die("Cannot find cpu function 1\n"); - } - f2_dev = get_node_pci(node_id, 2); - if (!f2_dev) { - die("Cannot find cpu function 2\n"); - } - f3_dev = get_node_pci(node_id, 3); - if (!f3_dev) { - die("Cannot find cpu function 3\n"); - } - - /* See if we scrubbing should be enabled */ - enable_scrubbing = 1; - get_option(&enable_scrubbing, "hw_scrubber"); - - /* Enable cache scrubbing at the lowest possible rate */ - if (enable_scrubbing) { - pci_write_config32(f3_dev, DRAM_SCRUB_RATE_CTRL, - (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0)); - } else { - pci_write_config32(f3_dev, DRAM_SCRUB_RATE_CTRL, - (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0)); - printk_debug("Scrubbing Disabled\n"); - } - - - /* If ecc support is not enabled don't touch memory */ - dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW); - if (!(dcl & DCL_DimmEccEn)) { - printk_debug("ECC Disabled\n"); - return; - } - - startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2; - endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; - -#if HW_MEM_HOLE_SIZEK != 0 - u32 val; - val = pci_read_config32(f1_dev, 0xf0); - if(val & 1) { - hole_startk = ((val & (0xff<<24)) >> 10); - } -#endif - - - /* Don't start too early */ - begink = startk; - if (begink < CONFIG_LB_MEM_TOPK) { - begink = CONFIG_LB_MEM_TOPK; - } - - printk_debug("Clearing memory %uK - %uK: ", begink, endk); - - /* Save the normal state */ - save_mtrr_state(&mtrr_state); - - /* Switch to the init ecc state */ - set_init_ecc_mtrrs(); - disable_lapic(); - - /* Walk through 2M chunks and zero them */ -#if HW_MEM_HOLE_SIZEK != 0 - /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */ - if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) { - for(basek = begink; basek < hole_startk; - basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) - { - clear_2M_ram(basek, &mtrr_state); - } - for(basek = 4*1024*1024; basek < endk; - basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) - { - clear_2M_ram(basek, &mtrr_state); - } - } else -#endif - for(basek = begink; basek < endk; - basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) { - clear_2M_ram(basek, &mtrr_state); - } - - - /* Restore the normal state */ - map_2M_page(0); - restore_mtrr_state(&mtrr_state); - enable_lapic(); - - /* Set the scrub base address registers */ - pci_write_config32(f3_dev, DRAM_SCRUB_ADDR_LOW, startk << 10); - pci_write_config32(f3_dev, DRAM_SCRUB_ADDR_HIGH, startk >> 22); - - /* Enable the scrubber? */ - if (enable_scrubbing) { - /* Enable scrubbing at the lowest possible rate */ - pci_write_config32(f3_dev, DRAM_SCRUB_RATE_CTRL, - (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0)); - } - - printk_debug(" done\n"); -} - - -static inline void fam10_errata(void) -{ - msr_t msr; - /* FIXME: Is doing errata here too late? */ - - /* 298 : FIXME: Fixed in B3/C1 */ -/* msr = rdmsr(0xC0010015); - msr.lo |= 1 << 3; - wrmsr(0xC0010015, msr); - - msr = rdmsr(0xC0010023); - msr.lo |= 1 << 1; - wrmsr(0xC0010023, msr); -*/ -} - -static void smash1Gpages(void) -{ - msr_t msr; - - /* 1G pages are smashed and installed in the TLB as 2M pages. - BIOS must set this bit for revision B. */ - /* FIXME: What about RevC? */ - - msr = rdmsr(0xC001102A); - msr.lo |= 1 << 29; - wrmsr(0xC001102A, msr); - -} - - - void model_10xxx_init(device_t dev) { - unsigned long i; + u8 i; msr_t msr; struct node_core_id id; #if CONFIG_LOGICAL_CPUS == 1 - unsigned siblings; + u32 siblings; #endif + id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ + printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); + /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); @@ -394,13 +93,14 @@ wrmsr(MCI_STATUS + (i * 4),msr); } - fam10_errata(); enable_cache(); /* Enable the local cpu apics */ setup_lapic(); + /* FIXME: Update CPUID name strings here */ + #if CONFIG_LOGICAL_CPUS == 1 siblings = cpuid_ecx(0x80000008) & 0xff; @@ -409,34 +109,23 @@ msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR); - msr.lo = (siblings+1)<<16; - wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr); - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1<<(33-32); + msr.hi |= 1 << (33-32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk_debug("siblings = %02d, ", siblings); #endif - id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46-32)); + wrmsr(NB_CFG_MSR, msr); - printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - init_pstates(dev, id.nodeid, id.coreid); // is it a good place? some cores are clearing their ram - - /* Is this a bad location? In particular can another node prefecth - * data from this node before we have initialized it? - */ - if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0 - -#if CONFIG_LOGICAL_CPUS==1 - /* Start up my cpu siblings */ -// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan -#endif - - smash1Gpages(); } static struct device_operations cpu_dev_ops = { Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c 2008-04-22 23:27:53 UTC (rev 3251) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c 2008-04-22 23:32:56 UTC (rev 3252) @@ -1,456 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/pae.h> -#include <pc80/mc146818rtc.h> -#include <cpu/x86/lapic.h> - -#include "../../../northbridge/amd/amdfam10/amdfam10.h" - -#include <cpu/amd/model_10xxx_rev.h> -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/mem.h> - -#include <cpu/amd/quadcore.h> - -#include <cpu/amd/model_10xxx_msr.h> -#include <cpu/amd/amdfam10_sysconf.h> - -extern device_t get_node_pci(u32 nodeid, u32 fn); - -#include "fidvid_common.c" - -#define PSTATES_DEBUG 0 - - - -static void inline dump_msr_pstates(u32 nodes) -{ -#if PSTATES_DEBUG==1 - int i, j; - for(j=0; j<5; j++) { - printk_debug("P%d:", j); - for(i=0;i<nodes;i++) { - printk_debug(" [%08x %08x] ", sysconf.msr_pstate[i*5+j].hi, sysconf.msr_pstate[i*5+j].lo); - } - printk_debug("\n"); - } -#endif -} - - -static void inline dump_p(const char *p_c, u32 nodes, u32 *p) -{ -#if PSTATES_DEBUG==1 - int i, j; - printk_debug(p_c); - printk_debug("p:"); - for(i=0;i<nodes;i++) { - printk_debug(" %d ", p[i]); - } - printk_debug("\n"); - -#endif -} - - -//according the pstate and make it work conformed to mixed conf system -static u32 get_pwrvalue(u32 val) -{ - u32 times; - switch((val>>8)&3) { - case 0: times = 1000; break; - case 1: times = 100; break; - case 2: times = 10; break; - default: - //error - times = 1; - } - - return (val & 0xff) * times; - -} - - -static u32 get_powerstep(u32 val) -{ - u32 time; - if(val<4) {time = (4 - val)*100;} - else if(val<8) { time = (9+4-val)*10;} - else { time = (10+8-val) * 5; } - - return time; - -} - - -static u32 get_plllocktime(u32 val) -{ - u32 time; - switch(val) { - case 0: - case 1: - case 2: - case 3: - time = val+1; break; - case 4: time = 8; break; - case 5: time = 16; break; - default: - //erro2 - time = 1; - } - return time; -} - - -static void disable_pstate(u32 nodes, u32 *p) -{ - int i; - - for(i=0;i<nodes; i++) { - sysconf.msr_pstate[i*5+p[i]].hi &= ~(1<<(63-32)); - } -} - - -static void match_pstate(u32 nodes, u32 *p) -{ - int i; - u32 corecof_min, pwrvalue_max, pwrval_max; - u32 enable; - enable = (sysconf.msr_pstate[0*5+p[0]].hi >> 31); - if(!enable) { - disable_pstate(nodes, p); - return; - } - corecof_min = ((sysconf.msr_pstate[0*5+p[0]].lo & 0x3f) + 0x10)>>((sysconf.msr_pstate[0*5+p[0]].lo>>6) & 7); - pwrval_max = sysconf.msr_pstate[0*5+p[0]].hi & 0x3ff; - pwrvalue_max = get_pwrvalue(pwrval_max); - - for(i=1; i<nodes; i++) { - enable = (sysconf.msr_pstate[0*5+p[i]].hi >> 31); - if(!enable) { - disable_pstate(nodes, p); - return; - } - - u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7); - u32 corecof = ((sysconf.msr_pstate[i*5+p[i]].lo & 0x3f) + 0x10)>>coredid; - if(corecof<corecof_min) corecof_min = corecof; - u32 pwrval, pwrvalue; - pwrval = sysconf.msr_pstate[i*5+p[i]].hi & 0x3ff; - pwrvalue = get_pwrvalue(pwrval); - if(pwrvalue>pwrvalue_max) { - pwrvalue_max = pwrvalue; - pwrval_max = pwrval; - } - } - - for(i=0; i<nodes; i++) { - u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7); - u32 corefid = (corecof_min<<coredid); - while(corefid<0x10) { - coredid++; - corefid = (corecof_min<<coredid); - } - sysconf.msr_pstate[i*5+p[i]].lo &= ~(0x1ff); - sysconf.msr_pstate[i*5+p[i]].lo |= (corefid - 0x10) | (coredid << 6); - sysconf.msr_pstate[i*5+p[i]].hi &= ~(0x3ff); - sysconf.msr_pstate[i*5+p[i]].hi |= pwrval_max; - } -} - - -static void match_pstates(u32 nodes, u32 *p, u32 *px) -{ - int i; - int j; - u32 p_int[NODE_NUMS]; - - int jj=1; - u32 end = 0; - for(i=0;i<nodes; i++) { - p_int[i] = px[i]; - } - while(1){ - for(i=0;i<nodes; i++) { - if(px[i]<=(p[i]+jj)) { - end = 1; - break; - } - } - if(!end) { - for(i=0; i<nodes; i++) { - p_int[i] = px[i] - jj; - } - match_pstate(nodes, p_int); - dump_p("P int\n", nodes, p_int); - jj++; - } - else { - for(i=0;i<nodes; i++) { - for(j=p[i]+1; j<p_int[i]; j++) { - sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); - } - } - break; - } - } -} - - -void prep_pstates_all(void) -{ - device_t f3_dev[NODE_NUMS], f4_dev[NODE_NUMS]; - u32 p[NODE_NUMS]; - u32 p_htc[NODE_NUMS]; - u32 p_lowest[NODE_NUMS]; - u32 htc_cap = 1; - u32 lowest_htc_equal = 0; - - u32 nodes = sysconf.nodes; - int i; - int j; - u32 val; - u32 nbdid; - u32 nbvid0; - u32 nbvid1; - - for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage... - f3_dev[i] = get_node_pci(i, 3); - f4_dev[i] = get_node_pci(i, 4); - } - - for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage... - val = pci_read_config32(f4_dev[i], 0x1f4); - nbvid0 = val & 0x3f; - nbvid1 = (val>>7) & 0x3f; - for(j=0; j<5; j++) { - val = pci_read_config32(f4_dev[i], 0x1e0 + (j<<2)); - nbdid = ((val>>16) & 1); - sysconf.msr_pstate[i*5+j].lo = (val & 0xffff) | (nbdid<<22) | ((nbdid?nbvid1:nbvid0)<<25); - sysconf.msr_pstate[i*5+j].hi = (((val>>17) & 0x3ff) << (32-32)) | (((val>>27) & 1)<<(63-32)); - } - } - - dump_msr_pstates(nodes); - - sysconf.needs_update_pstate_msrs = 0; // normal case for all sockets are installed same conf CPU - - for(i=1; (i<nodes) && (!sysconf.needs_update_pstate_msrs); i++) { - for(j=0; j<5; j++) { - if((sysconf.msr_pstate[i*5+j].lo != sysconf.msr_pstate[0*5+j].lo) || (sysconf.msr_pstate[i*5+j].hi != sysconf.msr_pstate[0*5+j].hi)) { - sysconf.needs_update_pstate_msrs = 1; - break; - } - } - } - - if(sysconf.needs_update_pstate_msrs) { - - // update msr_pstate for mixed conf - - //P0 - /* Match P0 cpu cof for all cpu cores to the lowest P0 cpu cof value in the coherent fabric, and match P0 power for all cpu cores to the highest P0 power value */ - for(i=0;i<nodes; i++) p[i] = 0; - match_pstate(nodes, p); - dump_p("P0\n", nodes, p); - dump_msr_pstates(nodes); - - - //p_htc - for(i=0;i<nodes; i++) { - val = pci_read_config32(f3_dev[i], 0xe8); //htc cap - if(!(val & (1<<10))) { - htc_cap = 0; - break; - } - - //HtcPstateLimit - val = pci_read_config32(f3_dev[i], 0x64); - p_htc[i] = (((val>>28) & 7)); - if(p_htc[i] == 0) { - val |= 1<<28; - pci_write_config32(f3_dev[i], 0x64, val); - val = pci_read_config32(f3_dev[i], 0x68); //stc - val &= ~(7<<28); - val |= (1<<28); - pci_write_config32(f3_dev[i], 0x68, val); - - p_htc[i] = 1; - } - } - if(htc_cap) { - match_pstate(nodes, p_htc); - - dump_p("P_htc\n", nodes, p_htc); - dump_msr_pstates(nodes); - } - - //p_lowest - for(i=0;i<nodes; i++) { - p_lowest[i] = 0; - for(j=1; j<5; j++) { - if(sysconf.msr_pstate[i*5+j].hi & (1<<(63-32))) { - p_lowest[i] = j; - } - } - // PstateMaxVal - val = pci_read_config32(f3_dev[i], 0xdc); - if(p_lowest[i]>((val>>8) & 7)) { - val &= ~(7<<8); - val |= (p_lowest[i])<<8; - pci_write_config32(f3_dev[i], 0xdc, val); - } - else { - p_lowest[i] = (val>>8) & 7; - } - } - if(htc_cap) { - for(i=0;i<nodes; i++) { - if(p_lowest[i]==p_htc[i]){ - lowest_htc_equal = 1; - break; - } - } - } - if(lowest_htc_equal) { - for(i=0;i<nodes; i++) { - // PstateMaxVal - val = pci_read_config32(f3_dev[i], 0xdc); - val &= ~(7<<8); - val |= p_htc[i]; - pci_write_config32(f3_dev[i], 0xdc, val); - for(j=p_htc[i]+1; j<5; j++) { - sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); - } - } - } else { - match_pstate(nodes, p_lowest); - for(i=0; i<nodes; i++) { - for(j=p_lowest[i]+1; j<5; j++) { - sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32)); - } - } - - } - - dump_p("Px\n", nodes, p_lowest); - dump_msr_pstates(nodes); - - - if(htc_cap) { - //p_up_int - match_pstates(nodes, p, p_htc); - - dump_msr_pstates(nodes); - - //p_lower_int - match_pstates(nodes, p_htc, p_lowest); - } else { - match_pstates(nodes, p, p_lowest); - } - - dump_msr_pstates(nodes); - - } - - // fill data into p_state - for(i=0; i<nodes; i++) { - sysconf.p_state_num = 0; - u32 corefid_equal = 1; - u32 corefid; - corefid = (sysconf.msr_pstate[i*5+0].lo & 0x3f); - for(j=1; j<5; j++) { - msr_t *msr_pstate; - msr_pstate = &(sysconf.msr_pstate[i*5+j]); - if(!(msr_pstate->hi & (1<<(63-32)) )) continue; - if((msr_pstate->lo & 0x3f) != corefid) { - corefid_equal = 0; - break; - } - } - for(j=0; j<5; j++) { - struct p_state_t *p_state; - msr_t *msr_pstate; - msr_pstate = &sysconf.msr_pstate[i*5+j]; - if(!(msr_pstate->hi & (1<<(63-32)) )) continue; - p_state = &sysconf.p_state[i*5+sysconf.p_state_num]; - u32 coredid = ((msr_pstate->lo>>6) & 7); - u32 corecof = ((msr_pstate->lo & 0x3f) + 0x10)>>coredid; - p_state->corefreq = corecof; - - u32 pwrval, pwrvalue; - pwrval = msr_pstate->hi & 0x3ff; - pwrvalue = get_pwrvalue(pwrval); - p_state->power = pwrvalue; - - u32 lat; - val = pci_read_config32(f3_dev[i], 0xd4); - lat = 15 * (get_powerstep((val>>24)& 0xf)+get_powerstep((val>>20)& 0xf)) /1000; - if(!corefid_equal) { - val = pci_read_config32(f3_dev[i], 0xa0); - lat += get_plllocktime((val >> 11 ) & 7); - } - p_state->transition_lat = lat; - p_state->busmaster_lat = lat; - - p_state->control = j; - p_state->status = j; - - sysconf.p_state_num++; - } - // don't need look at other nodes - if(!sysconf.p_state_num) break; - } -} - - -//it will update pstates info from ram into MSR -void init_pstates(device_t dev, u32 nodeid, u32 coreid) -{ - int j; - msr_t msr; - - if(sysconf.needs_update_pstate_msrs) { - for(j=0; j < 5; j++) { - wrmsr(0xC0010064 + j, sysconf.msr_pstate[nodeid * 5 + j]); - } - } - - /* Set TSC Freq Select: TSC increments at the rate of the core P-state 0 */ - msr = rdmsr(0xC0010015); - msr.lo |= 1 << 24; - wrmsr(0xC0010015, msr); - - // Enter the state P0 - //FIXME I don't think that this works correctly. May depend on early fid/vid setup. - if(sysconf.p_state_num) - set_core_nb_max_pstate_after_other_warm_reset(nodeid, coreid); - -}

1 0

[patch][v2][3/4] Family 10
by Marc Jones 23 Apr '08

23 Apr '08

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Find matching settings for each CPUs FID, VID, and P-state registers and initialize them. Supports single and split plane systems. Set P0 on all cores for best performance. All APs will be in hlt(C1). The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore. Signed-off-by: Marc Jones (marc.jones(a)amd.com) Index: coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/fidvid.c 2008-04-16 10:19:39.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c 2008-04-16 10:36:34.000000000 -0600 @@ -18,6 +18,7 @@ */ #if FAM10_SET_FIDVID == 1 +#include "../../../northbridge/amd/amdht/AsPsDefs.h" #define FAM10_SET_FIDVID_DEBUG 1 @@ -46,6 +47,11 @@ } +struct fidvid_st { + u32 common_fid; +}; + + static void enable_fid_change(u8 fid) { u32 dword; @@ -53,7 +59,7 @@ device_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = get_nodes(); for(i = 0; i < nodes; i++) { dev = NODE_PCI(i,3); @@ -66,124 +72,293 @@ } } + +static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +{ + u8 pviModeFlag; + u8 highVoltageVid, lowVoltageVid, bValue; + u16 minimumSlamTime; + u16 vSlamTimes[7]={1000,2000,3000,4000,6000,10000,20000}; /* Reg settings scaled by 100 */ + u32 dtemp; + msr_t msr; + + /* This function calculates the VsSlamTime using the range of possible + * voltages instead of a hardcoded 200us. + * Note:This function is called from setFidVidRegs and setUserPs after + * programming a custom Pstate. + */ + + /* Calculate Slam Time + * Vslam = 0.4us/mV * Vp0 - (lowest out of Vpmin or Valt) + * In our case, we will scale the values by 100 to avoid + * decimals. + */ + + + + /* Determine if this is a PVI or SVI system */ + dtemp = pci_read_config32(dev, 0xA0); + + if( dtemp & PVI_MODE ) + pviModeFlag = 1; + else + pviModeFlag = 0; + + /* Get P0's voltage */ + msr = rdmsr(0xC0010064); + highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); + + /* If SVI, we only care about CPU VID. + * If PVI, determine the higher voltage b/t NB and CPU + */ + if (pviModeFlag) { + bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); + if( highVoltageVid > bValue ) + highVoltageVid = bValue; + } + + /* Get Pmin's index */ + msr = rdmsr(0xC0010061); + bValue = (u8) ((msr.lo >> PS_CUR_LIM_SHFT) & BIT_MASK_3); + + /* Get Pmin's VID */ + msr = rdmsr(0xC0010064 + bValue); + lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); + + /* If SVI, we only care about CPU VID. + * If PVI, determine the higher voltage b/t NB and CPU + */ + if (pviModeFlag) { + bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); + if( lowVoltageVid > bValue ) + lowVoltageVid = bValue; + } + + /* Get AltVID */ + dtemp = pci_read_config32(dev, 0xDC); + bValue = (u8) (dtemp & BIT_MASK_7); + + /* Use the VID with the lowest voltage (higher VID) */ + if( lowVoltageVid < bValue ) + lowVoltageVid = bValue; + + /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */ + if (lowVoltageVid > 0x7C) { + lowVoltageVid = 0x7C; + if(highVoltageVid > 0x7C) + highVoltageVid = 0x7C; + } + + bValue = (u8) (lowVoltageVid - highVoltageVid); + + /* Each Vid increment is 12.5 mV. The minimum slam time is: + * vidCodeDelta * 12.5mV * 0.4us/mV + * Scale by 100 to avoid decimals. + */ + minimumSlamTime = bValue * (125 * 4); + + /* Now round up to nearest register setting. + * Note that if we don't find a value, we + * will fall through to a value of 7 + */ + for(bValue=0; bValue < 7; bValue++) { + if(minimumSlamTime <= vSlamTimes[bValue]) + break; + } + + /* Apply the value */ + dtemp = pci_read_config32(dev, 0xD8); + dtemp &= VSSLAM_MASK; + dtemp |= bValue; + pci_write_config32(dev, 0xd8, dtemp); +} + + static void prep_fid_change(void) { - u32 dword; + u32 dword, dtemp; u32 nodes; device_t dev; int i; /* This needs to be run before any Pstate changes are requested */ - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = get_nodes(); for(i = 0; i < nodes; i++) { - printk_debug("Node:%02x \n", i); + printk_debug("Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i,3); - dword = pci_read_config32(dev, 0xa0); - dword &= ~(1<<29); - dword |= ((~dword >> 8) & 1) << 29; // SlamVidMode is the inverse to the PviMode - dword |= PLLLOCK_DFT_L; /* Force per BKDG */ - pci_write_config32(dev, 0xa0, dword); - printk_debug(" F3xA0: %08x \n", dword); - dword = pci_read_config32(dev, 0xd8); - dword &= ~0x77; - dword |= (1<<4) | 6; // VSRampTime, and VSSlamTime - dword |= 3 << 24; // ReConDel set to 3 per BKDG + dword &= VSRAMP_MASK; + dword |= VSRAMP_VALUE; pci_write_config32(dev, 0xd8, dword); - printk_debug(" F3xD8: %08x \n", dword); - dword = pci_read_config32(dev, 0xd4); - dword &= 0x1F; - dword |= 0xC331AF00; // per BKDG - pci_write_config32(dev, 0xd4, dword); - printk_debug(" F3xD4: %08x \n", dword); + /* Figure out the value for VsSlamTime and program it */ + recalculateVsSlamTimeSettingOnCorePre(dev); + + /* Program fields in Clock Power/Control register0 (F3xD4) */ + /* set F3xD4 Clock Power/Timing Control 0 Register + * NbClkDidApplyAll=1b + * NbClkDid=100b + * PowerStepUp= "platform dependent" + * PowerStepDown= "platform dependent" + * LinkPllLink=01b + * ClkRampHystSel=HW default + */ + /* check platform type */ + if (!(get_platform_type() & AMD_PTYPE_SVR)) { + /* For non-server platform + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns + */ + dword = pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | + LNK_PLL_LOCK; /* per BKDG */ + pci_write_config32(dev, 0xd4, dword); + } else { + dword = pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + /* get number of cores for PowerStepUp & PowerStepDown in server + 1 core - 400nS - 0000b + 2 cores - 200nS - 0010b + 3 cores - 133nS -> 100nS - 0011b + 4 cores - 100nS - 0011b + */ + switch(get_core_num_in_bsp(i)) + { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } + dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; + pci_write_config32(dev, 0xd4, dword); + } + + /* check PVI/SVI */ + dword = pci_read_config32(dev, 0xA0); + if(dword & PVI_MODE) { /* PVI */ + /* set slamVidMode to 0 for PVI */ + dword &= VID_SLAM_OFF | PLLLOCK_OFF; + dword |= PLLLOCK_DFT_L; + pci_write_config32(dev, 0xA0, dword); + } else { /* SVI */ + /* set slamVidMode to 1 for SVI */ + dword &= PLLLOCK_OFF; + dword |= PLLLOCK_DFT_L | VID_SLAM_ON; + pci_write_config32(dev, 0xA0, dword); + + dtemp = dword; + + /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */ + dword = pci_read_config32(dev, 0xD8); + + if( dtemp & DUAL_VDD_BIT) + dword |= PWR_PLN_ON; + else + dword &= PWR_PLN_OFF; + pci_write_config32(dev, 0xD8, dword); + } - dword = pci_read_config32(dev, 0xdc); - dword |= 0x5 << 12; // NbsynPtrAdj set to 0x5 per BKDG (needs reset) + /* Note the following settings are additional from the ported + * function setFidVidRegs() + */ + dword = pci_read_config32(dev, 0xDc); + dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); - printk_debug(" F3xDC: %08x \n", dword); - // Rev B settings - FIXME: support other revs. + /* Rev B settings - FIXME: support other revs. */ dword = 0xA0E641E6; pci_write_config32(dev, 0x84, dword); - printk_debug(" F3x84: %08x \n", dword); dword = 0xE600A681; pci_write_config32(dev, 0x80, dword); + + dword = pci_read_config32(dev, 0x80); printk_debug(" F3x80: %08x \n", dword); + dword = pci_read_config32(dev, 0x84); + printk_debug(" F3x84: %08x \n", dword); + dword = pci_read_config32(dev, 0xD4); + printk_debug(" F3xD4: %08x \n", dword); + dword = pci_read_config32(dev, 0xD8); + printk_debug(" F3xD8: %08x \n", dword); + dword = pci_read_config32(dev, 0xDC); + printk_debug(" F3xDC: %08x \n", dword); + } } -#include "fidvid_common.c" +static void UpdateSinglePlaneNbVid(void) +{ + u32 nbVid, cpuVid; + u8 i; + msr_t msr; + /* copy higher voltage (lower VID) of NBVID & CPUVID to both */ + for (i = 0; i < 5; i++) { + msr = rdmsr(PS_REG_BASE + i); + nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT; + cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT; + + if( nbVid != cpuVid ) { + if(nbVid > cpuVid) + nbVid = cpuVid; + + msr.lo = msr.lo & PS_BOTH_VID_OFF; + msr.lo = msr.lo | (u32)((nbVid) << PS_NB_VID_SHFT); + msr.lo = msr.lo | (u32)((nbVid) << PS_CPU_VID_SHFT); + wrmsr(PS_REG_BASE + i, msr); + } + } +} -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) -{ +static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid) +{ msr_t msr; - device_t dev; - u8 vid_max; - u8 fid_max; u8 startup_pstate; - u8 nb_cof_vid_update; - u8 pvimode; - u32 reg1fc; - u32 dword; - u32 send; - - printk_debug("FIDVID on AP: %02x\n", apicid); - /* Only support single plane system at this time. */ - /* Steps 1-6 of BIOS NB COF and VID Configuration - * for Single-Plane PVI Systems + /* This function sets NbVid before the warm reset. + * Get StartupPstate from MSRC001_0071. + * Read Pstate register pionted by [StartupPstate]. + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. */ - dev = NODE_PCI(nodeid,3); - reg1fc = pci_read_config32(dev, 0x1FC); - nb_cof_vid_update = reg1fc & 1; - if (nb_cof_vid_update) { - /* Get fused settings */ - dword = pci_read_config32(dev, 0xa0); - pvimode = (dword >> 8) & 1; - - vid_max = (reg1fc >> 7) & 0x7F; // per node - fid_max = (reg1fc >> 2) & 0x1F; // per system - - if (pvimode) { - /* FIXME: support daul plane mode */ - die("PVImode not supported\n"); - /* fidmax = vidmax - (reg1fc >> 17) & 0x1F; - fidmax = fidmax + (reg1fc >> 14) & 0x03; - */ - } - - } else { - /* Use current values */ - msr = rdmsr(0xc0010071); - fid_max = ((msr.hi >> (59-32)) & 0x1f); //max nb fid - vid_max = ((msr.hi >> (35-32)) & 0x7f); //max vid - } - /* Note this is the single plane setup. Need to add dual plane path */ msr = rdmsr(0xc0010071); startup_pstate = (msr.hi >> (32-32)) & 0x07; - /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0. - Then transition to P1 for corex and P0 for core0. */ + * Then transition to P1 for corex and P0 for core0. + * These setting will be cleared by the warm reset + */ msr = rdmsr(0xC0010064 + startup_pstate); wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr); msr.lo &= ~0xFE000000; // clear nbvid - msr.lo |= vid_max << 25; + msr.lo |= newNbVid << 25; wrmsr(0xC0010064, msr); + UpdateSinglePlaneNbVid(); + // Transition to P1 for all APs and P0 for core0. msr = rdmsr(0xC0010062); msr.lo = (msr.lo & ~0x07) | 1; @@ -202,7 +377,164 @@ msr = rdmsr(0xC0010063); } while (msr.lo != 0); } +} + + +static void coreDelay (void) +{ + u32 saved; + u32 hi, lo, msr; + u32 cycles; + + /* delay ~40us + This seems like a hack to me... + It would be nice to have a central delay function. */ + + cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */ + + msr = 0x10; /* TSC */ + _RDMSR(msr, &lo, &hi); + saved = lo; + do { + _RDMSR(msr, &lo, &hi); + } while (lo - saved < cycles ); +} + +static void transitionVid(u32 targetVid, u8 dev, u8 isNb) +{ + u32 currentVid, dtemp; + msr_t msr; + u8 vsTimecode; + u16 timeTable[8]={10, 20, 30, 40, 60, 100, 200, 500}; + int vsTime; + + /* This function steps or slam the Nb VID to the target VID. + * It uses VSRampTime for [SlamVidMode]=0 ([PviMode]=1) + * or VSSlamTime for [SlamVidMode]=1 ([PviMode]=0)to time period. + */ + + /* get the current VID */ + msr = rdmsr(0xC0010071); + if(isNb) + currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7; + else + currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7; + + /* Read MSRC001_0070 COFVID Control Register */ + msr = rdmsr(0xC0010070); + + /* check PVI/SPI */ + dtemp = pci_read_config32(dev, 0xA0); + if (dtemp & PVI_MODE) { /* PVI, step VID */ + if (currentVid < targetVid) { + while (currentVid < targetVid) { + currentVid++; + if(isNb) + msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); + else + msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); + wrmsr(0xC0010070, msr); + + /* read F3xD8[VSRampTime] */ + dtemp = pci_read_config32(dev, 0xD8); + vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int) timeTable[vsTimecode]; + do { + coreDelay(); + vsTime -=40; + } while(vsTime > 0); + } + } else if (currentVid > targetVid) { + while (currentVid > targetVid) { + currentVid--; + if(isNb) + msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); + else + msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); + wrmsr(0xC0010070, msr); + + /* read F3xD8[VSRampTime] */ + dtemp = pci_read_config32(dev, 0xD8); + vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int) timeTable[vsTimecode]; + do { + coreDelay(); + vsTime -=40; + } while(vsTime > 0); + } + } + } else { /* SVI, slam VID */ + if(isNb) + msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS); + else + msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS); + wrmsr(0xC0010070, msr); + + /* read F3xD8[VSRampTime] */ + dtemp = pci_read_config32(dev, 0xD8); + vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int) timeTable[vsTimecode]; + do { + coreDelay(); + vsTime -=40; + } while(vsTime > 0); + } +} + + +static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) +{ + device_t dev; + u32 vid_max; + u32 fid_max; + u8 nb_cof_vid_update; + u8 pvimode; + u32 reg1fc; + u32 send; + u8 nodes; + u8 i; + + printk_debug("FIDVID on AP: %02x\n", apicid); + + /* Steps 1-6 of BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems. + */ + + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nodes = get_nodes(); + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; + } + } + + dev = NODE_PCI(nodeid,3); + pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; + reg1fc = pci_read_config32(dev, 0x1FC); + + if (nb_cof_vid_update) { + if (pvimode) { + vid_max = (reg1fc >> 7) & 0x7F; + fid_max = (reg1fc >> 2) & 0x1F; + + /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ + fixPsNbVidBeforeWR(vid_max, coreid); + } else { /* SVI */ + vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); + fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7); + transitionVid(vid_max, dev, IS_NB); + } + + /* fid setup is handled by the BSP at the end. */ + + } else { /* ! nb_cof_vid_update */ + /* Use max values */ + if (pvimode) + UpdateSinglePlaneNbVid(); + } send = (nb_cof_vid_update << 16) | (fid_max << 8); send |= (apicid << 24); // ap apicid @@ -232,9 +564,6 @@ return fid_packed; } -struct fidvid_st { - u32 common_fid; -}; static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp ) { @@ -269,44 +598,147 @@ } +static void updateSviPsNbVidAfterWR(u32 newNbVid) +{ + msr_t msr; + u8 i; + + /* This function copies newNbVid to NbVid bits in P-state Registers[4:0] + * for SVI mode. + */ + + for( i = 0; i < 5; i++) { + msr = rdmsr(0xC0010064 + i); + if ((msr.hi >> 31) & 1) { /* PstateEn? */ + msr.lo &= ~(0x7F << 25); + msr.lo |= (newNbVid & 0x7F) << 25; + wrmsr(0xC0010064 + i, msr); + } + } +} + + +static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll) +{ + msr_t msr; + u8 i; + u8 StartupPstate; + + /* This function copies newNbVid to NbVid bits in P-state + * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of + * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in + * P-state Registers[4:0] if its and PstateEn bit =1 in case of + * NbVidUpdatedAll=1. Then transition to StartPstate. + */ + + /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ + for( i = 0; i < 5; i++) { + msr = rdmsr(0xC0010064 + i); + /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ + if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) { + msr.lo &= ~(0x7F << 25); + msr.lo |= (newNbVid & 0x7F) << 25; + wrmsr (0xC0010064 + i, msr); + } + } + + UpdateSinglePlaneNbVid(); + + /* For each core in the system, transition all cores to StartupPstate */ + msr = rdmsr(0xC0010071); + StartupPstate = msr.hi & 0x07; + msr = rdmsr(0xC0010062); + msr.lo = StartupPstate; + wrmsr(0xC0010062, msr); + + /* Wait for StartupPstate to set.*/ + do { + msr = rdmsr(0xC0010063); + } while (msr.lo != StartupPstate); +} + + +static void set_p0(void) +{ + msr_t msr; + + // Transition P0 for calling core. + msr = rdmsr(0xC0010062); + msr.lo = (msr.lo & ~0x07); + wrmsr(0xC0010062, msr); + + /* Wait for P0 to set. */ + do { + msr = rdmsr(0xC0010063); + } while (msr.lo != 0); +} + + +static void finalPstateChange (void) { + /* Enble P0 on all cores for best performance. + * Linux can slow them down later if need be. + * It is safe since they will be in C1 halt + * most of the time anyway. + */ + set_p0(); +} + + static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; device_t dev; u32 reg1fc; - u8 StartupPstate; - u8 nbvid; - int i; + u32 dtemp; + u32 nbvid; + u8 nb_cof_vid_update; + u8 nodes; + u8 NbVidUpdateAll; + u8 i; + u8 pvimode; /* After warm reset finish the fid/vid setup for all cores. */ + + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nodes = get_nodes(); + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; + } + } + dev = NODE_PCI(nodeid,3); + pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; reg1fc = pci_read_config32(dev, 0x1FC); nbvid = (reg1fc >> 7) & 0x7F; + NbVidUpdateAll = (reg1fc >> 1) & 1; - if (reg1fc & 0x02) { // NbVidUpdateAll ? - for( i = 0; i < 5; i++) { - msr = rdmsr(0xC0010064 + i); - if ((msr.hi >> 31) & 1) { // PstateEn? - msr.lo &= ~(0x7F << 25); - msr.lo |= (nbvid & 0x7F) << 25; - } - } - } else { - for( i = 0; i < 5; i++) { - msr = rdmsr(0xC0010064 + i); - if (((msr.hi >> 31) & 1) && (((msr.lo >> 22) & 1) == 0)) { // PstateEn and PDid == 0? - msr.lo &= ~(0x7F << 25); - msr.lo |= (nbvid & 0x7F) << 25; - } + if (nb_cof_vid_update) { + if (pvimode) { + nbvid = (reg1fc >> 7) & 0x7F; + /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ + fixPsNbVidAfterWR(nbvid, NbVidUpdateAll); + } else { /* SVI */ + nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); + updateSviPsNbVidAfterWR(nbvid); } + } else { /* !nb_cof_vid_update */ + if (pvimode) + UpdateSinglePlaneNbVid(); } - - // For each processor in the system, transition all cores to StartupPstate - msr = rdmsr(0xC0010071); - StartupPstate = msr.hi >> (32-32) & 0x03; - msr = rdmsr(0xC0010062); - msr.lo = StartupPstate; - wrmsr(0xC0010062, msr); + dtemp = pci_read_config32(dev, 0xA0); + dtemp &= PLLLOCK_OFF; + dtemp |= PLLLOCK_DFT_L; + pci_write_config32(dev, 0xA0, dtemp); + + finalPstateChange(); + + /* Set TSC to tick at the P0 ndfid rate */ + msr = rdmsr(HWCR); + msr.lo |= 1 << 24; + wrmsr(HWCR, msr); } @@ -334,80 +766,55 @@ u32 i; #endif struct fidvid_st fv; - msr_t msr; device_t dev; - u8 vid_max; - u8 fid_max; - u8 startup_pstate; + u32 vid_max; + u32 fid_max; u8 nb_cof_vid_update; u32 reg1fc; - u32 dword; u8 pvimode; printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid); + /* FIXME: The first half of this function is nearly the same as + * init_fidvid_bsp() and the code could be combined. + */ - /* FIXME: Only support single plane system at this time. */ /* Steps 1-6 of BIOS NB COF and VID Configuration - * for Single-Plane PVI Systems + * for SVI and Single-Plane PVI Systems. */ - dev = NODE_PCI(0,3); // nodeid for the BSP is 0 - reg1fc = pci_read_config32(dev, 0x1FC); - nb_cof_vid_update = reg1fc & 1; - if (nb_cof_vid_update) { - /* Get fused settings */ - dword = pci_read_config32(dev, 0xa0); - pvimode = (dword >> 8) & 1; - - vid_max = (reg1fc >> 7) & 0x7F; // per node - fid_max = (reg1fc >> 2) & 0x1F; // per system - if (pvimode) { - /* FIXME: support daul plane mode */ - die("PVImode not supported\n"); - /* fidmax = vidmax - (reg1fc >> 17) & 0x1F; - fidmax = fidmax + (reg1fc >> 14) & 0x03; - */ + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; } - - } else { - /* Use current values */ - msr = rdmsr(0xc0010071); - fid_max = ((msr.hi >> (59-32)) & 0x1f); //max nb fid - vid_max = ((msr.hi >> (35-32)) & 0x7f); //max vid } - /* Note this is the single plane setup. Need to add dual plane path */ - msr = rdmsr(0xc0010071); - startup_pstate = (msr.hi >> (32-32)) & 0x07; - - - /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0. - Then transition to P1 for corex and P0 for core0. */ - msr = rdmsr(0xC0010064 + startup_pstate); - wrmsr(0xC0010065, msr); - wrmsr(0xC0010064, msr); - - msr.lo &= ~0xFE000000; // clear nbvid - msr.lo |= vid_max << 25; - wrmsr(0xC0010064, msr); + dev = NODE_PCI(0, 3); + pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; + reg1fc = pci_read_config32(dev, 0x1FC); - // Transition to P1 and then P0 for core0. - msr = rdmsr(0xC0010062); - msr.lo = (msr.lo & ~0x07) | 1; - wrmsr(0xC0010062, msr); + if (nb_cof_vid_update) { + if (pvimode) { + vid_max = (reg1fc >> 7) & 0x7F; + fid_max = (reg1fc >> 2) & 0x1F; - // Wait for P1 to set. - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 1); + /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ + fixPsNbVidBeforeWR(vid_max, 0); + } else { /* SVI */ + vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); + fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7); + transitionVid(vid_max, dev, IS_NB); + } - msr.lo = msr.lo & ~0x07; - wrmsr(0xC0010062, msr); - // Wait for P0 to set. - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 0); + /* fid setup is handled by the BSP at the end. */ + } else { /* ! nb_cof_vid_update */ + /* Use max values */ + if (pvimode) + UpdateSinglePlaneNbVid(); + } fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ; print_debug_fv("BSP fid = ", fv.common_fid); @@ -430,7 +837,7 @@ print_debug_fv("common_fid = ", fv.common_fid); - if (fv.common_fid & ~(0xFF << 16)) { // check nb_cof_vid_update + if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */ // Enable the common fid and other settings. enable_fid_change((fv.common_fid >> 8) & 0x1F); @@ -441,15 +848,4 @@ return 0; // No FID/VID changes. Don't reset } -static void set_p0(void) -{ - msr_t msr; - - // Transition P0 for calling core. - msr = rdmsr(0xC0010062); - msr.lo = (msr.lo & ~0x07); - wrmsr(0xC0010062, msr); - - // Don't bother to wait around for the P state to change. -} #endif Index: coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-16 10:19:39.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-16 10:36:34.000000000 -0600 @@ -157,7 +157,10 @@ #define CPTC1 0xd8 /* Clock Power/Timing Control1 Register*/ #define VSRAMP_SLAM_MASK 0xffffff88 /* MaskOff [VSRampTime]&[VSSlamTime] */ #define VSRAMP_SLAM_VALUE 0x16 /* [VSRampTime]=001b&[VSSlamTime]=110b */ +#define VSRAMP_MASK 0xffffff8f /* MaskOff [VSRampTime] */ +#define VSRAMP_VALUE 0x10 /* [VSRampTime]=001b */ #define VS_RAMP_T 4 /* VSRampTime bit position */ +#define VSSLAM_MASK 0xfffffff8 /* MaskOff [VSSlamTime] */ #define PWR_PLN_SHIFT 28 /* PwrPlanes bit shift */ #define PWR_PLN_ON 0x10000000 /* PwrPlanes bit ON */ #define PWR_PLN_OFF 0x0efffffff /* PwrPlanes bit OFF */ Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-16 11:24:39.000000000 -0600 +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-16 10:39:59.000000000 -0600 @@ -229,7 +229,6 @@ { struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; u32 bsp_apicid = 0; u32 val; msr_t msr; @@ -237,7 +236,7 @@ post_code(0x30); if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); //mmconf is inited in init_cpus + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } @@ -288,7 +287,7 @@ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 - // Core0 on each node is configured. Now setup any additional cores. + /* Core0 on each node is configured. Now setup any additional cores. */ printk_debug("start_other_cores()\n"); start_other_cores(); post_code(0x37); @@ -299,7 +298,7 @@ #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("Begin MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -307,36 +306,37 @@ post_code(0x39); - if (warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - needs_reset |= (init_fidvid_bsp(bsp_apicid, sysinfo->nodes) << 31); + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); - set_p0(); // Speed up the BSP! - - // show final fid and vid + /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif - // Reset for HT and FIDVID changes? - if (needs_reset) { - print_info("\tht reset -\n"); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); - //enable cf9 for hard reset + + /* FIXME: Move this to chipset init. + enable cf9 for hard reset */ print_debug("enable_cf9_x()\n"); enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x3C); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ printk_debug("fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D);

2 2

r3251 - in trunk/coreboot-v2/src: cpu/amd/model_10xxx mainboard/amd/serengeti_cheetah_fam10 northbridge/amd/amdht
by svn＠coreboot.org 23 Apr '08

23 Apr '08

Author: mjones Date: 2008-04-23 01:27:53 +0200 (Wed, 23 Apr 2008) New Revision: 3251 Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h Log: Find matching settings for each CPUs FID, VID, and P-state registers and initialize them. Supports single and split plane systems. Set P0 on all cores for best performance. All APs will be in hlt(C1). The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c 2008-04-22 23:20:07 UTC (rev 3250) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c 2008-04-22 23:27:53 UTC (rev 3251) @@ -18,6 +18,7 @@ */ #if FAM10_SET_FIDVID == 1 +#include "../../../northbridge/amd/amdht/AsPsDefs.h" #define FAM10_SET_FIDVID_DEBUG 1 @@ -46,6 +47,11 @@ } +struct fidvid_st { + u32 common_fid; +}; + + static void enable_fid_change(u8 fid) { u32 dword; @@ -53,7 +59,7 @@ device_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = get_nodes(); for(i = 0; i < nodes; i++) { dev = NODE_PCI(i,3); @@ -66,124 +72,293 @@ } } + +static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +{ + u8 pviModeFlag; + u8 highVoltageVid, lowVoltageVid, bValue; + u16 minimumSlamTime; + u16 vSlamTimes[7]={1000,2000,3000,4000,6000,10000,20000}; /* Reg settings scaled by 100 */ + u32 dtemp; + msr_t msr; + + /* This function calculates the VsSlamTime using the range of possible + * voltages instead of a hardcoded 200us. + * Note:This function is called from setFidVidRegs and setUserPs after + * programming a custom Pstate. + */ + + /* Calculate Slam Time + * Vslam = 0.4us/mV * Vp0 - (lowest out of Vpmin or Valt) + * In our case, we will scale the values by 100 to avoid + * decimals. + */ + + + + /* Determine if this is a PVI or SVI system */ + dtemp = pci_read_config32(dev, 0xA0); + + if( dtemp & PVI_MODE ) + pviModeFlag = 1; + else + pviModeFlag = 0; + + /* Get P0's voltage */ + msr = rdmsr(0xC0010064); + highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); + + /* If SVI, we only care about CPU VID. + * If PVI, determine the higher voltage b/t NB and CPU + */ + if (pviModeFlag) { + bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); + if( highVoltageVid > bValue ) + highVoltageVid = bValue; + } + + /* Get Pmin's index */ + msr = rdmsr(0xC0010061); + bValue = (u8) ((msr.lo >> PS_CUR_LIM_SHFT) & BIT_MASK_3); + + /* Get Pmin's VID */ + msr = rdmsr(0xC0010064 + bValue); + lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); + + /* If SVI, we only care about CPU VID. + * If PVI, determine the higher voltage b/t NB and CPU + */ + if (pviModeFlag) { + bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); + if( lowVoltageVid > bValue ) + lowVoltageVid = bValue; + } + + /* Get AltVID */ + dtemp = pci_read_config32(dev, 0xDC); + bValue = (u8) (dtemp & BIT_MASK_7); + + /* Use the VID with the lowest voltage (higher VID) */ + if( lowVoltageVid < bValue ) + lowVoltageVid = bValue; + + /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */ + if (lowVoltageVid > 0x7C) { + lowVoltageVid = 0x7C; + if(highVoltageVid > 0x7C) + highVoltageVid = 0x7C; + } + + bValue = (u8) (lowVoltageVid - highVoltageVid); + + /* Each Vid increment is 12.5 mV. The minimum slam time is: + * vidCodeDelta * 12.5mV * 0.4us/mV + * Scale by 100 to avoid decimals. + */ + minimumSlamTime = bValue * (125 * 4); + + /* Now round up to nearest register setting. + * Note that if we don't find a value, we + * will fall through to a value of 7 + */ + for(bValue=0; bValue < 7; bValue++) { + if(minimumSlamTime <= vSlamTimes[bValue]) + break; + } + + /* Apply the value */ + dtemp = pci_read_config32(dev, 0xD8); + dtemp &= VSSLAM_MASK; + dtemp |= bValue; + pci_write_config32(dev, 0xd8, dtemp); +} + + static void prep_fid_change(void) { - u32 dword; + u32 dword, dtemp; u32 nodes; device_t dev; int i; /* This needs to be run before any Pstate changes are requested */ - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = get_nodes(); for(i = 0; i < nodes; i++) { - printk_debug("Node:%02x \n", i); + printk_debug("Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i,3); - dword = pci_read_config32(dev, 0xa0); - dword &= ~(1<<29); - dword |= ((~dword >> 8) & 1) << 29; // SlamVidMode is the inverse to the PviMode - dword |= PLLLOCK_DFT_L; /* Force per BKDG */ - pci_write_config32(dev, 0xa0, dword); - printk_debug(" F3xA0: %08x \n", dword); - dword = pci_read_config32(dev, 0xd8); - dword &= ~0x77; - dword |= (1<<4) | 6; // VSRampTime, and VSSlamTime - dword |= 3 << 24; // ReConDel set to 3 per BKDG + dword &= VSRAMP_MASK; + dword |= VSRAMP_VALUE; pci_write_config32(dev, 0xd8, dword); - printk_debug(" F3xD8: %08x \n", dword); - dword = pci_read_config32(dev, 0xd4); - dword &= 0x1F; - dword |= 0xC331AF00; // per BKDG - pci_write_config32(dev, 0xd4, dword); - printk_debug(" F3xD4: %08x \n", dword); + /* Figure out the value for VsSlamTime and program it */ + recalculateVsSlamTimeSettingOnCorePre(dev); - dword = pci_read_config32(dev, 0xdc); - dword |= 0x5 << 12; // NbsynPtrAdj set to 0x5 per BKDG (needs reset) + /* Program fields in Clock Power/Control register0 (F3xD4) */ + /* set F3xD4 Clock Power/Timing Control 0 Register + * NbClkDidApplyAll=1b + * NbClkDid=100b + * PowerStepUp= "platform dependent" + * PowerStepDown= "platform dependent" + * LinkPllLink=01b + * ClkRampHystSel=HW default + */ + /* check platform type */ + if (!(get_platform_type() & AMD_PTYPE_SVR)) { + /* For non-server platform + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns + */ + dword = pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | + LNK_PLL_LOCK; /* per BKDG */ + pci_write_config32(dev, 0xd4, dword); + } else { + dword = pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + /* get number of cores for PowerStepUp & PowerStepDown in server + 1 core - 400nS - 0000b + 2 cores - 200nS - 0010b + 3 cores - 133nS -> 100nS - 0011b + 4 cores - 100nS - 0011b + */ + switch(get_core_num_in_bsp(i)) + { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } + dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; + pci_write_config32(dev, 0xd4, dword); + } + + /* check PVI/SVI */ + dword = pci_read_config32(dev, 0xA0); + if(dword & PVI_MODE) { /* PVI */ + /* set slamVidMode to 0 for PVI */ + dword &= VID_SLAM_OFF | PLLLOCK_OFF; + dword |= PLLLOCK_DFT_L; + pci_write_config32(dev, 0xA0, dword); + } else { /* SVI */ + /* set slamVidMode to 1 for SVI */ + dword &= PLLLOCK_OFF; + dword |= PLLLOCK_DFT_L | VID_SLAM_ON; + pci_write_config32(dev, 0xA0, dword); + + dtemp = dword; + + /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */ + dword = pci_read_config32(dev, 0xD8); + + if( dtemp & DUAL_VDD_BIT) + dword |= PWR_PLN_ON; + else + dword &= PWR_PLN_OFF; + pci_write_config32(dev, 0xD8, dword); + } + + /* Note the following settings are additional from the ported + * function setFidVidRegs() + */ + dword = pci_read_config32(dev, 0xDc); + dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); - printk_debug(" F3xDC: %08x \n", dword); - // Rev B settings - FIXME: support other revs. + /* Rev B settings - FIXME: support other revs. */ dword = 0xA0E641E6; pci_write_config32(dev, 0x84, dword); - printk_debug(" F3x84: %08x \n", dword); dword = 0xE600A681; pci_write_config32(dev, 0x80, dword); + + dword = pci_read_config32(dev, 0x80); printk_debug(" F3x80: %08x \n", dword); + dword = pci_read_config32(dev, 0x84); + printk_debug(" F3x84: %08x \n", dword); + dword = pci_read_config32(dev, 0xD4); + printk_debug(" F3xD4: %08x \n", dword); + dword = pci_read_config32(dev, 0xD8); + printk_debug(" F3xD8: %08x \n", dword); + dword = pci_read_config32(dev, 0xDC); + printk_debug(" F3xDC: %08x \n", dword); + } } -#include "fidvid_common.c" +static void UpdateSinglePlaneNbVid(void) +{ + u32 nbVid, cpuVid; + u8 i; + msr_t msr; + /* copy higher voltage (lower VID) of NBVID & CPUVID to both */ + for (i = 0; i < 5; i++) { + msr = rdmsr(PS_REG_BASE + i); + nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT; + cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT; + if( nbVid != cpuVid ) { + if(nbVid > cpuVid) + nbVid = cpuVid; -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) + msr.lo = msr.lo & PS_BOTH_VID_OFF; + msr.lo = msr.lo | (u32)((nbVid) << PS_NB_VID_SHFT); + msr.lo = msr.lo | (u32)((nbVid) << PS_CPU_VID_SHFT); + wrmsr(PS_REG_BASE + i, msr); + } + } +} + + + +static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid) { - msr_t msr; - device_t dev; - u8 vid_max; - u8 fid_max; u8 startup_pstate; - u8 nb_cof_vid_update; - u8 pvimode; - u32 reg1fc; - u32 dword; - u32 send; - printk_debug("FIDVID on AP: %02x\n", apicid); - - /* Only support single plane system at this time. */ - /* Steps 1-6 of BIOS NB COF and VID Configuration - * for Single-Plane PVI Systems + /* This function sets NbVid before the warm reset. + * Get StartupPstate from MSRC001_0071. + * Read Pstate register pionted by [StartupPstate]. + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. */ - dev = NODE_PCI(nodeid,3); - reg1fc = pci_read_config32(dev, 0x1FC); - nb_cof_vid_update = reg1fc & 1; - if (nb_cof_vid_update) { - /* Get fused settings */ - dword = pci_read_config32(dev, 0xa0); - pvimode = (dword >> 8) & 1; - vid_max = (reg1fc >> 7) & 0x7F; // per node - fid_max = (reg1fc >> 2) & 0x1F; // per system - - if (pvimode) { - /* FIXME: support daul plane mode */ - die("PVImode not supported\n"); - /* fidmax = vidmax - (reg1fc >> 17) & 0x1F; - fidmax = fidmax + (reg1fc >> 14) & 0x03; - */ - } - - } else { - /* Use current values */ - msr = rdmsr(0xc0010071); - fid_max = ((msr.hi >> (59-32)) & 0x1f); //max nb fid - vid_max = ((msr.hi >> (35-32)) & 0x7f); //max vid - } - - /* Note this is the single plane setup. Need to add dual plane path */ msr = rdmsr(0xc0010071); startup_pstate = (msr.hi >> (32-32)) & 0x07; - /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0. - Then transition to P1 for corex and P0 for core0. */ + * Then transition to P1 for corex and P0 for core0. + * These setting will be cleared by the warm reset + */ msr = rdmsr(0xC0010064 + startup_pstate); wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr); msr.lo &= ~0xFE000000; // clear nbvid - msr.lo |= vid_max << 25; + msr.lo |= newNbVid << 25; wrmsr(0xC0010064, msr); + UpdateSinglePlaneNbVid(); + // Transition to P1 for all APs and P0 for core0. msr = rdmsr(0xC0010062); msr.lo = (msr.lo & ~0x07) | 1; @@ -202,8 +377,165 @@ msr = rdmsr(0xC0010063); } while (msr.lo != 0); } +} +static void coreDelay (void) +{ + u32 saved; + u32 hi, lo, msr; + u32 cycles; + + /* delay ~40us + This seems like a hack to me... + It would be nice to have a central delay function. */ + + cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */ + + msr = 0x10; /* TSC */ + _RDMSR(msr, &lo, &hi); + saved = lo; + do { + _RDMSR(msr, &lo, &hi); + } while (lo - saved < cycles ); +} + + +static void transitionVid(u32 targetVid, u8 dev, u8 isNb) +{ + u32 currentVid, dtemp; + msr_t msr; + u8 vsTimecode; + u16 timeTable[8]={10, 20, 30, 40, 60, 100, 200, 500}; + int vsTime; + + /* This function steps or slam the Nb VID to the target VID. + * It uses VSRampTime for [SlamVidMode]=0 ([PviMode]=1) + * or VSSlamTime for [SlamVidMode]=1 ([PviMode]=0)to time period. + */ + + /* get the current VID */ + msr = rdmsr(0xC0010071); + if(isNb) + currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7; + else + currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7; + + /* Read MSRC001_0070 COFVID Control Register */ + msr = rdmsr(0xC0010070); + + /* check PVI/SPI */ + dtemp = pci_read_config32(dev, 0xA0); + if (dtemp & PVI_MODE) { /* PVI, step VID */ + if (currentVid < targetVid) { + while (currentVid < targetVid) { + currentVid++; + if(isNb) + msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); + else + msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); + wrmsr(0xC0010070, msr); + + /* read F3xD8[VSRampTime] */ + dtemp = pci_read_config32(dev, 0xD8); + vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int) timeTable[vsTimecode]; + do { + coreDelay(); + vsTime -=40; + } while(vsTime > 0); + } + } else if (currentVid > targetVid) { + while (currentVid > targetVid) { + currentVid--; + if(isNb) + msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); + else + msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); + wrmsr(0xC0010070, msr); + + /* read F3xD8[VSRampTime] */ + dtemp = pci_read_config32(dev, 0xD8); + vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int) timeTable[vsTimecode]; + do { + coreDelay(); + vsTime -=40; + } while(vsTime > 0); + } + } + } else { /* SVI, slam VID */ + if(isNb) + msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS); + else + msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS); + wrmsr(0xC0010070, msr); + + /* read F3xD8[VSRampTime] */ + dtemp = pci_read_config32(dev, 0xD8); + vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int) timeTable[vsTimecode]; + do { + coreDelay(); + vsTime -=40; + } while(vsTime > 0); + } +} + + +static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) +{ + device_t dev; + u32 vid_max; + u32 fid_max; + u8 nb_cof_vid_update; + u8 pvimode; + u32 reg1fc; + u32 send; + u8 nodes; + u8 i; + + printk_debug("FIDVID on AP: %02x\n", apicid); + + /* Steps 1-6 of BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems. + */ + + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nodes = get_nodes(); + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; + } + } + + dev = NODE_PCI(nodeid,3); + pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; + reg1fc = pci_read_config32(dev, 0x1FC); + + if (nb_cof_vid_update) { + if (pvimode) { + vid_max = (reg1fc >> 7) & 0x7F; + fid_max = (reg1fc >> 2) & 0x1F; + + /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ + fixPsNbVidBeforeWR(vid_max, coreid); + } else { /* SVI */ + vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); + fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7); + transitionVid(vid_max, dev, IS_NB); + } + + /* fid setup is handled by the BSP at the end. */ + + } else { /* ! nb_cof_vid_update */ + /* Use max values */ + if (pvimode) + UpdateSinglePlaneNbVid(); + } + send = (nb_cof_vid_update << 16) | (fid_max << 8); send |= (apicid << 24); // ap apicid @@ -232,9 +564,6 @@ return fid_packed; } -struct fidvid_st { - u32 common_fid; -}; static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp ) { @@ -269,44 +598,147 @@ } +static void updateSviPsNbVidAfterWR(u32 newNbVid) +{ + msr_t msr; + u8 i; + + /* This function copies newNbVid to NbVid bits in P-state Registers[4:0] + * for SVI mode. + */ + + for( i = 0; i < 5; i++) { + msr = rdmsr(0xC0010064 + i); + if ((msr.hi >> 31) & 1) { /* PstateEn? */ + msr.lo &= ~(0x7F << 25); + msr.lo |= (newNbVid & 0x7F) << 25; + wrmsr(0xC0010064 + i, msr); + } + } +} + + +static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll) +{ + msr_t msr; + u8 i; + u8 StartupPstate; + + /* This function copies newNbVid to NbVid bits in P-state + * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of + * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in + * P-state Registers[4:0] if its and PstateEn bit =1 in case of + * NbVidUpdatedAll=1. Then transition to StartPstate. + */ + + /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ + for( i = 0; i < 5; i++) { + msr = rdmsr(0xC0010064 + i); + /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ + if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) { + msr.lo &= ~(0x7F << 25); + msr.lo |= (newNbVid & 0x7F) << 25; + wrmsr (0xC0010064 + i, msr); + } + } + + UpdateSinglePlaneNbVid(); + + /* For each core in the system, transition all cores to StartupPstate */ + msr = rdmsr(0xC0010071); + StartupPstate = msr.hi & 0x07; + msr = rdmsr(0xC0010062); + msr.lo = StartupPstate; + wrmsr(0xC0010062, msr); + + /* Wait for StartupPstate to set.*/ + do { + msr = rdmsr(0xC0010063); + } while (msr.lo != StartupPstate); +} + + +static void set_p0(void) +{ + msr_t msr; + + // Transition P0 for calling core. + msr = rdmsr(0xC0010062); + msr.lo = (msr.lo & ~0x07); + wrmsr(0xC0010062, msr); + + /* Wait for P0 to set. */ + do { + msr = rdmsr(0xC0010063); + } while (msr.lo != 0); +} + + +static void finalPstateChange (void) { + /* Enble P0 on all cores for best performance. + * Linux can slow them down later if need be. + * It is safe since they will be in C1 halt + * most of the time anyway. + */ + set_p0(); +} + + static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; device_t dev; u32 reg1fc; - u8 StartupPstate; - u8 nbvid; - int i; + u32 dtemp; + u32 nbvid; + u8 nb_cof_vid_update; + u8 nodes; + u8 NbVidUpdateAll; + u8 i; + u8 pvimode; /* After warm reset finish the fid/vid setup for all cores. */ + + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nodes = get_nodes(); + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; + } + } + dev = NODE_PCI(nodeid,3); + pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; reg1fc = pci_read_config32(dev, 0x1FC); nbvid = (reg1fc >> 7) & 0x7F; + NbVidUpdateAll = (reg1fc >> 1) & 1; - if (reg1fc & 0x02) { // NbVidUpdateAll ? - for( i = 0; i < 5; i++) { - msr = rdmsr(0xC0010064 + i); - if ((msr.hi >> 31) & 1) { // PstateEn? - msr.lo &= ~(0x7F << 25); - msr.lo |= (nbvid & 0x7F) << 25; - } + if (nb_cof_vid_update) { + if (pvimode) { + nbvid = (reg1fc >> 7) & 0x7F; + /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ + fixPsNbVidAfterWR(nbvid, NbVidUpdateAll); + } else { /* SVI */ + nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); + updateSviPsNbVidAfterWR(nbvid); } - } else { - for( i = 0; i < 5; i++) { - msr = rdmsr(0xC0010064 + i); - if (((msr.hi >> 31) & 1) && (((msr.lo >> 22) & 1) == 0)) { // PstateEn and PDid == 0? - msr.lo &= ~(0x7F << 25); - msr.lo |= (nbvid & 0x7F) << 25; - } - } + } else { /* !nb_cof_vid_update */ + if (pvimode) + UpdateSinglePlaneNbVid(); } + dtemp = pci_read_config32(dev, 0xA0); + dtemp &= PLLLOCK_OFF; + dtemp |= PLLLOCK_DFT_L; + pci_write_config32(dev, 0xA0, dtemp); - // For each processor in the system, transition all cores to StartupPstate - msr = rdmsr(0xC0010071); - StartupPstate = msr.hi >> (32-32) & 0x03; - msr = rdmsr(0xC0010062); - msr.lo = StartupPstate; - wrmsr(0xC0010062, msr); + finalPstateChange(); + + /* Set TSC to tick at the P0 ndfid rate */ + msr = rdmsr(HWCR); + msr.lo |= 1 << 24; + wrmsr(HWCR, msr); } @@ -334,81 +766,56 @@ u32 i; #endif struct fidvid_st fv; - msr_t msr; device_t dev; - u8 vid_max; - u8 fid_max; - u8 startup_pstate; + u32 vid_max; + u32 fid_max; u8 nb_cof_vid_update; u32 reg1fc; - u32 dword; u8 pvimode; printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid); + /* FIXME: The first half of this function is nearly the same as + * init_fidvid_bsp() and the code could be combined. + */ - /* FIXME: Only support single plane system at this time. */ /* Steps 1-6 of BIOS NB COF and VID Configuration - * for Single-Plane PVI Systems + * for SVI and Single-Plane PVI Systems. */ - dev = NODE_PCI(0,3); // nodeid for the BSP is 0 - reg1fc = pci_read_config32(dev, 0x1FC); - nb_cof_vid_update = reg1fc & 1; - if (nb_cof_vid_update) { - /* Get fused settings */ - dword = pci_read_config32(dev, 0xa0); - pvimode = (dword >> 8) & 1; - vid_max = (reg1fc >> 7) & 0x7F; // per node - fid_max = (reg1fc >> 2) & 0x1F; // per system - - if (pvimode) { - /* FIXME: support daul plane mode */ - die("PVImode not supported\n"); - /* fidmax = vidmax - (reg1fc >> 17) & 0x1F; - fidmax = fidmax + (reg1fc >> 14) & 0x03; - */ + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; } - - } else { - /* Use current values */ - msr = rdmsr(0xc0010071); - fid_max = ((msr.hi >> (59-32)) & 0x1f); //max nb fid - vid_max = ((msr.hi >> (35-32)) & 0x7f); //max vid } - /* Note this is the single plane setup. Need to add dual plane path */ - msr = rdmsr(0xc0010071); - startup_pstate = (msr.hi >> (32-32)) & 0x07; + dev = NODE_PCI(0, 3); + pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; + reg1fc = pci_read_config32(dev, 0x1FC); + if (nb_cof_vid_update) { + if (pvimode) { + vid_max = (reg1fc >> 7) & 0x7F; + fid_max = (reg1fc >> 2) & 0x1F; - /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0. - Then transition to P1 for corex and P0 for core0. */ - msr = rdmsr(0xC0010064 + startup_pstate); - wrmsr(0xC0010065, msr); - wrmsr(0xC0010064, msr); + /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ + fixPsNbVidBeforeWR(vid_max, 0); + } else { /* SVI */ + vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); + fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7); + transitionVid(vid_max, dev, IS_NB); + } - msr.lo &= ~0xFE000000; // clear nbvid - msr.lo |= vid_max << 25; - wrmsr(0xC0010064, msr); + /* fid setup is handled by the BSP at the end. */ - // Transition to P1 and then P0 for core0. - msr = rdmsr(0xC0010062); - msr.lo = (msr.lo & ~0x07) | 1; - wrmsr(0xC0010062, msr); + } else { /* ! nb_cof_vid_update */ + /* Use max values */ + if (pvimode) + UpdateSinglePlaneNbVid(); + } - // Wait for P1 to set. - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 1); - - msr.lo = msr.lo & ~0x07; - wrmsr(0xC0010062, msr); - // Wait for P0 to set. - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 0); - - fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ; print_debug_fv("BSP fid = ", fv.common_fid); @@ -430,7 +837,7 @@ print_debug_fv("common_fid = ", fv.common_fid); - if (fv.common_fid & ~(0xFF << 16)) { // check nb_cof_vid_update + if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */ // Enable the common fid and other settings. enable_fid_change((fv.common_fid >> 8) & 0x1F); @@ -441,15 +848,4 @@ return 0; // No FID/VID changes. Don't reset } -static void set_p0(void) -{ - msr_t msr; - - // Transition P0 for calling core. - msr = rdmsr(0xC0010062); - msr.lo = (msr.lo & ~0x07); - wrmsr(0xC0010062, msr); - - // Don't bother to wait around for the P state to change. -} #endif Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-22 23:20:07 UTC (rev 3250) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-22 23:27:53 UTC (rev 3251) @@ -229,7 +229,6 @@ { struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; u32 bsp_apicid = 0; u32 val; msr_t msr; @@ -237,7 +236,7 @@ post_code(0x30); if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); //mmconf is inited in init_cpus + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } @@ -288,7 +287,7 @@ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 - // Core0 on each node is configured. Now setup any additional cores. + /* Core0 on each node is configured. Now setup any additional cores. */ printk_debug("start_other_cores()\n"); start_other_cores(); post_code(0x37); @@ -299,7 +298,7 @@ #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("Begin MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -307,36 +306,37 @@ post_code(0x39); - if (warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } else { - needs_reset |= (init_fidvid_bsp(bsp_apicid, sysinfo->nodes) << 31); } post_code(0x3A); - set_p0(); // Speed up the BSP! - - // show final fid and vid + /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif - // Reset for HT and FIDVID changes? - if (needs_reset) { - print_info("\tht reset -\n"); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); - //enable cf9 for hard reset + + /* FIXME: Move this to chipset init. + enable cf9 for hard reset */ print_debug("enable_cf9_x()\n"); enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x3C); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ printk_debug("fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-22 23:20:07 UTC (rev 3250) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-22 23:27:53 UTC (rev 3251) @@ -157,7 +157,10 @@ #define CPTC1 0xd8 /* Clock Power/Timing Control1 Register*/ #define VSRAMP_SLAM_MASK 0xffffff88 /* MaskOff [VSRampTime]&[VSSlamTime] */ #define VSRAMP_SLAM_VALUE 0x16 /* [VSRampTime]=001b&[VSSlamTime]=110b */ +#define VSRAMP_MASK 0xffffff8f /* MaskOff [VSRampTime] */ +#define VSRAMP_VALUE 0x10 /* [VSRampTime]=001b */ #define VS_RAMP_T 4 /* VSRampTime bit position */ +#define VSSLAM_MASK 0xfffffff8 /* MaskOff [VSSlamTime] */ #define PWR_PLN_SHIFT 28 /* PwrPlanes bit shift */ #define PWR_PLN_ON 0x10000000 /* PwrPlanes bit ON */ #define PWR_PLN_OFF 0x0efffffff /* PwrPlanes bit OFF */

1 0

[patch][v2][2/4] Family 10
by Marc Jones 23 Apr '08

23 Apr '08

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Update the FAM10 microcode to current versions. In addition, AP microcode is now updated in early initialization to support errata settings that require it. Signed-off-by: Marc Jones (marc.jones(a)amd.com) Index: coreboot-v2/src/cpu/amd/microcode/microcode.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/microcode/microcode.c 2008-04-16 10:20:04.000000000 -0600 +++ coreboot-v2/src/cpu/amd/microcode/microcode.c 2008-04-16 10:27:43.000000000 -0600 @@ -61,8 +61,8 @@ { if (m->processor_rev_id != equivalent_processor_rev_id) { - printk_debug("microcode: rev id does not match this patch.\n"); - printk_debug("microcode: Not updated! Fix microcode_updates[] \n"); + printk_err("microcode: rev id (%x) does not match this patch.\n", m->processor_rev_id); + printk_err("microcode: Not updated! Fix microcode_updates[] \n"); return 0; } if (m->nb_dev_id) { Index: coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h 2008-04-16 09:49:40.000000000 -0600 @@ -0,0 +1,164 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2008 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x11, 0x01, 0x65, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x9B, 0x78, 0x67, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xAA, 0x0B, 0x00, 0x00, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x11, 0x01, 0x66, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x83, 0x75, 0xF0, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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#include "mc_patch_01000065.h" #endif /* Dummy terminator */ @@ -57,6 +57,7 @@ 0x100f21, 0x1020, 0x100f2A, 0x1020, 0x100f22, 0x1022, + 0x100f23, 0x1022, }; u32 new_id; Index: coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/mc_patch_01000018.h 2008-04-16 10:20:04.000000000 -0600 +++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,163 +0,0 @@ -/* - ============================================================ - (c) Advanced Micro Devices, Inc., 2004-2005 - - The enclosed microcode is intended to be used with AMD - Microprocessors. You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - -0x07, 0x20, 0x08, 0x02, 0x18, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0x66, 0x70, 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x44, 0x06, 0x00, 0x00, -0xff, 0xff, 0xff, 0xff, 0xa4, 0x06, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, -0x72, 0x09, 0x00, 0x00, 0x70, 0x09, 0x00, 0x00, 0x9b, 0x0b, 0x00, 0x00, -0xff, 0xff, 0xff, 0xff, 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x37, -0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07, -0x37, 0xfc, 0x03, 0xf8, 0xc0, 0xff, 0xf7, 0x00, 0x80, 0xff, 0xc0, 0x3f, -0x9b, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00, -0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0x40, 0x37, 0x6b, -0xff, 0xfb, 0xfd, 0xff, 0x57, 0x7d, 0xf0, 0xcd, 0xff, 0x1f, 0xb7, 0xfe, -0xc0, 0xcf, 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. 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coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/model_10xxx_init.c 2008-04-16 10:20:04.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c 2008-04-16 10:27:43.000000000 -0600 @@ -369,7 +369,6 @@ } -extern void update_microcode(u32 cpu_deviceid); void model_10xxx_init(device_t dev) @@ -386,10 +385,6 @@ amd_setup_mtrrs(); x86_mtrr_check(); - - /* Update the microcode */ - update_microcode(dev->device); - disable_cache(); /* zero the machine check error status registers */ @@ -455,6 +450,7 @@ { X86_VENDOR_AMD, 0x100f21 }, { X86_VENDOR_AMD, 0x100f2A }, { X86_VENDOR_AMD, 0x100f22 }, + { X86_VENDOR_AMD, 0x100f23 }, { 0, 0 }, }; static struct cpu_driver model_10xxx __cpu_driver = {

3 8

[patch][v2] [1/4] Family 10
by Marc Jones 23 Apr '08

23 Apr '08

This is the first of four Fam10 patches that I have been promising since the coreboot summit. Thanks for being patient. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Add early MSR and PCI register initialization. This fixes many default setting as well as erratas. Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code. Signed-off-by: Marc Jones (marc.jones(a)amd.com) Index: coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-15 09:42:02.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-16 09:38:52.000000000 -0600 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "defaults.h" //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID #ifndef FAM10_SET_FIDVID @@ -29,7 +30,6 @@ #define FAM10_SET_FIDVID_CORE0_ONLY 0 #endif - static inline void print_initcpu8 (const char *strval, u8 val) { printk_debug("%s%02x\n", strval, val); @@ -55,6 +55,7 @@ static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); +void cpuSetAMDMSR(void); #if PCI_IO_CFG_EXT == 1 static inline void set_EnableCf8ExtCfg(void) @@ -261,12 +262,6 @@ } -static void wait_all_aps_started(u32 bsp_apicid) -{ - for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0); -} - - static void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 @@ -287,6 +282,15 @@ lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); } +static void enable_apic_ext_id(u32 node) +{ + u32 val; + + val = pci_read_config32(NODE_HT(node), 0x68); + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); + pci_write_config32(NODE_HT(node), 0x68, val); +} + static void STOP_CAR_AND_CPU() { @@ -383,6 +387,13 @@ if(apicid != bsp_apicid) { + /* Setup each AP's cores MSRs. + * This happens after HTinit. + * The BSP runs this code in it's own path. + */ + cpuSetAMDMSR(); + + #if FAM10_SET_FIDVID == 1 #if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1) // Run on all AP for proper FID/VID setup. @@ -512,13 +523,415 @@ } printk_debug(" done\n"); } -#endif +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ + +void AMD_Errata281(u8 node, u32 revision, u32 platform) +{ + /* Workaround for Transaction Scheduling Conflict in + * Northbridge Cross Bar. Implement XCS Token adjustment + * for ganged links. Also, perform fix up for the mixed + * revision case. + */ + + u32 reg, val; + u8 i; + u8 mixed = 0; + u8 nodes = get_nodes(); + + if (platform & AMD_PTYPE_SVR) { + /* For each node we need to check for a "broken" node */ + if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { + for (i = 0; i < nodes; i++) { + if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1)) { + mixed = 1; + break; + } + } + } + + if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) { + + /* F0X68[22:21] DsNpReqLmt0 = 01b */ + val = pci_read_config32(NODE_PCI(node, 0), 0x68); + val &= ~0x00600000; + val |= 0x00200000; + pci_write_config32(NODE_PCI(node, 0), 0x68, val); + + /* F3X6C */ + val = pci_read_config32(NODE_PCI(node, 3), 0x6C); + val &= ~0x700780F7; + val |= 0x00010094; + pci_write_config32(NODE_PCI(node, 3), 0x6C, val); + + /* F3X7C */ + val = pci_read_config32(NODE_PCI(node, 3), 0x7C); + val &= ~0x707FFF1F; + val |= 0x00144514; + pci_write_config32(NODE_PCI(node, 3), 0x7C, val); + + /* F3X144[3:0] RspTok = 0001b */ + val = pci_read_config32(NODE_PCI(node, 3), 0x144); + val &= ~0x0000000F; + val |= 0x00000001; + pci_write_config32(NODE_PCI(node, 3), 0x144, val); + + for (i = 0; i < 3; i++) { + reg = 0x148 + (i * 4); + val = pci_read_config32(NODE_PCI(node, 3), reg); + val &= ~0x000000FF; + val |= 0x000000DB; + pci_write_config32(NODE_PCI(node, 3), reg, val); + } + } + } +} + + +void AMD_Errata298(void) +{ + /* Workaround for L2 Eviction May Occur during operation to + * set Accessed or dirty bit. + */ + + msr_t msr; + u8 i; + u8 affectedRev = 0; + u8 nodes = get_nodes(); + + /* For each core we need to check for a "broken" node */ + for (i = 0; i < nodes; i++) { + if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) { + affectedRev = 1; + break; + } + } + + if (affectedRev) { + msr = rdmsr(HWCR); + msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ + wrmsr(HWCR, msr); + + msr = rdmsr(BU_CFG); + msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ + wrmsr(BU_CFG, msr); + + msr = rdmsr(OSVW_ID_Length); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_ID_Length, msr); + + msr = rdmsr(OSVW_Status); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_Status, msr); + } + + if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) { + msr = rdmsr(OSVW_ID_Length); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_ID_Length, msr); + + } +} + + +u32 get_platform_type(void) +{ + u32 ret = 0; + + switch(SYSTEM_TYPE) { + case 1: + ret |= AMD_PTYPE_DSK; + break; + case 2: + ret |= AMD_PTYPE_MOB; + break; + case 0: + ret |= AMD_PTYPE_SVR; + break; + default: + break; + } + + /* FIXME: add UMA support. */ + + /* All Fam10 are multi core */ + ret |= AMD_PTYPE_MC; + + return ret; +} + + +/** + * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. + * HT Phy operations are not valid on links that aren't present, so this + * prevents invalid accesses. + * + * Returns the offset of the link register. + */ +BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) +{ + u32 val; + + /* get start of CPU HT Host Capabilities */ + val = pci_read_config32(NODE_PCI(node, 0), 0x34); + val &= 0xFF; + + cap_count++; + + /* Traverse through the capabilities. */ + do { + val = pci_read_config32(NODE_PCI(node, 0), val); + /* Is the capability block a HyperTransport capability block? */ + if ((val & 0xFF) == 0x08) + /* Is the HT capability block an HT Host Capability? */ + if ((val & 0xE0000000) == (1 << 29)) + cap_count--; + val = (val >> 8) & 0xFF; + } while (cap_count && val); + + *offset = (u8) val; + + /* If requested capability found val != 0 */ + if (!cap_count) + return TRUE; + else + return FALSE; +} + + +/** + * AMD_checkLinkType - Compare desired link characteristics using a logical + * link type mask. + * + * Returns the link characteristic mask. + */ +u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff) +{ + u32 val; + u32 linktype; + + /* Check coherency */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); + val &= 0x1F; + + if (val == 3) + linktype |= HTPHY_LINKTYPE_COHERENT; + + if (val == 7) + linktype |= HTPHY_LINKTYPE_NONCOHERENT; + + /* Check gen3 */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); + + if (((val >> 8) & 0x0F) > 6) + linktype |= HTPHY_LINKTYPE_HT3; + else + linktype |= HTPHY_LINKTYPE_HT1; + + + /* Check ganged */ + val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); + + if ( val & 1) + linktype |= HTPHY_LINKTYPE_GANGED; + else + linktype |= HTPHY_LINKTYPE_UNGANGED; + + return linktype; +} + + +/** + * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update + * a phy setting for that link. + */ +void AMD_SetHtPhyRegister (u8 node, u8 link, u8 entry) +{ + u32 phyReg; + u32 phyBase; + u32 val; + + /* Determine this link's portal */ + if (link > 3) + link -= 4; + + phyBase = ((u32)link << 3) | 0x180; + + + /* Get the portal control register's initial value + * and update it to access the desired phy register + */ + phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase); + + if (fam10_htphy_default[entry].htreg > 0x1FF) { + phyReg &= ~HTPHY_DIRECT_OFFSET_MASK; + phyReg |= HTPHY_DIRECT_MAP; + } else { + phyReg &= ~HTPHY_OFFSET_MASK; + } + + /* Now get the current phy register data + * LinkPhyDone = 0, LinkPhyWrite = 0 is a read + */ + phyReg |= fam10_htphy_default[entry].htreg; + pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); + + do { + val = pci_read_config32(NODE_PCI(node, 4), phyBase); + } while (!(val & HTPHY_IS_COMPLETE_MASK)); + + /* Now we have the phy register data, apply the change */ + val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4); + val &= ~fam10_htphy_default[entry].mask; + val |= fam10_htphy_default[entry].data; + pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val); + + /* write it through the portal to the phy + * LinkPhyDone = 0, LinkPhyWrite = 1 is a write + */ + phyReg |= HTPHY_WRITE_CMD; + pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); + + do { + val = pci_read_config32(NODE_PCI(node, 4), phyBase); + } while (!(val & HTPHY_IS_COMPLETE_MASK)); +} + + +void cpuSetAMDMSR(void) +{ + /* This routine loads the CPU with default settings in fam10_msr_default + * table . It must be run after Cache-As-RAM has been enabled, and + * Hypertransport initialization has taken place. Also note + * that it is run on the current processor only, and only for the current + * processor core. + */ + msr_t msr; + u8 i; + u32 revision, platform; + + printk_debug("cpuSetAMDMSR "); + + revision = mctGetLogicalCPUID(0xFF); + platform = get_platform_type(); + + for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) { + if ((fam10_msr_default[i].revision & revision) && + (fam10_msr_default[i].platform & platform)) { + msr = rdmsr(fam10_msr_default[i].msr); + msr.hi &= ~fam10_msr_default[i].mask_hi; + msr.hi |= fam10_msr_default[i].data_hi; + msr.lo &= ~fam10_msr_default[i].mask_lo; + msr.lo |= fam10_msr_default[i].data_lo; + wrmsr(fam10_msr_default[i].msr, msr); + } + } + AMD_Errata298(); + + printk_debug(" done\n"); +} + + +void cpuSetAMDPCI(u8 node) +{ + /* This routine loads the CPU with default settings in fam10_pci_default + * table . It must be run after Cache-As-RAM has been enabled, and + * Hypertransport initialization has taken place. Also note + * that it is run for the first core on each node + */ + u8 i, j; + u32 revision, platform; + u32 val; + u8 offset; + + printk_debug("cpuSetAMDPCI %02d", node); + + revision = mctGetLogicalCPUID(node); + platform = get_platform_type(); + + for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { + if ((fam10_pci_default[i].revision & revision) && + (fam10_pci_default[i].platform & platform)) { + val = pci_read_config32(NODE_PCI(node, + fam10_pci_default[i].function), + fam10_pci_default[i].offset); + val &= ~fam10_pci_default[i].mask; + val |= fam10_pci_default[i].data; + pci_write_config32(NODE_PCI(node, + fam10_pci_default[i].function), + fam10_pci_default[i].offset, val); + } + } + + for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) { + if ((fam10_htphy_default[i].revision & revision) && + (fam10_htphy_default[i].platform & platform)) { + /* HT Phy settings either apply to both sublinks or have + * separate registers for sublink zero and one, so there + * will be two table entries. So, here we only loop + cd t * through the sublink zeros in function zero. + */ + for (j = 0; j < 4; j++) { + if (AMD_CpuFindCapability(node, j, &offset)) { + if (AMD_checkLinkType(node, j, offset) + & fam10_htphy_default[i].linktype) { + AMD_SetHtPhyRegister(node, j, i); + } + } else { + /* No more capabilities, + * link not present + */ + break; + } + } + } + } + + /* FIXME: add UMA support and programXbarToSriReg(); */ + + AMD_Errata281(node, revision, platform); + + /* FIXME: if the dct phy doesn't init correct it needs to reset. + if (revision & (AMD_DR_B2 | AMD_DR_B3)) + dctPhyDiag(); */ + + printk_debug(" done\n"); +} + + +void cpuInitializeMCA(void) +{ + /* Clears Machine Check Architecture (MCA) registers, which power on + * containing unknown data, on currently running processor. + * This routine should only be executed on initial power on (cold boot), + * not across a warm reset because valid data is present at that time. + */ + + msr_t msr; + u32 reg; + u8 i; + + if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ + msr = rdmsr(MCG_CAP); + if (msr.lo & MCG_CTL_P){ /* MCG_CTL_P bit is set? */ + msr.lo &= 0xFF; + msr.lo--; + msr.lo <<= 2; /* multiply the count by 4 */ + reg = MC0_STA + msr.lo; + msr.lo = msr.hi = 0; + for (i=0; i < 4; i++) { + wrmsr (reg, msr); + reg -=4; /* Touch status regs for each bank */ + } + } + } +} + + /** * finalize_node_setup() * * Do any additional post HT init * - * This could really be moved to cache_as_ram_auto.c since it really isn't HT init. */ void finalize_node_setup(struct sys_info *sysinfo) { @@ -535,7 +948,10 @@ sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); #endif - setup_link_trans_cntrl(); + + for (i = 0; i < nodes; i++) { + cpuSetAMDPCI(i); + } #if FAM10_SET_FIDVID == 1 // Prep each node for FID/VID setup. Index: coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdfam10/raminit_amdmct.c 2008-04-15 09:42:02.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2008-04-15 09:42:14.000000000 -0600 @@ -106,23 +106,26 @@ u32 mctGetLogicalCPUID(u32 Node) { + /* FIXME: Move this to a more generic place. Maybe to the CPU code */ + /* Converts the CPUID to a logical ID MASK that is used to check + CPU version support versions */ u32 dev; u32 val, valx; u32 family, model, stepping; u32 ret; - dev = PA_NBMISC(Node); - val = Get_NB32(dev, 0xfc); - print_debug("Family_Model:"); print_debug_hex32(val); print_debug("\n"); - - family = ((val >> 8) & 0x0f) + ((val>>20) & 0xff); - model = ((val>>4) & 0x0f) | ((val>>(16-4)) & 0xf0); - stepping = val & 0xff; - print_debug("Family:"); print_debug_hex8(family); print_debug("\t"); - print_debug("Model:"); print_debug_hex8(model); print_debug("\t"); - print_debug("Stepping:"); print_debug_hex8(stepping); print_debug("\n"); - valx = (family<<12) | (model<<4) | (stepping); - print_debug("converted:"); print_debug_hex32(valx); print_debug("\n"); + if (Node == 0xFF) { /* current node */ + val = cpuid_eax(0x80000001); + } else { + dev = PA_NBMISC(Node); + val = Get_NB32(dev, 0xfc); + } + + family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff); + model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0); + stepping = val & 0x0f; + + valx = (family << 12) | (model << 4) | (stepping); switch (valx) { case 0x10000: @@ -134,7 +137,21 @@ case 0x10002: ret = AMD_DR_A2; break; + case 0x10020: + ret = AMD_DR_B0; + break; + case 0x10021: + ret = AMD_DR_B1; + break; + case 0x10022: + ret = AMD_DR_B2; + break; + case 0x10023: + ret = AMD_DR_B3; + break; default: + /* FIXME: mabe we should die() here. */ + print_err("FIXME! CPU Version unknown or not supported! \n"); ret = 0; } Index: coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-15 09:42:02.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-16 10:19:39.000000000 -0600 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,14 +21,6 @@ #ifndef ASPSDEFS_H #define ASPSDEFS_H -/* AMD Platform Types */ -#define AMD_PTYPE_DSK 1 -#define AMD_PTYPE_MOB 2 -#define AMD_PTYPE_SVR 4 -#define AMD_PTYPE_DC 8 -#define AMD_PTYPE_MC 0x10 -#define AMD_PTYPE_UMA 0x20 - #define APIC_BAR 0x1b /* APIC_BAR register */ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ Index: coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdht/ht_wrapper.c 2008-04-15 09:42:02.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-04-16 10:19:34.000000000 -0600 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -60,6 +60,7 @@ #define NODE_MP(x) NODE_PCI(x,1) #define NODE_MC(x) NODE_PCI(x,3) #define NODE_LC(x) NODE_PCI(x,4) + static u32 get_nodes(void) { device_t dev; @@ -75,26 +76,6 @@ return nodes; } -static void enable_apic_ext_id(u32 node) -{ - u32 val; - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); -} - - -static void setup_link_trans_cntrl() -{ - /* FIXME: Not sure that this belongs here but it is HT related */ - u32 val; - val = pci_read_config32(NODE_HT(0), 0x68); - val |= 0x00206800; // DSNpReqLimit, LimitCldtCfg, BufRefPri, RespPassPW per BKDG; - pci_write_config32(NODE_HT(0), 0x68, val); -} - - - /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) Index: coreboot-v2/src/northbridge/amd/amdmct/amddefs.h =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdmct/amddefs.h 2008-04-15 09:42:02.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2008-04-15 09:42:14.000000000 -0600 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ + /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ #define AMD_SAFEMODE 0x80000000 /* Unknown future revision - SAFE MODE */ #define AMD_NPT_F0 0x00000001 /* F0 stepping */ @@ -37,33 +39,83 @@ #define AMD_DR_B1 0x00100000 /* Barcelona B1 */ #define AMD_DR_B2 0x00200000 /* Barcelona B2 */ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ +#define AMD_DR_B3 0x00800000 /* Barcelona B3 */ /* - Groups - Create as many as you wish, from the above public values -*/ -#define AMD_NPT_F2 (AMD_NPT_F2C + AMD_NPT_F2D + AMD_NPT_F2E + AMD_NPT_F2G + AMD_NPT_F2J + AMD_NPT_F2K) + * Groups - Create as many as you wish, from the above public values + */ +#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) #define AMD_NPT_F3 (AMD_NPT_F3L) -#define AMD_NPT_Fx (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2 + AMD_NPT_F3) -#define AMD_NPT_Gx (AMD_NPT_G0A + AMD_NPT_G1B) -#define AMD_NPT_ALL (AMD_NPT_Fx + AMD_NPT_Gx) -#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) -#define AMD_FINEDELAY (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2) +#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) +#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) +#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) +#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) #define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) +#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) +#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) +#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) +#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) +#define AMD_DR_ALL (AMD_DR_Bx) - -#define CPUID_EXT_PM 0x80000007 - -#define CPUID_MODEL 1 +/* + * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE + */ +#define AMD_PTYPE_DSK 0x001 /* Desktop/DTR/UP */ +#define AMD_PTYPE_MOB 0x002 /* Mobile/Cool-n-quiet */ +#define AMD_PTYPE_SVR 0x004 /* Workstation/Server/Multicore DT */ +#define AMD_PTYPE_UC 0x008 /* Single Core */ +#define AMD_PTYPE_DC 0x010 /* Dual Core */ +#define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */ +#define AMD_PTYPE_UMA 0x040 /* UMA required */ + + /* + * Groups - Create as many as you wish, from the above public values + */ +#define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */ -#define HWCR 0xC0010015 +/* + * CPU PCI HT PHY REGISTER, LINK TYPES - PRIVATE + */ +#define HTPHY_LINKTYPE_HT3 0x00000001 +#define HTPHY_LINKTYPE_HT1 0x00000002 +#define HTPHY_LINKTYPE_COHERENT 0x00000004 +#define HTPHY_LINKTYPE_NONCOHERENT 0x00000008 +#define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT) +#define HTPHY_LINKTYPE_GANGED 0x00000010 +#define HTPHY_LINKTYPE_UNGANGED 0x00000020 +#define HTPHY_LINKTYPE_ALL 0x7FFFFFFF -#define FidVidStatus 0xC0010042 +/* + * CPU HT PHY REGISTERS, FIELDS, AND MASKS + */ +#define HTPHY_OFFSET_MASK 0xE00001FF +#define HTPHY_WRITE_CMD 0x40000000 +#define HTPHY_IS_COMPLETE_MASK 0x80000000 +#define HTPHY_DIRECT_MAP 0x20000000 +#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF +/* + * Various AMD MSRs + */ +#define CPUID_EXT_PM 0x80000007 +#define CPUID_MODEL 1 +#define MCG_CAP 0x00000179 + #define MCG_CTL_P 8 +#define MC0_CTL 0x00000400 +#define MC0_STA MC0_CTL + 1 #define FS_Base 0xC0000100 - - +#define SYSCFG 0xC0010010 +#define HWCR 0xC0010015 +#define NB_CFG 0xC001001F +#define FidVidStatus 0xC0010042 +#define MC4_CTL_MASK 0xC0010048 +#define OSVW_ID_Length 0xC0010140 +#define OSVW_Status 0xC0010141 +#define CPUIDFEATURES 0xC0011004 +#define LS_CFG 0xC0011020 +#define DC_CFG 0xC0011022 #define BU_CFG 0xC0011023 #define BU_CFG2 0xC001102A Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-15 09:42:02.000000000 -0600 +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-15 09:42:14.000000000 -0600 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -255,60 +255,30 @@ // Load MPB val = cpuid_eax(1); - printk_debug("Family_Model: %08x \n", val); - - /* FIXME: Need to make sure that APs are updated with the microcode and Errata */ - update_microcode(val); - post_code(0x33); - - /* FIXME: This errata code needs to move out of the mainboard but I am not sure where to yet.*/ - /* FIXME: Check CPU revision to apply correct erratas */ - /* Rev B errata */ - /* Errata #169 - supercedes errata #131 */ - msr = rdmsr(0xC001001F); - msr.hi |= 1 << (32 - 32); - wrmsr(0xC001101F, msr); - - /* Errata #202 [DIS_PIGGY_BACK_SCRUB]=1 */ - msr = rdmsr(0xC0011022); - msr.hi |= 1 << 24; - wrmsr(0xC0010022, msr); - - /* 298 : FIXME: Fixed in B3/C1 */ -/* msr = rdmsr(0xC0010015); - msr.lo |= 1 << 3; - wrmsr(0xC0010015, msr); - - msr = rdmsr(0xC0011023); - msr.lo |= 1 << 1; - wrmsr(0xC0010023, msr); -*/ - /* FIXME: Erratum #254 revB1 BU_CFG[21]=1 */ - - + printk_debug("BSP Family_Model: %08x \n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - setup_mb_resource_map(); - post_code(0x34); - -// dump_pci_device(PCI_DEV(CBB, CDB, 0)); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); - post_code(0x35); + update_microcode(val); + post_code(0x33); - // FIXME: Add needs_reset check to HT links. - amd_ht_init(sysinfo); -// print_pci_devices(); -// dump_pci_devices(); + cpuSetAMDMSR(); + post_code(0x34); - post_code(0x36); + amd_ht_init(sysinfo); + post_code(0x35); + /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. @@ -378,10 +348,10 @@ memreset_setup(); + post_code(0x40); // die("Die Before MCT init."); - post_code(0x40); printk_debug("raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); Index: coreboot-v2/src/cpu/amd/model_10xxx/defaults.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2008-04-15 10:52:30.000000000 -0600 @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * Default MSR and errata settings. + */ +static const struct { + u32 msr; + u32 revision; + u32 platform; + u32 data_lo; + u32 data_hi; + u32 mask_lo; + u32 mask_hi; +} fam10_msr_default[] = { + { TOP_MEM2, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF }, + + { SYSCFG, AMD_DR_ALL, AMD_PTYPE_ALL, + 3 << 21, 0x00000000, + 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ + + { HWCR, AMD_DR_ALL, AMD_PTYPE_ALL, + 1 << 4, 0x00000000, + 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */ + + { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xF << 19, 0x00000000, + 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ + + { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR, + 0x00000000, 0x00000004, + 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */ + + { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR, + 0x00000000, 0x00000000, + 0x00000000, 0x00000C00 }, /* Errata 326 */ + + { NB_CFG, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + 0x00000000, 1 << 22, + 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ + + { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL, + 1 << 29, 0x00000000, + 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ + + { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL, + 1 << 24, 0x00000000, + 1 << 24, 0x00000000 }, /* Erratum #202 [DIS_PIGGY_BACK_SCRUB]=1 */ + + { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + 0 << 1, 0x00000000, + 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ + + { BU_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + 1 << 21, 0x00000000, + 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */ + + { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, + 1 << 23, 0x00000000, + 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */ + + /* CPUID_EXT_FEATURES */ + { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + 1 << 28, 0x00000000, + 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ + + { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC, + 0x00000000, 1 << (33-32), + 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ +}; + + +/* + * Default PCI and errata settings. + */ +static const struct { + u8 function; + u16 offset; + u32 revision; + u32 platform; + u32 data; + u32 mask; +} fam10_pci_default[] = { + + /* Function 0 - HT Config */ + + { 0, 0x68, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config, + [14:13] BufPriRel = 2h [11] RspPassPW set, + [22:21] DsNpReqLmt = 10b */ + + /* Errata 281 Workaround */ + { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ + + { 0, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xC4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xE4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + /* Link Global Extended Control Register */ + { 0, 0x16C, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x0000C000, 0x0000E000 }, /* [15:13] ForceFullT0 = 110b */ + + /* Function 1 - Map Init */ + + /* Before reading F1x114_x2 or F1x114_x3 software must + * initialize the registers or NB Array MCA errors may + * occur. BIOS should initialize index 0h of F1x114_x2 and + * F1x114_x3 to prevent reads from F1x114 from generating NB + * Array MCA errors. BKDG Doc #3116 Rev 1.07 + */ + + { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ + + { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000000, 0xFFFFFFFF }, /* Clear map */ + + { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ + + { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000000, 0xFFFFFFFF }, /* Clear map */ + + /* Function 2 - DRAM Controller */ + + /* Function 3 - Misc. Control */ + { 3, 0x40, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ + + { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x0A100044, 0x0A300044 }, /* [27] NB MCA to CPU0 Enable, + [25] DisPciCfgCpuErrRsp, + [21] SyncOnErr=0, + [20] SyncOnWDTEn=1, + [6] CpuErrDis, + [2] SyncOnUcEccEn=1 */ + + /* XBAR buffer settings */ + { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00018052, 0x700780F7 }, + + /* Errata 281 Workaround */ + { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, + + { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x60018051, 0x700780F7 }, + + { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00041153, 0x777777F7 }, + + { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x61221151, 0x777777F7 }, + + { 3, 0x74, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00080101, 0x000F7777 }, + + { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00090914, 0x707FFF1F }, + + /* Errata 281 Workaround */ + { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, + + { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00070814, 0x007FFF1F }, + + { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00800756, 0x00F3FFFF }, + + { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00C37756, 0x00F3FFFF }, + + { 3, 0x144, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00000036, 0x000000FF }, + + /* Errata 281 Workaround */ + { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, + /* [3:0] RspTok = 0001b */ + + { 3, 0x148, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x8000052A, 0xD5FFFFFF }, + + /* ACPI Power State Control Reg1 */ + { 3, 0x80, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xE6002200, 0xFFFFFFFF }, + + /* ACPI Power State Control Reg2 */ + { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xA0E641E6, 0xFFFFFFFF }, + + { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB, + 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ + + { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */ + + /* Reported Temp Control Register */ + { 3, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */ + + /* Clock Power/Timing Control 0 Register */ + { 3, 0xD4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1, + [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */ + + /* Clock Power/Timing Control 1 Register */ + { 3, 0xD8, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1, + [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */ + + + /* Clock Power/Timing Control 2 Register */ + { 3, 0xDC, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */ + + + /* Extended NB MCA Config Register */ + { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00700022, 0x00700022 }, /* [5] = DisPciCfgCpuMstAbtRsp + [22:20] = SyncFloodOn_Err = 7, + [1] = SyncFloodOnUsPwDataErr = 1 */ + + /* L3 Control Register */ + { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ + + /* IBS Control Register */ + { 3, 0x1CC, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ +}; + + +/* + * Default HyperTransport Phy and errata settings. + */ +static const struct { + u16 htreg; /* HT Phy Register index */ + u32 revision; + u32 platform; + u32 linktype; + u32 data; + u32 mask; +} fam10_htphy_default[] = { + + { 0x520A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ + + { 0x530A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ + + { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + + { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + + { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + /* Link Phy Receiver Loop Filter Registers */ + { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + + { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + + { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ + + { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ +};

3 4

r3250 - in trunk/coreboot-v2/src/cpu/amd: microcode model_10xxx
by svn＠coreboot.org 23 Apr '08

23 Apr '08

Author: mjones Date: 2008-04-23 01:20:07 +0200 (Wed, 23 Apr 2008) New Revision: 3250 Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000066.h Removed: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h Modified: trunk/coreboot-v2/src/cpu/amd/microcode/microcode.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c Log: Update the FAM10 microcode to current versions. In addition, AP microcode is now updated in early initialization to support errata settings that require it. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/microcode/microcode.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/microcode/microcode.c 2008-04-22 23:09:34 UTC (rev 3249) +++ trunk/coreboot-v2/src/cpu/amd/microcode/microcode.c 2008-04-22 23:20:07 UTC (rev 3250) @@ -61,8 +61,8 @@ { if (m->processor_rev_id != equivalent_processor_rev_id) { - printk_debug("microcode: rev id does not match this patch.\n"); - printk_debug("microcode: Not updated! Fix microcode_updates[] \n"); + printk_err("microcode: rev id (%x) does not match this patch.\n", m->processor_rev_id); + printk_err("microcode: Not updated! Fix microcode_updates[] \n"); return 0; } if (m->nb_dev_id) { Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-22 23:09:34 UTC (rev 3249) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-22 23:20:07 UTC (rev 3250) @@ -53,6 +53,7 @@ } +void update_microcode(u32 cpu_deviceid); static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); @@ -391,6 +392,7 @@ * This happens after HTinit. * The BSP runs this code in it's own path. */ + update_microcode(cpuid_eax(1)); cpuSetAMDMSR(); Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h 2008-04-22 23:09:34 UTC (rev 3249) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h 2008-04-22 23:20:07 UTC (rev 3250) @@ -1,163 +0,0 @@ -/* - ============================================================ - (c) Advanced Micro Devices, Inc., 2004-2005 - - The enclosed microcode is intended to be used with AMD - Microprocessors. You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - -0x07, 0x20, 0x27, 0x06, 0x33, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00, -0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - -0x07, 0x20, 0x23, 0x07, 0x35, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00, -0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x11, 0x01, 0x65, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x9B, 0x78, 0x67, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xAA, 0x0B, 0x00, 0x00, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x11, 0x01, 0x66, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x83, 0x75, 0xF0, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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+450,7 @@ { X86_VENDOR_AMD, 0x100f21 }, { X86_VENDOR_AMD, 0x100f2A }, { X86_VENDOR_AMD, 0x100f22 }, + { X86_VENDOR_AMD, 0x100f23 }, { 0, 0 }, }; static struct cpu_driver model_10xxx __cpu_driver = { Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2008-04-22 23:09:34 UTC (rev 3249) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2008-04-22 23:20:07 UTC (rev 3250) @@ -31,14 +31,14 @@ #ifdef __ROMCC__ - // Barcelona revAx + // Barcelona rev Ax // #include "mc_patch_01000020.h" - // Barcelona revBx - #include "mc_patch_01000033.h" + // Barcelona rev B0, B1, BA +// #include "mc_patch_01000066.h" - // Barcelona rev Cx?? -// #include "mc_patch_01000035.h" + // Barcelona rev B2, B3 + #include "mc_patch_01000065.h" #endif /* Dummy terminator */ @@ -57,6 +57,7 @@ 0x100f21, 0x1020, 0x100f2A, 0x1020, 0x100f22, 0x1022, + 0x100f23, 0x1022, }; u32 new_id;

1 0

r3249 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
by svn＠coreboot.org 23 Apr '08

23 Apr '08

Author: mjones Date: 2008-04-23 01:09:34 +0200 (Wed, 23 Apr 2008) New Revision: 3249 Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h Log: Missed this file in the previous check-in, r3248. Add early MSR and PCI register initialization. This fixes many default setting as well as erratas. Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2008-04-22 23:09:34 UTC (rev 3249) @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * Default MSR and errata settings. + */ +static const struct { + u32 msr; + u32 revision; + u32 platform; + u32 data_lo; + u32 data_hi; + u32 mask_lo; + u32 mask_hi; +} fam10_msr_default[] = { + { TOP_MEM2, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF }, + + { SYSCFG, AMD_DR_ALL, AMD_PTYPE_ALL, + 3 << 21, 0x00000000, + 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ + + { HWCR, AMD_DR_ALL, AMD_PTYPE_ALL, + 1 << 4, 0x00000000, + 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */ + + { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xF << 19, 0x00000000, + 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ + + { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR, + 0x00000000, 0x00000004, + 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */ + + { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR, + 0x00000000, 0x00000000, + 0x00000000, 0x00000C00 }, /* Errata 326 */ + + { NB_CFG, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + 0x00000000, 1 << 22, + 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ + + { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL, + 1 << 29, 0x00000000, + 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ + + { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL, + 1 << 24, 0x00000000, + 1 << 24, 0x00000000 }, /* Erratum #202 [DIS_PIGGY_BACK_SCRUB]=1 */ + + { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + 0 << 1, 0x00000000, + 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ + + { BU_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + 1 << 21, 0x00000000, + 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */ + + { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, + 1 << 23, 0x00000000, + 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */ + + /* CPUID_EXT_FEATURES */ + { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + 1 << 28, 0x00000000, + 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ + + { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC, + 0x00000000, 1 << (33-32), + 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ +}; + + +/* + * Default PCI and errata settings. + */ +static const struct { + u8 function; + u16 offset; + u32 revision; + u32 platform; + u32 data; + u32 mask; +} fam10_pci_default[] = { + + /* Function 0 - HT Config */ + + { 0, 0x68, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config, + [14:13] BufPriRel = 2h [11] RspPassPW set, + [22:21] DsNpReqLmt = 10b */ + + /* Errata 281 Workaround */ + { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ + + { 0, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xC4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xE4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + /* Link Global Extended Control Register */ + { 0, 0x16C, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x0000C000, 0x0000E000 }, /* [15:13] ForceFullT0 = 110b */ + + /* Function 1 - Map Init */ + + /* Before reading F1x114_x2 or F1x114_x3 software must + * initialize the registers or NB Array MCA errors may + * occur. BIOS should initialize index 0h of F1x114_x2 and + * F1x114_x3 to prevent reads from F1x114 from generating NB + * Array MCA errors. BKDG Doc #3116 Rev 1.07 + */ + + { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ + + { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000000, 0xFFFFFFFF }, /* Clear map */ + + { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ + + { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000000, 0xFFFFFFFF }, /* Clear map */ + + /* Function 2 - DRAM Controller */ + + /* Function 3 - Misc. Control */ + { 3, 0x40, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ + + { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x0A100044, 0x0A300044 }, /* [27] NB MCA to CPU0 Enable, + [25] DisPciCfgCpuErrRsp, + [21] SyncOnErr=0, + [20] SyncOnWDTEn=1, + [6] CpuErrDis, + [2] SyncOnUcEccEn=1 */ + + /* XBAR buffer settings */ + { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00018052, 0x700780F7 }, + + /* Errata 281 Workaround */ + { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, + + { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x60018051, 0x700780F7 }, + + { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00041153, 0x777777F7 }, + + { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x61221151, 0x777777F7 }, + + { 3, 0x74, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00080101, 0x000F7777 }, + + { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00090914, 0x707FFF1F }, + + /* Errata 281 Workaround */ + { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, + + { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00070814, 0x007FFF1F }, + + { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00800756, 0x00F3FFFF }, + + { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00C37756, 0x00F3FFFF }, + + { 3, 0x144, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x00000036, 0x000000FF }, + + /* Errata 281 Workaround */ + { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, + /* [3:0] RspTok = 0001b */ + + { 3, 0x148, AMD_DR_ALL, AMD_PTYPE_UMA, + 0x8000052A, 0xD5FFFFFF }, + + /* ACPI Power State Control Reg1 */ + { 3, 0x80, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xE6002200, 0xFFFFFFFF }, + + /* ACPI Power State Control Reg2 */ + { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xA0E641E6, 0xFFFFFFFF }, + + { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB, + 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ + + { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */ + + /* Reported Temp Control Register */ + { 3, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */ + + /* Clock Power/Timing Control 0 Register */ + { 3, 0xD4, AMD_DR_ALL, AMD_PTYPE_ALL, + 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1, + [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */ + + /* Clock Power/Timing Control 1 Register */ + { 3, 0xD8, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1, + [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */ + + + /* Clock Power/Timing Control 2 Register */ + { 3, 0xDC, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */ + + + /* Extended NB MCA Config Register */ + { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00700022, 0x00700022 }, /* [5] = DisPciCfgCpuMstAbtRsp + [22:20] = SyncFloodOn_Err = 7, + [1] = SyncFloodOnUsPwDataErr = 1 */ + + /* L3 Control Register */ + { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ + + /* IBS Control Register */ + { 3, 0x1CC, AMD_DR_ALL, AMD_PTYPE_ALL, + 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ +}; + + +/* + * Default HyperTransport Phy and errata settings. + */ +static const struct { + u16 htreg; /* HT Phy Register index */ + u32 revision; + u32 platform; + u32 linktype; + u32 data; + u32 mask; +} fam10_htphy_default[] = { + + { 0x520A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ + + { 0x530A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ + + { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + + { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + + { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + /* Link Phy Receiver Loop Filter Registers */ + { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + + { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + + { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ + + { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ +};

1 0

r3248 build service
by coreboot information 23 Apr '08

23 Apr '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3248 to the coreboot source repository and caused the following changes: Change Log: Add early MSR and PCI register initialization. This fixes many default setting as well as erratas. Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3248&device=serengeti_chee… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3248 - in trunk/coreboot-v2/src: cpu/amd/model_10xxx mainboard/amd/serengeti_cheetah_fam10 northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct
by svn＠coreboot.org 23 Apr '08

23 Apr '08

Author: mjones Date: 2008-04-23 00:11:31 +0200 (Wed, 23 Apr 2008) New Revision: 3248 Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h Log: Add early MSR and PCI register initialization. This fixes many default setting as well as erratas. Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-22 20:19:53 UTC (rev 3247) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-22 22:11:31 UTC (rev 3248) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "defaults.h" //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID #ifndef FAM10_SET_FIDVID @@ -29,7 +30,6 @@ #define FAM10_SET_FIDVID_CORE0_ONLY 0 #endif - static inline void print_initcpu8 (const char *strval, u8 val) { printk_debug("%s%02x\n", strval, val); @@ -55,6 +55,7 @@ static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); +void cpuSetAMDMSR(void); #if PCI_IO_CFG_EXT == 1 static inline void set_EnableCf8ExtCfg(void) @@ -261,12 +262,6 @@ } -static void wait_all_aps_started(u32 bsp_apicid) -{ - for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0); -} - - static void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 @@ -287,7 +282,16 @@ lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); } +static void enable_apic_ext_id(u32 node) +{ + u32 val; + val = pci_read_config32(NODE_HT(node), 0x68); + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); + pci_write_config32(NODE_HT(node), 0x68, val); +} + + static void STOP_CAR_AND_CPU() { disable_cache_as_ram(); // inline @@ -383,6 +387,13 @@ if(apicid != bsp_apicid) { + /* Setup each AP's cores MSRs. + * This happens after HTinit. + * The BSP runs this code in it's own path. + */ + cpuSetAMDMSR(); + + #if FAM10_SET_FIDVID == 1 #if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1) // Run on all AP for proper FID/VID setup. @@ -512,13 +523,415 @@ } printk_debug(" done\n"); } -#endif +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ + +void AMD_Errata281(u8 node, u32 revision, u32 platform) +{ + /* Workaround for Transaction Scheduling Conflict in + * Northbridge Cross Bar. Implement XCS Token adjustment + * for ganged links. Also, perform fix up for the mixed + * revision case. + */ + + u32 reg, val; + u8 i; + u8 mixed = 0; + u8 nodes = get_nodes(); + + if (platform & AMD_PTYPE_SVR) { + /* For each node we need to check for a "broken" node */ + if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { + for (i = 0; i < nodes; i++) { + if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1)) { + mixed = 1; + break; + } + } + } + + if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) { + + /* F0X68[22:21] DsNpReqLmt0 = 01b */ + val = pci_read_config32(NODE_PCI(node, 0), 0x68); + val &= ~0x00600000; + val |= 0x00200000; + pci_write_config32(NODE_PCI(node, 0), 0x68, val); + + /* F3X6C */ + val = pci_read_config32(NODE_PCI(node, 3), 0x6C); + val &= ~0x700780F7; + val |= 0x00010094; + pci_write_config32(NODE_PCI(node, 3), 0x6C, val); + + /* F3X7C */ + val = pci_read_config32(NODE_PCI(node, 3), 0x7C); + val &= ~0x707FFF1F; + val |= 0x00144514; + pci_write_config32(NODE_PCI(node, 3), 0x7C, val); + + /* F3X144[3:0] RspTok = 0001b */ + val = pci_read_config32(NODE_PCI(node, 3), 0x144); + val &= ~0x0000000F; + val |= 0x00000001; + pci_write_config32(NODE_PCI(node, 3), 0x144, val); + + for (i = 0; i < 3; i++) { + reg = 0x148 + (i * 4); + val = pci_read_config32(NODE_PCI(node, 3), reg); + val &= ~0x000000FF; + val |= 0x000000DB; + pci_write_config32(NODE_PCI(node, 3), reg, val); + } + } + } +} + + +void AMD_Errata298(void) +{ + /* Workaround for L2 Eviction May Occur during operation to + * set Accessed or dirty bit. + */ + + msr_t msr; + u8 i; + u8 affectedRev = 0; + u8 nodes = get_nodes(); + + /* For each core we need to check for a "broken" node */ + for (i = 0; i < nodes; i++) { + if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) { + affectedRev = 1; + break; + } + } + + if (affectedRev) { + msr = rdmsr(HWCR); + msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ + wrmsr(HWCR, msr); + + msr = rdmsr(BU_CFG); + msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ + wrmsr(BU_CFG, msr); + + msr = rdmsr(OSVW_ID_Length); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_ID_Length, msr); + + msr = rdmsr(OSVW_Status); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_Status, msr); + } + + if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) { + msr = rdmsr(OSVW_ID_Length); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_ID_Length, msr); + + } +} + + +u32 get_platform_type(void) +{ + u32 ret = 0; + + switch(SYSTEM_TYPE) { + case 1: + ret |= AMD_PTYPE_DSK; + break; + case 2: + ret |= AMD_PTYPE_MOB; + break; + case 0: + ret |= AMD_PTYPE_SVR; + break; + default: + break; + } + + /* FIXME: add UMA support. */ + + /* All Fam10 are multi core */ + ret |= AMD_PTYPE_MC; + + return ret; +} + + /** + * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. + * HT Phy operations are not valid on links that aren't present, so this + * prevents invalid accesses. + * + * Returns the offset of the link register. + */ +BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) +{ + u32 val; + + /* get start of CPU HT Host Capabilities */ + val = pci_read_config32(NODE_PCI(node, 0), 0x34); + val &= 0xFF; + + cap_count++; + + /* Traverse through the capabilities. */ + do { + val = pci_read_config32(NODE_PCI(node, 0), val); + /* Is the capability block a HyperTransport capability block? */ + if ((val & 0xFF) == 0x08) + /* Is the HT capability block an HT Host Capability? */ + if ((val & 0xE0000000) == (1 << 29)) + cap_count--; + val = (val >> 8) & 0xFF; + } while (cap_count && val); + + *offset = (u8) val; + + /* If requested capability found val != 0 */ + if (!cap_count) + return TRUE; + else + return FALSE; +} + + +/** + * AMD_checkLinkType - Compare desired link characteristics using a logical + * link type mask. + * + * Returns the link characteristic mask. + */ +u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff) +{ + u32 val; + u32 linktype; + + /* Check coherency */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); + val &= 0x1F; + + if (val == 3) + linktype |= HTPHY_LINKTYPE_COHERENT; + + if (val == 7) + linktype |= HTPHY_LINKTYPE_NONCOHERENT; + + /* Check gen3 */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); + + if (((val >> 8) & 0x0F) > 6) + linktype |= HTPHY_LINKTYPE_HT3; + else + linktype |= HTPHY_LINKTYPE_HT1; + + + /* Check ganged */ + val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); + + if ( val & 1) + linktype |= HTPHY_LINKTYPE_GANGED; + else + linktype |= HTPHY_LINKTYPE_UNGANGED; + + return linktype; +} + + +/** + * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update + * a phy setting for that link. + */ +void AMD_SetHtPhyRegister (u8 node, u8 link, u8 entry) +{ + u32 phyReg; + u32 phyBase; + u32 val; + + /* Determine this link's portal */ + if (link > 3) + link -= 4; + + phyBase = ((u32)link << 3) | 0x180; + + + /* Get the portal control register's initial value + * and update it to access the desired phy register + */ + phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase); + + if (fam10_htphy_default[entry].htreg > 0x1FF) { + phyReg &= ~HTPHY_DIRECT_OFFSET_MASK; + phyReg |= HTPHY_DIRECT_MAP; + } else { + phyReg &= ~HTPHY_OFFSET_MASK; + } + + /* Now get the current phy register data + * LinkPhyDone = 0, LinkPhyWrite = 0 is a read + */ + phyReg |= fam10_htphy_default[entry].htreg; + pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); + + do { + val = pci_read_config32(NODE_PCI(node, 4), phyBase); + } while (!(val & HTPHY_IS_COMPLETE_MASK)); + + /* Now we have the phy register data, apply the change */ + val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4); + val &= ~fam10_htphy_default[entry].mask; + val |= fam10_htphy_default[entry].data; + pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val); + + /* write it through the portal to the phy + * LinkPhyDone = 0, LinkPhyWrite = 1 is a write + */ + phyReg |= HTPHY_WRITE_CMD; + pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); + + do { + val = pci_read_config32(NODE_PCI(node, 4), phyBase); + } while (!(val & HTPHY_IS_COMPLETE_MASK)); +} + + +void cpuSetAMDMSR(void) +{ + /* This routine loads the CPU with default settings in fam10_msr_default + * table . It must be run after Cache-As-RAM has been enabled, and + * Hypertransport initialization has taken place. Also note + * that it is run on the current processor only, and only for the current + * processor core. + */ + msr_t msr; + u8 i; + u32 revision, platform; + + printk_debug("cpuSetAMDMSR "); + + revision = mctGetLogicalCPUID(0xFF); + platform = get_platform_type(); + + for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) { + if ((fam10_msr_default[i].revision & revision) && + (fam10_msr_default[i].platform & platform)) { + msr = rdmsr(fam10_msr_default[i].msr); + msr.hi &= ~fam10_msr_default[i].mask_hi; + msr.hi |= fam10_msr_default[i].data_hi; + msr.lo &= ~fam10_msr_default[i].mask_lo; + msr.lo |= fam10_msr_default[i].data_lo; + wrmsr(fam10_msr_default[i].msr, msr); + } + } + AMD_Errata298(); + + printk_debug(" done\n"); +} + + +void cpuSetAMDPCI(u8 node) +{ + /* This routine loads the CPU with default settings in fam10_pci_default + * table . It must be run after Cache-As-RAM has been enabled, and + * Hypertransport initialization has taken place. Also note + * that it is run for the first core on each node + */ + u8 i, j; + u32 revision, platform; + u32 val; + u8 offset; + + printk_debug("cpuSetAMDPCI %02d", node); + + revision = mctGetLogicalCPUID(node); + platform = get_platform_type(); + + for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { + if ((fam10_pci_default[i].revision & revision) && + (fam10_pci_default[i].platform & platform)) { + val = pci_read_config32(NODE_PCI(node, + fam10_pci_default[i].function), + fam10_pci_default[i].offset); + val &= ~fam10_pci_default[i].mask; + val |= fam10_pci_default[i].data; + pci_write_config32(NODE_PCI(node, + fam10_pci_default[i].function), + fam10_pci_default[i].offset, val); + } + } + + for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) { + if ((fam10_htphy_default[i].revision & revision) && + (fam10_htphy_default[i].platform & platform)) { + /* HT Phy settings either apply to both sublinks or have + * separate registers for sublink zero and one, so there + * will be two table entries. So, here we only loop + cd t * through the sublink zeros in function zero. + */ + for (j = 0; j < 4; j++) { + if (AMD_CpuFindCapability(node, j, &offset)) { + if (AMD_checkLinkType(node, j, offset) + & fam10_htphy_default[i].linktype) { + AMD_SetHtPhyRegister(node, j, i); + } + } else { + /* No more capabilities, + * link not present + */ + break; + } + } + } + } + + /* FIXME: add UMA support and programXbarToSriReg(); */ + + AMD_Errata281(node, revision, platform); + + /* FIXME: if the dct phy doesn't init correct it needs to reset. + if (revision & (AMD_DR_B2 | AMD_DR_B3)) + dctPhyDiag(); */ + + printk_debug(" done\n"); +} + + +void cpuInitializeMCA(void) +{ + /* Clears Machine Check Architecture (MCA) registers, which power on + * containing unknown data, on currently running processor. + * This routine should only be executed on initial power on (cold boot), + * not across a warm reset because valid data is present at that time. + */ + + msr_t msr; + u32 reg; + u8 i; + + if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ + msr = rdmsr(MCG_CAP); + if (msr.lo & MCG_CTL_P){ /* MCG_CTL_P bit is set? */ + msr.lo &= 0xFF; + msr.lo--; + msr.lo <<= 2; /* multiply the count by 4 */ + reg = MC0_STA + msr.lo; + msr.lo = msr.hi = 0; + for (i=0; i < 4; i++) { + wrmsr (reg, msr); + reg -=4; /* Touch status regs for each bank */ + } + } + } +} + + +/** * finalize_node_setup() * * Do any additional post HT init * - * This could really be moved to cache_as_ram_auto.c since it really isn't HT init. */ void finalize_node_setup(struct sys_info *sysinfo) { @@ -535,8 +948,11 @@ sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); #endif - setup_link_trans_cntrl(); + for (i = 0; i < nodes; i++) { + cpuSetAMDPCI(i); + } + #if FAM10_SET_FIDVID == 1 // Prep each node for FID/VID setup. prep_fid_change(); Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-22 20:19:53 UTC (rev 3247) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-22 22:11:31 UTC (rev 3248) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -255,60 +255,30 @@ // Load MPB val = cpuid_eax(1); - printk_debug("Family_Model: %08x \n", val); - - /* FIXME: Need to make sure that APs are updated with the microcode and Errata */ - update_microcode(val); - post_code(0x33); - - /* FIXME: This errata code needs to move out of the mainboard but I am not sure where to yet.*/ - /* FIXME: Check CPU revision to apply correct erratas */ - /* Rev B errata */ - /* Errata #169 - supercedes errata #131 */ - msr = rdmsr(0xC001001F); - msr.hi |= 1 << (32 - 32); - wrmsr(0xC001101F, msr); - - /* Errata #202 [DIS_PIGGY_BACK_SCRUB]=1 */ - msr = rdmsr(0xC0011022); - msr.hi |= 1 << 24; - wrmsr(0xC0010022, msr); - - /* 298 : FIXME: Fixed in B3/C1 */ -/* msr = rdmsr(0xC0010015); - msr.lo |= 1 << 3; - wrmsr(0xC0010015, msr); - - msr = rdmsr(0xC0011023); - msr.lo |= 1 << 1; - wrmsr(0xC0010023, msr); -*/ - /* FIXME: Erratum #254 revB1 BU_CFG[21]=1 */ - - + printk_debug("BSP Family_Model: %08x \n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - setup_mb_resource_map(); - post_code(0x34); - -// dump_pci_device(PCI_DEV(CBB, CDB, 0)); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); - post_code(0x35); + update_microcode(val); + post_code(0x33); - // FIXME: Add needs_reset check to HT links. + cpuSetAMDMSR(); + post_code(0x34); + amd_ht_init(sysinfo); -// print_pci_devices(); -// dump_pci_devices(); + post_code(0x35); - post_code(0x36); - + /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. @@ -378,10 +348,10 @@ memreset_setup(); + post_code(0x40); // die("Die Before MCT init."); - post_code(0x40); printk_debug("raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2008-04-22 20:19:53 UTC (rev 3247) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2008-04-22 22:11:31 UTC (rev 3248) @@ -106,24 +106,27 @@ u32 mctGetLogicalCPUID(u32 Node) { + /* FIXME: Move this to a more generic place. Maybe to the CPU code */ + /* Converts the CPUID to a logical ID MASK that is used to check + CPU version support versions */ u32 dev; u32 val, valx; u32 family, model, stepping; u32 ret; - dev = PA_NBMISC(Node); - val = Get_NB32(dev, 0xfc); - print_debug("Family_Model:"); print_debug_hex32(val); print_debug("\n"); - family = ((val >> 8) & 0x0f) + ((val>>20) & 0xff); - model = ((val>>4) & 0x0f) | ((val>>(16-4)) & 0xf0); - stepping = val & 0xff; - print_debug("Family:"); print_debug_hex8(family); print_debug("\t"); - print_debug("Model:"); print_debug_hex8(model); print_debug("\t"); - print_debug("Stepping:"); print_debug_hex8(stepping); print_debug("\n"); + if (Node == 0xFF) { /* current node */ + val = cpuid_eax(0x80000001); + } else { + dev = PA_NBMISC(Node); + val = Get_NB32(dev, 0xfc); + } - valx = (family<<12) | (model<<4) | (stepping); - print_debug("converted:"); print_debug_hex32(valx); print_debug("\n"); + family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff); + model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0); + stepping = val & 0x0f; + valx = (family << 12) | (model << 4) | (stepping); + switch (valx) { case 0x10000: ret = AMD_DR_A0A; @@ -134,7 +137,21 @@ case 0x10002: ret = AMD_DR_A2; break; + case 0x10020: + ret = AMD_DR_B0; + break; + case 0x10021: + ret = AMD_DR_B1; + break; + case 0x10022: + ret = AMD_DR_B2; + break; + case 0x10023: + ret = AMD_DR_B3; + break; default: + /* FIXME: mabe we should die() here. */ + print_err("FIXME! CPU Version unknown or not supported! \n"); ret = 0; } Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-22 20:19:53 UTC (rev 3247) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/AsPsDefs.h 2008-04-22 22:11:31 UTC (rev 3248) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,14 +21,6 @@ #ifndef ASPSDEFS_H #define ASPSDEFS_H -/* AMD Platform Types */ -#define AMD_PTYPE_DSK 1 -#define AMD_PTYPE_MOB 2 -#define AMD_PTYPE_SVR 4 -#define AMD_PTYPE_DC 8 -#define AMD_PTYPE_MC 0x10 -#define AMD_PTYPE_UMA 0x20 - #define APIC_BAR 0x1b /* APIC_BAR register */ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-04-22 20:19:53 UTC (rev 3247) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-04-22 22:11:31 UTC (rev 3248) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -60,6 +60,7 @@ #define NODE_MP(x) NODE_PCI(x,1) #define NODE_MC(x) NODE_PCI(x,3) #define NODE_LC(x) NODE_PCI(x,4) + static u32 get_nodes(void) { device_t dev; @@ -75,27 +76,7 @@ return nodes; } -static void enable_apic_ext_id(u32 node) -{ - u32 val; - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); -} - -static void setup_link_trans_cntrl() -{ - /* FIXME: Not sure that this belongs here but it is HT related */ - u32 val; - val = pci_read_config32(NODE_HT(0), 0x68); - val |= 0x00206800; // DSNpReqLimit, LimitCldtCfg, BufRefPri, RespPassPW per BKDG; - pci_write_config32(NODE_HT(0), 0x68, val); -} - - - - /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) * Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2008-04-22 20:19:53 UTC (rev 3247) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2008-04-22 22:11:31 UTC (rev 3248) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ + /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ #define AMD_SAFEMODE 0x80000000 /* Unknown future revision - SAFE MODE */ #define AMD_NPT_F0 0x00000001 /* F0 stepping */ @@ -37,33 +39,83 @@ #define AMD_DR_B1 0x00100000 /* Barcelona B1 */ #define AMD_DR_B2 0x00200000 /* Barcelona B2 */ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ +#define AMD_DR_B3 0x00800000 /* Barcelona B3 */ /* - Groups - Create as many as you wish, from the above public values -*/ -#define AMD_NPT_F2 (AMD_NPT_F2C + AMD_NPT_F2D + AMD_NPT_F2E + AMD_NPT_F2G + AMD_NPT_F2J + AMD_NPT_F2K) + * Groups - Create as many as you wish, from the above public values + */ +#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) #define AMD_NPT_F3 (AMD_NPT_F3L) -#define AMD_NPT_Fx (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2 + AMD_NPT_F3) -#define AMD_NPT_Gx (AMD_NPT_G0A + AMD_NPT_G1B) -#define AMD_NPT_ALL (AMD_NPT_Fx + AMD_NPT_Gx) +#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) +#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) +#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) +#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) +#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) #define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) -#define AMD_FINEDELAY (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2) -#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) +#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) +#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) +#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) +#define AMD_DR_ALL (AMD_DR_Bx) +/* + * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE + */ +#define AMD_PTYPE_DSK 0x001 /* Desktop/DTR/UP */ +#define AMD_PTYPE_MOB 0x002 /* Mobile/Cool-n-quiet */ +#define AMD_PTYPE_SVR 0x004 /* Workstation/Server/Multicore DT */ +#define AMD_PTYPE_UC 0x008 /* Single Core */ +#define AMD_PTYPE_DC 0x010 /* Dual Core */ +#define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */ +#define AMD_PTYPE_UMA 0x040 /* UMA required */ -#define CPUID_EXT_PM 0x80000007 + /* + * Groups - Create as many as you wish, from the above public values + */ +#define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */ -#define CPUID_MODEL 1 +/* + * CPU PCI HT PHY REGISTER, LINK TYPES - PRIVATE + */ +#define HTPHY_LINKTYPE_HT3 0x00000001 +#define HTPHY_LINKTYPE_HT1 0x00000002 +#define HTPHY_LINKTYPE_COHERENT 0x00000004 +#define HTPHY_LINKTYPE_NONCOHERENT 0x00000008 +#define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT) +#define HTPHY_LINKTYPE_GANGED 0x00000010 +#define HTPHY_LINKTYPE_UNGANGED 0x00000020 +#define HTPHY_LINKTYPE_ALL 0x7FFFFFFF -#define HWCR 0xC0010015 +/* + * CPU HT PHY REGISTERS, FIELDS, AND MASKS + */ +#define HTPHY_OFFSET_MASK 0xE00001FF +#define HTPHY_WRITE_CMD 0x40000000 +#define HTPHY_IS_COMPLETE_MASK 0x80000000 +#define HTPHY_DIRECT_MAP 0x20000000 +#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF -#define FidVidStatus 0xC0010042 - +/* + * Various AMD MSRs + */ +#define CPUID_EXT_PM 0x80000007 +#define CPUID_MODEL 1 +#define MCG_CAP 0x00000179 + #define MCG_CTL_P 8 +#define MC0_CTL 0x00000400 +#define MC0_STA MC0_CTL + 1 #define FS_Base 0xC0000100 - - +#define SYSCFG 0xC0010010 +#define HWCR 0xC0010015 +#define NB_CFG 0xC001001F +#define FidVidStatus 0xC0010042 +#define MC4_CTL_MASK 0xC0010048 +#define OSVW_ID_Length 0xC0010140 +#define OSVW_Status 0xC0010141 +#define CPUIDFEATURES 0xC0011004 +#define LS_CFG 0xC0011020 +#define DC_CFG 0xC0011022 #define BU_CFG 0xC0011023 #define BU_CFG2 0xC001102A

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[PATCH] coreinfo: Add dmesg module to display v3 printk buffer
by Uwe Hermann 22 Apr '08

22 Apr '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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coreboot April 2008