coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

Code flow from reset vector
by Viswesh S 26 Mar '08

26 Mar '08

Hi, I understand that in Intel architectures, the reset_vector is at 0xFFFFFFF0 and when I do an nm in coreboot.map I could see this address for reset_vector. I am executing qemu with linux bios. The final binary file is bios.bin or coreboot.rom which is going to be flashed. When I objdump on this file, I dont see the reset_vector address or instruction there.So this might have been stripped of, if we look at the makefile. But as we are using this coreboot.rom file for flashing and the reset_vector is @ 0xFFFFFFF0, how is it possible that we will be writing into the reset_vector location. Is there anything wrong in my understanding. I understand the coreboot.rom is the BIOS code, which comes inside the address mapped in real mode.( 0xA0000 - 0x100000). If that is the case, then how do we write into the address 0xFFFFFFF0, while we flash the BIOS. Thanks, Viswesh ----- Original Message ---- From: "coreboot-request(a)coreboot.org" <coreboot-request(a)coreboot.org> To: coreboot(a)coreboot.org Sent: Tuesday, March 25, 2008 6:33:23 PM Subject: coreboot Digest, Vol 37, Issue 167 Send coreboot mailing list submissions to coreboot(a)coreboot.org To subscribe or unsubscribe via the World Wide Web, visit http://www.coreboot.org/mailman/listinfo/coreboot or, via email, send a message with subject or body 'help' to coreboot-request(a)coreboot.org You can reach the person managing the list at coreboot-owner(a)coreboot.org When replying, please edit your Subject line so it is more specific than "Re: Contents of coreboot digest..." Today's Topics: 1. Re: filo booting cd problem (Peter Stuge) 2. Re: filo booting cd problem (Peter Stuge) 3. Re: Device mapping problem (Klaus Stammermann) ---------------------------------------------------------------------- Message: 1 Date: Tue, 25 Mar 2008 12:28:35 +0100 From: Peter Stuge <peter(a)stuge.se> Subject: Re: [coreboot] filo booting cd problem To: coreboot(a)coreboot.org Message-ID: <20080325112835.8859.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii On Tue, Mar 25, 2008 at 10:15:45AM +0000, Tiago Marques wrote: > Any particular reason for that? Coreboot is not the OS loader if the OS is on a CD. Coreboot is what runs before that loader. An OS loader can be eliminated completely if the OS fits into the boot flash, but so far this is not the typical case. (LAB, Linux-as-Bootloader) > If it is indeed this widespread, it would be something necessary > for a bigger deployment of coreboot than what is possible today. FILO (GRUB2?) are the OS loaders that can load from a CD. If support for the ElTorito extension is needed it should be added there. Sorry I wasn't more clear about this separation in the last post. I should have been more clear since the subject says FILO but the discussion started going toward coreboot. But - ElTorito is needed only for floppy disk emulation. Possibly it can be avoided completely and instead we'll have native support for booting from the CDs that people want to use. (As FILO already does for Linux, and hopefully will do for Windows too once booting Windows in general works well enough.) //Peter ------------------------------ Message: 2 Date: Tue, 25 Mar 2008 12:31:32 +0100 From: Peter Stuge <peter(a)stuge.se> Subject: Re: [coreboot] filo booting cd problem To: coreboot(a)coreboot.org Message-ID: <20080325113132.10168.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii On Mon, Mar 24, 2008 at 08:06:33PM -0400, joe(a)smittys.pointclark.net wrote: > > Try using the real filename on the disc. I don't know how FILO > > deals with ISO9660 extensions, filename casing and such. > > I thought that is what I am doing? > hdc1:/GEEXBOX/boot/vmlinuz initrd=hdc1:/GEEXBOX/boot/initrd.gz > root=/dev/ram0 rw init=linuxrc boot=cdrom installator As you may know, ISO9660 does not support case sensitive filenames, but I do not know if and how FILO will do case conversion. //Peter ------------------------------ Message: 3 Date: Tue, 25 Mar 2008 14:03:14 +0100 (CET) From: "Klaus Stammermann" <klaus123(a)ibnoetzold.de> Subject: Re: [coreboot] Device mapping problem To: coreboot(a)coreboot.org Cc: Stefan Reinauer <stepan(a)coresystems.de> Message-ID: <57122.87.122.18.149.1206450194.squirrel(a)www.ibnoetzold.de> Content-Type: text/plain;charset=iso-8859-1 > Klaus Stammermann wrote: >> Hi there >> >> Booting on my Via EPIA-ME6000 with original BIOS the installed OS starts >> without any problems. But using my coreboot image it got a problem with >> device mapping. >> >> I posted changes on my coreboot config here: >> http://www.coreboot.org/pipermail/coreboot/2008-March/031945.html >> >> At end of that posting there is this error description: >> "But system does not booting at all. I think device mapping works not >> correct. On booting system is checking sda. Some errors like: >> exception Emask ... 0x2 frozen >> soft resetting port... >> configured for UDMA... >> (... are inserted by me because I got this output only on display) >> > > Can you send a full log? > Hi I changed kernel to get serial output. So it is not same error message but I think it is same problem. So this is my boot log: 0 coreboot-2.0.0.0-Fallback Mo 10. M?r 15:34:24 CET 2008 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)00 Starting at CAS 3 We can do CAS 2.5 tRP 3c tRCD 3c tRAS 28 Low Bond 00 High Bondc8 Setting DQS delay85vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 62 32 01 20 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 02 10 80:0f 60 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0.0-Fallback Mo 17. M?r 14:07:30 CET 2008 booting... clocks_per_usec: 1378 Enumerating buses... APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0001 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled PCI: 00:0d.0 [1106/3044] enabled In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable ffff ffff. Disabling static device: PCI: 00:10.3 In vt8235_enable 1106 3177. Initialising Devices Keyboard init... PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable 1106 3068. PCI: 00:11.6 [1106/3068] disabled In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=001 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled PCI: 00:0d.0 [1106/3044] enabled PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3104] enabled PCI: 00:11.0 [1106/3177] enabled PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:11.6 [1106/3068] enabled PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus returning with max=002 done Allocating resources... Reading resources... Done reading resources. Allocating VGA resource PCI: 02:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0001 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... I would set ram size to 0x40000 Kbytes PCI: 00:0d.0 10 <- [0x00febfc000 - 0x00febfc7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000002400 - 0x000000247f] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000002800 - 0x000000281f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002820 - 0x000000283f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002840 - 0x000000285f] size 0x00000020 gran 0x05 io PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io PCI: 00:11.1 20 <- [0x00000028c0 - 0x00000028cf] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febfe000 - 0x00febfe0ff] size 0x00000100 gran 0x08 mem I would set ram size to 0x40000 Kbytes PCI: 00:0d.0 10 <- [0x00febfd000 - 0x00febfd7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000002480 - 0x00000024ff] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000002860 - 0x000000287f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002880 - 0x000000289f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x00000028a0 - 0x00000028bf] size 0x00000020 gran 0x05 io PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] size 0x00000100 gran 0x08 mem PCI: 00:11.1 20 <- [0x00000028d0 - 0x00000028df] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:11.6 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] size 0x00000100 gran 0x08 mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 01:00.0 cmd <- ffff PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 01 PCI: 00:11.0 cmd <- 07 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 02:00.0 cmd <- 03 PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 cmd <- 01 PCI: 00:11.6 cmd <- 01 PCI: 00:12.0 cmd <- 83 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 698 CPU: family 06, model 09, stepping 08 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:11.0 init vt8235 init RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum pci_routing_fixup: dev is 000114c0 setting firewire Assigning IRQ 9 to 0:d.0 Readback = 9 setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 Assigning IRQ 9 to 0:10.1 Readback = 9 Assigning IRQ 9 to 0:10.2 Readback = 9 Assigning IRQ 5 to 0:10.3 Readback = 5 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 Assigning IRQ 9 to 0:11.5 Readback = 9 Assigning IRQ 9 to 0:11.6 Readback = 9 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 setting vga setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x18 enables in reg 0x40 read back as 0x1b enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 biosint: INT# 0x15 biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1a7d4 biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1a7d4 biosint: ip 0x641c cs 0xc000 flags 0x46 biosint: INT# 0x1a biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b biosint: ip 0x40f0 cs 0xc000 flags 0x46 0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5 biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1a7d4 biosint: ip 0x651b cs 0xc000 flags 0x87 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1a7d4 biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112 biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1a7d4 biosint: ip 0x6533 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112 biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6479 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6485 cs 0xc000 flags 0x202 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0001ba18 setting firewire Assigning IRQ 9 to 0:d.0 Readback = 9 setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 Assigning IRQ 9 to 0:10.1 Readback = 9 Assigning IRQ 9 to 0:10.2 Readback = 9 Assigning IRQ 5 to 0:10.3 Readback = 5 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 Assigning IRQ 9 to 0:11.5 Readback = 9 Assigning IRQ 9 to 0:11.6 Readback = 9 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 setting vga setting pci slot setting cardbus slot setting riser slot PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x1b enables in reg 0x40 read back as 0x1b enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8f command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:11.6 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 02:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 biosint: INT# 0x15 biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1c724 biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1c724 biosint: ip 0x641c cs 0xc000 flags 0x46 biosint: INT# 0x1a biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b biosint: ip 0x40f0 cs 0xc000 flags 0x46 0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5 biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1c724 biosint: ip 0x651b cs 0xc000 flags 0x87 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c724 biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112 biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1c724 biosint: ip 0x6533 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112 biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6479 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6485 cs 0xc000 flags 0x202 Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. ACPI: Writing ACPI tables at f0400... ACPI: * FACS ACPI: * DSDT @ 000f04aa Length 3f0 ACPI: * FADT ACPI: added table 1/8 Length now 40 ACPI: done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0c00 to 0x00100000 Wrote coreboot table at: 00000530 - 00000c0c checksum 6b35 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffd0000 - 0xfffd814f Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x22060 offset 0xc0 filesize 0x7e88 (cleaned up) New segment addr 0x100000 size 0x22060 offset 0xc0 filesize 0x7e88 New segment addr 0x122060 size 0x48 offset 0x7f60 filesize 0x48 (cleaned up) New segment addr 0x122060 size 0x48 offset 0x7f60 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000022060 filesz: 0x0000000000007e88 Clearing Segment: addr: 0x0000000000107e88 memsz: 0x000000000001a1d8 Loading Segment: addr: 0x0000000000122060 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x106224 FILO version 0.5 (klausst@thor) Mon Mar 10 15:33:24 CET 2008 No sound device found boot: hda1:/boot/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 hda: LBA 2049MB: SanDisk SDCFX-2048 Mounted ext2fs Found Linux version 2.6.22.9 (root@zenwalk) #1 SMP PREEMPT Sat Sep 29 22:22:07 CEST 2007 bzImage. Loading kernel... ok Jumping to entry point... 0 coreboot-2.0.0.0-Fallback Mo 10. M?r 15:34:24 CET 2008 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)00 Starting at CAS 3 We can do CAS 2.5 tRP 3c tRCD 3c tRAS 28 Low Bond 00 High Bondc8 Setting DQS delay85vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 62 32 01 20 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 02 10 80:0f 60 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0.0-Fallback Mo 17. M?r 14:07:30 CET 2008 booting... clocks_per_usec: 1378 Enumerating buses... APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0001 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled PCI: 00:0d.0 [1106/3044] enabled In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable ffff ffff. Disabling static device: PCI: 00:10.3 In vt8235_enable 1106 3177. Initialising Devices Keyboard init... PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable 1106 3068. PCI: 00:11.6 [1106/3068] disabled In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=001 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled PCI: 00:0d.0 [1106/3044] enabled PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3104] enabled PCI: 00:11.0 [1106/3177] enabled PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:11.6 [1106/3068] enabled PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus returning with max=002 done Allocating resources... Reading resources... Done reading resources. Allocating VGA resource PCI: 02:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0001 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... I would set ram size to 0x40000 Kbytes PCI: 00:0d.0 10 <- [0x00febfc000 - 0x00febfc7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000002400 - 0x000000247f] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000002800 - 0x000000281f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002820 - 0x000000283f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002840 - 0x000000285f] size 0x00000020 gran 0x05 io PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io PCI: 00:11.1 20 <- [0x00000028c0 - 0x00000028cf] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febfe000 - 0x00febfe0ff] size 0x00000100 gran 0x08 mem I would set ram size to 0x40000 Kbytes PCI: 00:0d.0 10 <- [0x00febfd000 - 0x00febfd7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000002480 - 0x00000024ff] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000002860 - 0x000000287f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002880 - 0x000000289f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x00000028a0 - 0x00000028bf] size 0x00000020 gran 0x05 io PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] size 0x00000100 gran 0x08 mem PCI: 00:11.1 20 <- [0x00000028d0 - 0x00000028df] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:11.6 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] size 0x00000100 gran 0x08 mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 01:00.0 cmd <- ffff PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 01 PCI: 00:11.0 cmd <- 07 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 02:00.0 cmd <- 03 PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 cmd <- 01 PCI: 00:11.6 cmd <- 01 PCI: 00:12.0 cmd <- 83 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 698 CPU: family 06, model 09, stepping 08 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:11.0 init vt8235 init RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum pci_routing_fixup: dev is 000114c0 setting firewire Assigning IRQ 9 to 0:d.0 Readback = 9 setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 Assigning IRQ 9 to 0:10.1 Readback = 9 Assigning IRQ 9 to 0:10.2 Readback = 9 Assigning IRQ 5 to 0:10.3 Readback = 5 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 Assigning IRQ 9 to 0:11.5 Readback = 9 Assigning IRQ 9 to 0:11.6 Readback = 9 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 setting vga setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x18 enables in reg 0x40 read back as 0x1b enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 biosint: INT# 0x15 biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1a7d4 biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1a7d4 biosint: ip 0x641c cs 0xc000 flags 0x46 biosint: INT# 0x1a biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b biosint: ip 0x40f0 cs 0xc000 flags 0x46 0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5 biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1a7d4 biosint: ip 0x651b cs 0xc000 flags 0x87 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1a7d4 biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112 biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1a7d4 biosint: ip 0x6533 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112 biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6479 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6485 cs 0xc000 flags 0x202 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0001ba18 setting firewire Assigning IRQ 9 to 0:d.0 Readback = 9 setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 Assigning IRQ 9 to 0:10.1 Readback = 9 Assigning IRQ 9 to 0:10.2 Readback = 9 Assigning IRQ 5 to 0:10.3 Readback = 5 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 Assigning IRQ 9 to 0:11.5 Readback = 9 Assigning IRQ 9 to 0:11.6 Readback = 9 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 setting vga setting pci slot setting cardbus slot setting riser slot PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x1b enables in reg 0x40 read back as 0x1b enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8f command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:11.6 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 02:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 biosint: INT# 0x15 biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1c724 biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1c724 biosint: ip 0x641c cs 0xc000 flags 0x46 biosint: INT# 0x1a biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b biosint: ip 0x40f0 cs 0xc000 flags 0x46 0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5 biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1c724 biosint: ip 0x651b cs 0xc000 flags 0x87 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c724 biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112 biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1c724 biosint: ip 0x6533 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112 biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6479 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6485 cs 0xc000 flags 0x202 Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. ACPI: Writing ACPI tables at f0400... ACPI: * FACS ACPI: * DSDT @ 000f04aa Length 3f0 ACPI: * FADT ACPI: added table 1/8 Length now 40 ACPI: done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0c00 to 0x00100000 Wrote coreboot table at: 00000530 - 00000c0c checksum b963 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffd0000 - 0xfffd814f Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x22060 offset 0xc0 filesize 0x7e88 (cleaned up) New segment addr 0x100000 size 0x22060 offset 0xc0 filesize 0x7e88 New segment addr 0x122060 size 0x48 offset 0x7f60 filesize 0x48 (cleaned up) New segment addr 0x122060 size 0x48 offset 0x7f60 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000022060 filesz: 0x0000000000007e88 Clearing Segment: addr: 0x0000000000107e88 memsz: 0x000000000001a1d8 Loading Segment: addr: 0x0000000000122060 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x106224 FILO version 0.5 (klausst@thor) Mon Mar 10 15:33:24 CET 2008 No sound device found boot: hda1:/boot/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 hda: LBA 2049MB: SanDisk SDCFX-2048 Mounted ext2fs Found Linux version 2.6.18.2-34-default (geeko@buildhost) #1 SMP Mon Nov 27 11:46:27 UTC 2006 bzImage. Loading kernel... ok Jumping to entry point... Linux version 2.6.18.2-34-default (geeko@buildhost) (gcc version 4.1.2 20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006 BIOS-provided physical RAM map: BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 0000000000100000 - 000000000e000000 (usable) 0MB HIGHMEM available. 224MB LOWMEM available. DMI 2.2 present. Using APIC driver default IO/L-APIC disabled because your old system seems to be old overwrite with "apic" ACPI: PM-Timer IO Port: 0x408 Allocating PCI resources starting at 10000000 (gap: 0e000000:f2000000) Detected 599.731 MHz processor. Built 1 zonelists. Total pages: 57344 Kernel command line: root=/dev/hda1 console=tty0 console=ttyS0,115200 Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 PID hash table entries: 1024 (order: 10, 4096 bytes) Console: colour VGA+ 80x25 Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 223532k/229376k available (1697k kernel code, 5384k reserved, 968k data, 196k init, 0k highmem) Checking if this processor honours the WP bit even in supervisor mode... Ok. Calibrating delay using timer specific routine.. 1201.25 BogoMIPS (lpj=2402504) Security Framework v1.0.0 initialized Mount-cache hash table entries: 512 CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) CPU: L2 Cache: 64K (32 bytes/line) Compat vDSO mapped to ffffe000. Checking 'hlt' instruction... OK. SMP alternatives: switching to UP code Freeing SMP alternatives: 16k freed ACPI: Core revision 20060707 ACPI: setting ELCR to 0020 (from 0220) CPU0: Centaur VIA Nehemiah stepping 08 SMP motherboard not detected. Local APIC not detected. Using dummy APIC emulation. Brought up 1 CPUs migration_cost=0 NET: Registered protocol family 16 ACPI: bus type pci registered PCI: PCI BIOS revision 2.10 entry at 0xfb260, last bus=1 PCI: Using configuration type 1 Setting up standard PCI resources irq 5: nobody cared (try booting with the "irqpoll" option) [<c0146772>] __report_bad_irq+0x36/0x7d [<c0146968>] note_interrupt+0x1af/0x1eb [<c01ea916>] acpi_ev_sci_xrupt_handler+0x12/0x19 [<c01e5562>] acpi_irq+0xb/0x14 [<c0145ed6>] handle_IRQ_event+0x23/0x49 [<c0145fb5>] __do_IRQ+0xb9/0xee [<c01067aa>] do_IRQ+0x71/0x83 [<c0104e1a>] common_interrupt+0x1a/0x20 [<c0124db8>] __do_softirq+0x51/0xbb [<c0124e58>] do_softirq+0x36/0x3a [<c01067af>] do_IRQ+0x76/0x83 [<c0104e1a>] common_interrupt+0x1a/0x20 [<c01465a2>] setup_irq+0x132/0x190 [<c01e5557>] acpi_irq+0x0/0x14 [<c014667c>] request_irq+0x7c/0x98 [<c01ea904>] acpi_ev_sci_xrupt_handler+0x0/0x19 [<c01e5b96>] acpi_os_install_interrupt_handler+0x60/0x8d [<c01e5557>] acpi_irq+0x0/0x14 [<c01e9ff0>] acpi_ev_install_xrupt_handlers+0x9/0x61 [<c01ea429>] acpi_ev_install_region_handlers+0x62/0x69 [<c01fb792>] acpi_enable_subsystem+0x86/0xa6 [<c03b7afd>] acpi_init+0x54/0x1f2 [<c0226b45>] class_create+0x40/0x56 [<c03b61ce>] fbmem_init+0x5b/0x86 [<c0100414>] init+0x118/0x2bc [<c0103ca6>] ret_from_fork+0x6/0x20 [<c01002fc>] init+0x0/0x2bc [<c01002fc>] init+0x0/0x2bc [<c0102005>] kernel_thread_helper+0x5/0xb handlers: [<c01e5557>] (acpi_irq+0x0/0x14) Disabling IRQ #5 ACPI: Interpreter enabled ACPI: Using PIC for interrupt routing ACPI: PCI Interrupt Link [LNKA] (IRQs *5 9 10) ACPI: PCI Interrupt Link [LNKB] (IRQs 5 *9 10) ACPI: PCI Interrupt Link [LNKC] (IRQs 5 *9 10) ACPI: PCI Interrupt Link [LNKD] (IRQs *5 9 10) ACPI: PCI Root Bridge [PCI0] (0000:00) PCI quirk: region 0400-047f claimed by vt8235 PM PCI quirk: region 0f00-0f0f claimed by vt8235 SMB Linux Plug and Play Support v0.97 (c) Adam Belay pnp: PnP ACPI init pnp: PnP ACPI: found 0 devices PnPBIOS: Disabled by ACPI PNP PCI: Using ACPI for IRQ routing PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report PCI: Device 0000:02:00.0 not found by BIOS PCI: Bridge: 0000:00:01.0 IO window: disabled. MEM window: dc000000-ddffffff PREFETCH window: d8000000-dbffffff NET: Registered protocol family 2 IP route cache hash table entries: 2048 (order: 1, 8192 bytes) TCP established hash table entries: 8192 (order: 4, 65536 bytes) TCP bind hash table entries: 4096 (order: 3, 32768 bytes) TCP: Hash tables configured (established 8192 bind 4096) TCP reno registered apm: BIOS not found. audit: initializing netlink socket (disabled) audit(1206457002.084:1): initialized Total HugeTLB memory allocated, 0 VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) Initializing Cryptographic API io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) isapnp: Scanning for PnP cards... isapnp: No Plug & Play device found Real Time Clock Driver v1.12ac Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A Floppy drive(s): fd0 is 1.44M FDC 0 is a post-1991 82077 RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize PNP: No PS/2 controller found. Probing ports directly. serio: i8042 AUX port at 0x60,0x64 irq 12 serio: i8042 KBD port at 0x60,0x64 irq 1 mice: PS/2 mouse device common for all mice input: PC Speaker as /class/input/input0 input: AT Translated Set 2 keyboard as /class/input/input1 input: ImExPS/2 Generic Explorer Mouse as /class/input/input2 md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27 md: bitmap version 4.39 NET: Registered protocol family 1 Using IPI No-Shortcut mode ACPI: (supports<6>Time: tsc clocksource has been installed. S0 S5) md: Autodetecting RAID arrays. md: autorun ... md: ... autorun DONE. VFS: Cannot open root device "hda1" or unknown-block(0,0) Please append a correct "root=" boot option Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) ------------------------------ _______________________________________________ coreboot mailing list coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot End of coreboot Digest, Vol 37, Issue 167 ***************************************** ____________________________________________________________________________________ Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ

2 1

nrv2b cleanup patch
by Myles Watson 25 Mar '08

25 Mar '08

This patch changes do_nrv2b_compress to act like do_lzma_compress. In other words, it now allocates and frees its own memory. This saves lar from having to know about worst case compression to avoid memory corruption. Tested by building coreboot with nrv2b as default, then copying to an lzma lar, then copying back to an nrv2b lar. No differences. Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com>

2 3

Re: [coreboot] #4: Directory names in svn should be (mostly) lower-case
by coreboot 25 Mar '08

25 Mar '08

#4: Directory names in svn should be (mostly) lower-case ----------------------------+----------------------------------------------- Reporter: uwe | Owner: somebody Type: enhancement | Status: closed Priority: minor | Milestone: Cosmetic fixes Component: code | Version: v3 Resolution: fixed | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by uwe): * status: new => closed * patchstatus: => there is no patch * resolution: => fixed * version: v2 => v3 Comment: This is fixed in v3 already, and I don't think it makes much sense messing with v2 here anymore. Closing. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/4#comment:6> coreboot <http://www.coreboot.org/>

1 0

Re: [coreboot] #13: Support for Intel 845GE/PE Northbridge
by coreboot 25 Mar '08

25 Mar '08

#13: Support for Intel 845GE/PE Northbridge ----------------------------+----------------------------------------------- Reporter: uwe | Owner: somebody Type: enhancement | Status: closed Priority: major | Milestone: Going mainstream Component: code | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by uwe): * status: new => closed * patchstatus: => there is no patch * resolution: => fixed Comment: Closing. While we still want to support 845GE/PE of course, this ticket is useless. If we'd add a ticket for each chipset we want to support, the tracker would become pretty full pretty soon. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/13#comment:2> coreboot <http://www.coreboot.org/>

1 0

Re: [coreboot] #15: fix abuild for all boards that use the "three images solution
by coreboot 25 Mar '08

25 Mar '08

#15: fix abuild for all boards that use the "three images solution --------------------------+------------------------------------------------- Reporter: anonymous | Owner: yhlu Type: defect | Status: closed Priority: major | Milestone: Component: code | Version: v2 Resolution: fixed | Keywords: abuild Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Changes (by uwe): * status: new => closed * patchstatus: => there is no patch * resolution: => fixed Comment: I think this can be closed as all images build fine in abuild at the moment? Please re-open if the issue is still valid. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/15#comment:3> coreboot <http://www.coreboot.org/>

1 0

r646 - coreboot-v3/util/lzma
by svn＠coreboot.org 25 Mar '08

25 Mar '08

Author: uwe Date: 2008-03-25 20:52:13 +0100 (Tue, 25 Mar 2008) New Revision: 646 Modified: coreboot-v3/util/lzma/minilzma.cc Log: Make util/lzma compile under gcc-4.3.0. Signed-off-by: Klaus Schnass <dev(a)stuffit.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/util/lzma/minilzma.cc =================================================================== --- coreboot-v3/util/lzma/minilzma.cc 2008-03-24 05:59:53 UTC (rev 645) +++ coreboot-v3/util/lzma/minilzma.cc 2008-03-25 19:52:13 UTC (rev 646) @@ -28,8 +28,11 @@ #include <sys/types.h> #include <sys/stat.h> #include <unistd.h> -#include <stdio.h> #include <errno.h> +#include <cstring> +#include <cstdio> +#include <cstdlib> +#include <cctype> #include <vector> #include <algorithm>

1 0

Re: [coreboot] #70: fix util/getpir so that the output will compile
by coreboot 25 Mar '08

25 Mar '08

#70: fix util/getpir so that the output will compile ------------------------------------------------------+--------------------- Reporter: Jon Dufresne <jon.dufresne(a)gmail.com> | Owner: somebody Type: defect | Status: closed Priority: major | Milestone: Component: code | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: patch has been committed ------------------------------------------------------+--------------------- Changes (by uwe): * patchstatus: patch needs review => patch has been committed -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/70#comment:5> coreboot <http://www.coreboot.org/>

1 0

r3189 - trunk/util/getpir
by svn＠coreboot.org 25 Mar '08

25 Mar '08

Author: uwe Date: 2008-03-25 20:43:01 +0100 (Tue, 25 Mar 2008) New Revision: 3189 Modified: trunk/util/getpir/code_gen.c Log: Make the getpir output compile (Closes #70). Signed-off-by: Jon Dufresne <jon.dufresne(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/getpir/code_gen.c =================================================================== --- trunk/util/getpir/code_gen.c 2008-03-24 15:47:49 UTC (rev 3188) +++ trunk/util/getpir/code_gen.c 2008-03-25 19:43:01 UTC (rev 3189) @@ -66,5 +66,10 @@ fprintf(fpir, "\t}\n"); fprintf(fpir, "};\n"); + fprintf(fpir, "\nunsigned long write_pirq_routing_table(unsigned long addr)\n"); + fprintf(fpir, "{\n"); + fprintf(fpir, "\treturn copy_pirq_routing_table(addr);\n"); + fprintf(fpir, "}\n"); + fclose(fpir); }

1 0

Re: [coreboot] Motherboard Support
by Uwe Hermann 25 Mar '08

25 Mar '08

Hi, On Sun, Mar 23, 2008 at 07:06:35AM +0000, brianmorrison2(a)comcast.net wrote: > Northbridge - Intel 865PE > Southbridge - Intel ICH5 This board is not supported yet, and it doesn't look like it can be done anytime soon, sorry. The main problem is that the northbridge (865PE) is not supported. Adding support for a completely new chipset usually takes weeks or months. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

Re: [coreboot] .. Re: .. Re: .. Re: Via epia
by jtd 25 Mar '08

25 Mar '08

On Monday 24 March 2008 09:52 pm, Uwe Hermann wrote: > On Mon, Mar 24, 2008 at 10:54:27AM +0530, jtd wrote: > > > or just under qemu? > > > > Tried qemu after that as there was no serial output. > > The serial port is working correctly with the null modem. > > Which image did you use for QEMU? coreboot v2 or v3? And which > board code? The QEMU "board" or the VIA EPIA? The latter cannot > work obviously, as QEMU doesn't emulate a VIA chipset, but rather > Intel 440BX-like hardware. Ah. Qemu board. So how do we get a "via emulator". Or would some other approach to debugging be more productive. -- Rgds JTD

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coreboot March 2008