coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

Motherboard Support
by brianmorrison2＠comcast.net 23 Mar '08

23 Mar '08

Hello, my name is Brian. I was reading the FAQ page of your website and was told to email to ask if coreboot would work on my system. The following are my specs as best as I can provide them; 1: CPU - Intel Celeron 3.07 GHZ Socket 478 Motherboard - MSI 865PE Neo2-V Northbridge - Intel 865PE Southbridge - Intel ICH5 2: LSPCI #00:00.0 Host bridge: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface \ # (rev 02) # 00:01.0 PCI bridge: Intel Corporation 82865G/PE/P PCI to AGP Controller (rev 02) # 00:1d.0 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 (rev 02) # 00:1d.1 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 (rev 02) # 00:1d.2 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 (rev 02) # 00:1d.3 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 (rev 02) # 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) # 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2) # 00:1f.0 ISA bridge: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge (rev 02) # 00:1f.1 IDE interface: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller (rev 02) # 00:1f.3 SMBus: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller (rev 02) # 00:1f.5 Multimedia audio controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio # Controller (rev 02) # 01:00.0 VGA compatible controller: nVidia Corporation NV44A [GeForce 6200] (rev a1) # 02:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 3: Super I/O Chip - Winbond W8327THF 4: Bios - AMIBIOS CU17 7866 5: Motherboard URL ; http://www.msicomputer.com/product/p_spec.asp?model=865PE_Neo2-V Thank you for your assistance

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Via VT82C686 (A/B) southbridge
by Jacek Chruscik 23 Mar '08

23 Mar '08

Hi, Does anybody know how to deal with this southbridge: VIA VT82c686 I'm trying to port coreboot v.2 for FIC FR33E motherboard, but this southbridge has the superio built in. I don't have any datasheet for this chip. coreboot-v2 has no option for such superio, and all I need to do is to initialize serial port. As a base I used via-epia code. The north is vt8601. So far I generated PIRQ table, modified auto.c to recognize correct southbridge, modified config.lb to initialize devices. There is serial init function in vt82c686 source: static void vt82c686_enable_serial(device_t dev, unsigned iobase) ..... but it requires 2 parameters, which I don't have (called as early serial init from auto.c): static void main(unsigned long bist) { unsigned long x; if (bist == 0) { early_mtrr_init(); } enable_vt8231_serial(); //now it is called as: vt82c686_enable_serial uart_init(); console_init(); .......

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Adding openSUSE flashrom packages to the Coreboot Wiki
by Bernhard Walle 23 Mar '08

23 Mar '08

Hi, can somebody with editing permissions add following information on http://www.coreboot.org/Flashrom: ----------------------------------------------------------------------- openSUSE: $ zypper install coreboot-utils For distributions older than openSUSE Factory (11.0) you find "backports" in the [[http://software.opensuse.org/search?baseproject=ALL&q=coreboot-utils openSUSE Build Service]]. ----------------------------------------------------------------------- Feel free to adjust the information as long as it's still true. :) Bernhard

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qemu v3 etherboot
by Bios 22 Mar '08

22 Mar '08

Yesterday I start v3 on qemu. As payload i used etherboot 5.4.3, it worked fine. http://rom-o-matic.net/5.4.3/build.php?version=5.4.3&F=&arch=i386&nic=ns839… The only trouble is Lar. There the output: --- domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 initialized 0 dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 1 initialized 1 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 1 initialized 1 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 1 initialized 1 dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 1 initialized 1 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 1 initialized 1 dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 1 initialized 1 Stage2 code done. LAR: Attempting to open 'normal/payload'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table LAR: seen member normal/initram/segment0 LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/payload/segment0 LAR: seen member bootblock LAR: File not found! LAR: Attempting to open 'normal/payload/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table LAR: seen member normal/initram/segment0 LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/payload/segment0 LAR: CHECK normal/payload/segment0 @ 0xfffe8850 start 0xfffe88a0 len 24320 reallen 24320 compression 0 entry 0x000100b0 loadaddress 0x00010000 LAR: Compression algorithm #0 (none) used LAR: Attempting to open 'normal/payload/segment1'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table LAR: seen member normal/initram/segment0 LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/payload/segment0 LAR: seen member bootblock LAR: File not found! LAR: load_file: No such file 'normal/payload/segment1' LAR: load_file_segments: All loaded, entry 0x000100b0 CPU 1338 Mhz Etherboot 5.4.3 (GPL) http://etherboot.org --- How can i solve this? Regards Markus

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Igel Thinclient tk 3000
by Markus 22 Mar '08

22 Mar '08

Today i was able to boot via etherboot 5.4.3 coreboot v2. But only with irqpoll. So i generate with getpir a irq_tables.c. I use the axus/tc320 as sample. So i copied the irq_tables.c to src/mainboard/axus/tc320 but after i can't compile any more. gcc -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot_ram -T /home/ryven/Linuxbios/coreboot-v2/src/config/coreboot_ram.ld coreboot_ram.o coreboot_ram.o: In function `write_tables': (.text+0x26f2): undefined reference to `write_pirq_routing_table' collect2: ld returned 1 exit status make[1]: *** [coreboot_ram] Fehler 1 make[1]: Leaving directory `/home/ryven/Linuxbios/coreboot-v2/targets/axus/tc320/tc320/normal' make: *** [normal/coreboot.rom] Fehler 1 So how is the right way? Regards Markus

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New Site Set-Top-Linux (formerly RM4100 Customizing)
by joe＠smittys.pointclark.net 22 Mar '08

22 Mar '08

Hello, We have a new website! As interests grew for other set-top-boxes I would like to introduce you to the new website Set-Top-Linux. There is currently support for 4 different set-top-boxes (RCA RM4100, RCA Akimbo IP1150, Thomson IP1000 Series, and Akimbo AP1200), and room to expand. It is setup with a new Wiki and forum. I would like everyone to take a few minutes out of your day to come and visit:-) Feedback is welcome. http://www.smittys.pointclark.net/stl/index.php What does this have to do with coreboot, you ask? Everything, My goal is to get coreboot running on all four of these boxes, 1 almost down, 3 to go. I have my work cut out for me..... BTW - I update any links on the coreboot wiki to point to the new site. Thanks - Joe

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[PATCH] [libpayload] VGA driver cursor placement and scrolling fixes
by Jonathan A. Kollasch 22 Mar '08

22 Mar '08

* Make cursor positioning work by using both halves of the VGA cursor position register. * Have vga_scroll_up() and vga_clear_line() present row/column arguments to the VIDEO() macro in the right order. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> ---

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r3186 - trunk/payloads/libpayload/drivers
by svn＠coreboot.org 22 Mar '08

22 Mar '08

Author: jcrouse Date: 2008-03-22 16:27:26 +0100 (Sat, 22 Mar 2008) New Revision: 3186 Modified: trunk/payloads/libpayload/drivers/vga.c Log: Make cursor positioning work by using both halves of the VGA cursor position register. Have vga_scroll_up() and vga_clear_line() present row/column arguments to the VIDEO() macro in the right order. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> -This line, and those below, will be ignored-- M libpayload/drivers/vga.c Modified: trunk/payloads/libpayload/drivers/vga.c =================================================================== --- trunk/payloads/libpayload/drivers/vga.c 2008-03-21 18:37:23 UTC (rev 3185) +++ trunk/payloads/libpayload/drivers/vga.c 2008-03-22 15:27:26 UTC (rev 3186) @@ -64,7 +64,7 @@ unsigned int addr; addr = ((unsigned int)crtc_read(0x0E)) << 8; - addr += crtc_read(0x0E); + addr += crtc_read(0x0F); cursorx = addr % WIDTH; cursory = addr / WIDTH; @@ -93,7 +93,7 @@ addr = cursorx + (WIDTH * cursory); crtc_write(addr >> 8, 0x0E); - crtc_write(addr, 0x0E); + crtc_write(addr, 0x0F); } void vga_cursor_enable(int state) @@ -115,7 +115,7 @@ void vga_clear_line(uint8_t row, uint8_t ch, uint8_t attr) { int col; - uint16_t *ptr = VIDEO(0, row); + uint16_t *ptr = VIDEO(row, 0); for (col = 0; col < WIDTH; col++) ptr[col] = ((attr & 0xFF) << 8) | (ch & 0xFF); @@ -123,7 +123,7 @@ static void vga_scroll_up(void) { - uint16_t *src = VIDEO(0, 1); + uint16_t *src = VIDEO(1, 0); uint16_t *dst = VIDEO(0, 0); int i;

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libpayload link address
by Jonathan A. Kollasch 22 Mar '08

22 Mar '08

Hi, I notice the ldscript for libpayload places the payload at 0x100000. This may not be a good idea, as this is the usual location to load the OS kernel. Jonathan Kollasch

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Re: [coreboot] #87: flashrom issues on m57sli-s4
by coreboot 22 Mar '08

22 Mar '08

#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: closed Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Comment (by anonymous): 徐州辉煌钢结构工程有限公司是一家集[http://www.hhgwj.cn/ 网架]钢结构设计、制作、安装及技术服务为一体的大型专业化企业。公司坐落于有网架之乡美誉的江苏省徐州市，这里是全国优质网架原材料供应基地，也是全国网架技术熟练工人培训基地，有着人才，技术和原材料的地域优势。企业创办多年来，本着"求实创新、开拓进取"的精神，不断引进吸收国内外先进技术经验，汇集来自全国各地从事专业管理，专业设计、制造、检测试验等高级优秀人才，配置了各种先进的成套生产和检测设备，能满足制造生产能力要求的流水生产线。公司始终本着“诚信为本、信守合同、用户至上”的理念，坚持贯彻实践三个“第一”——质量第一、信誉第一，服务第一，企业不断深化改革，深挖潜力，降低成本，以最低的价格吸引客户，以最好的质量服务客户，让辉煌网架钢构建设遍布全国各地，多年来深受广大客户及建设单位的一致好评。　　竭诚欢迎各界新老朋友真诚合作、共创辉煌、共享绩效，公司将一如既往地为各界朋友提供优秀的服务！ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/87#comment:7> coreboot <http://www.coreboot.org/>

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coreboot March 2008