coreboot March 2008

coreboot@coreboot.org

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r3135 build service
by coreboot information 12 Mar '08

12 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3135 to the coreboot source repository and caused the following changes: Change Log: Formatting fixes, no content changes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3135&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3135&device=rm4100&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3135 - trunk/coreboot-v2/src/cpu/amd/model_fxx
by svn＠coreboot.org 12 Mar '08

12 Mar '08

Author: uwe Date: 2008-03-13 00:18:04 +0100 (Thu, 13 Mar 2008) New Revision: 3135 Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c Log: Formatting fixes, no content changes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2008-03-12 12:28:40 UTC (rev 3134) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2008-03-12 23:18:04 UTC (rev 3135) @@ -560,73 +560,75 @@ static struct device_operations cpu_dev_ops = { .init = model_fxx_init, }; + static struct cpu_device_id cpu_table[] = { #if K8_REV_F_SUPPORT == 0 - { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ - { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ - { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ - { X86_VENDOR_AMD, 0xf58 }, /* SH-C0 (socket 940) */ - { X86_VENDOR_AMD, 0xf48 }, /* SH-C0 (socket 754) */ - { X86_VENDOR_AMD, 0xf5a }, /* SH-CG (socket 940) */ - { X86_VENDOR_AMD, 0xf4a }, /* SH-CG (socket 754) */ - { X86_VENDOR_AMD, 0xf7a }, /* SH-CG (socket 939) */ - { X86_VENDOR_AMD, 0xfc0 }, /* DH-CG (socket 754) */ - { X86_VENDOR_AMD, 0xfe0 }, /* DH-CG (socket 754) */ - { X86_VENDOR_AMD, 0xff0 }, /* DH-CG (socket 939) */ - { X86_VENDOR_AMD, 0xf82 }, /* CH-CG (socket 754) */ - { X86_VENDOR_AMD, 0xfb2 }, /* CH-CG (socket 939) */ + { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ + { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ + { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ + { X86_VENDOR_AMD, 0xf58 }, /* SH-C0 (socket 940) */ + { X86_VENDOR_AMD, 0xf48 }, /* SH-C0 (socket 754) */ + { X86_VENDOR_AMD, 0xf5a }, /* SH-CG (socket 940) */ + { X86_VENDOR_AMD, 0xf4a }, /* SH-CG (socket 754) */ + { X86_VENDOR_AMD, 0xf7a }, /* SH-CG (socket 939) */ + { X86_VENDOR_AMD, 0xfc0 }, /* DH-CG (socket 754) */ + { X86_VENDOR_AMD, 0xfe0 }, /* DH-CG (socket 754) */ + { X86_VENDOR_AMD, 0xff0 }, /* DH-CG (socket 939) */ + { X86_VENDOR_AMD, 0xf82 }, /* CH-CG (socket 754) */ + { X86_VENDOR_AMD, 0xfb2 }, /* CH-CG (socket 939) */ -//AMD_D0_SUPPORT + /* AMD D0 support */ { X86_VENDOR_AMD, 0x10f50 }, /* SH-D0 (socket 940) */ { X86_VENDOR_AMD, 0x10f40 }, /* SH-D0 (socket 754) */ { X86_VENDOR_AMD, 0x10f70 }, /* SH-D0 (socket 939) */ - { X86_VENDOR_AMD, 0x10fc0 }, /* DH-D0 (socket 754) */ - { X86_VENDOR_AMD, 0x10ff0 }, /* DH-D0 (socket 939) */ - { X86_VENDOR_AMD, 0x10f80 }, /* CH-D0 (socket 754) */ - { X86_VENDOR_AMD, 0x10fb0 }, /* CH-D0 (socket 939) */ + { X86_VENDOR_AMD, 0x10fc0 }, /* DH-D0 (socket 754) */ + { X86_VENDOR_AMD, 0x10ff0 }, /* DH-D0 (socket 939) */ + { X86_VENDOR_AMD, 0x10f80 }, /* CH-D0 (socket 754) */ + { X86_VENDOR_AMD, 0x10fb0 }, /* CH-D0 (socket 939) */ -//AMD_E0_SUPPORT - { X86_VENDOR_AMD, 0x20f50 }, /* SH-E0 */ - { X86_VENDOR_AMD, 0x20f40 }, - { X86_VENDOR_AMD, 0x20f70 }, - { X86_VENDOR_AMD, 0x20fc0 }, /* DH-E3 (socket 754) */ - { X86_VENDOR_AMD, 0x20ff0 }, /* DH-E3 (socket 939) */ - { X86_VENDOR_AMD, 0x20f10 }, /* JH-E1 (socket 940) */ - { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 (socket 940) */ - { X86_VENDOR_AMD, 0x20f71 }, /* SH-E4 (socket 939) */ - { X86_VENDOR_AMD, 0x20fb1 }, /* BH-E4 (socket 939) */ - { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 (socket 754) */ - { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 (socket 939) */ - { X86_VENDOR_AMD, 0x20fc2 }, /* DH-E6 (socket 754) */ - { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 (socket 940) */ - { X86_VENDOR_AMD, 0x20f32 }, /* JH-E6 (socket 939) */ + /* AMD E0 support */ + { X86_VENDOR_AMD, 0x20f50 }, /* SH-E0 */ + { X86_VENDOR_AMD, 0x20f40 }, + { X86_VENDOR_AMD, 0x20f70 }, + { X86_VENDOR_AMD, 0x20fc0 }, /* DH-E3 (socket 754) */ + { X86_VENDOR_AMD, 0x20ff0 }, /* DH-E3 (socket 939) */ + { X86_VENDOR_AMD, 0x20f10 }, /* JH-E1 (socket 940) */ + { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 (socket 940) */ + { X86_VENDOR_AMD, 0x20f71 }, /* SH-E4 (socket 939) */ + { X86_VENDOR_AMD, 0x20fb1 }, /* BH-E4 (socket 939) */ + { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 (socket 754) */ + { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 (socket 939) */ + { X86_VENDOR_AMD, 0x20fc2 }, /* DH-E6 (socket 754) */ + { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 (socket 940) */ + { X86_VENDOR_AMD, 0x20f32 }, /* JH-E6 (socket 939) */ { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif #if K8_REV_F_SUPPORT == 1 -//AMD_F0_SUPPORT - { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 Socket F (1207): Opteron */ - { X86_VENDOR_AMD, 0x40f70 }, /* AM2: Athlon64/Athlon64 FX */ - { X86_VENDOR_AMD, 0x40f40 }, /* S1g1: Mobile Athlon64 */ - { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 Socket F (1207): Opteron Dual Core */ - { X86_VENDOR_AMD, 0x40f31 }, /* AM2: Athlon64 x2/Athlon64 FX Dual Core */ - { X86_VENDOR_AMD, 0x40f01 }, /* S1g1: Mobile Athlon64 */ - { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 Socket F (1207): Opteron Dual Core */ - { X86_VENDOR_AMD, 0x40f32 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ - { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */ - { X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */ - { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */ - { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 Socket AM2: Athlon64 */ - { X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */ - { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */ - { X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ - { X86_VENDOR_AMD, 0xc0f13 }, /* AM2 : Athlon64 FX*/ - { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 Socket AM2: Athlon64 */ - { X86_VENDOR_AMD, 0x60fb1 }, /* Socket AM2: Athlon64 x2 5000+*/ + { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 (socket F/1207) */ + { X86_VENDOR_AMD, 0x40f70 }, /* SH-F0 (socket AM2) */ + { X86_VENDOR_AMD, 0x40f40 }, /* SH-F0 (socket S1g1) */ + { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 (socket F/1207) */ + { X86_VENDOR_AMD, 0x40f31 }, /* JH-F1 (socket AM2) */ + { X86_VENDOR_AMD, 0x40f01 }, /* JH-F1 (socket S1g1) */ + + { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 (socket F/1207) */ + { X86_VENDOR_AMD, 0x40f32 }, /* JH-F2 (socket AM2) */ + { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 (socket AM2) */ + { X86_VENDOR_AMD, 0x40f82 }, /* BH-F2 (socket S1g1) */ + { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 (socket AM2) */ + { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 (socket AM2) */ + { X86_VENDOR_AMD, 0x40fc2 }, /* DH-F2 (socket S1g1) */ + { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 (socket F/1207) */ + { X86_VENDOR_AMD, 0x40f33 }, /* JH-F3 (socket AM2) */ + { X86_VENDOR_AMD, 0xc0f13 }, /* JH-F3 (socket F/1207) */ + { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 (socket AM2) */ + { X86_VENDOR_AMD, 0x60fb1 }, /* BH-G1 (socket AM2) */ #endif { 0, 0 }, }; + static const struct cpu_driver model_fxx __cpu_driver = { .ops = &cpu_dev_ops, .id_table = cpu_table,

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Re: [coreboot] Possible support for Lippert Cool LiteRunner
by Martin Trautmann 12 Mar '08

12 Mar '08

In-Reply-To: <47D7CFC6.5070203(a)gmx.net> On 2008-03-12 13:42, Carl-Daniel Hailfinger wrote: > On 12.03.2008 06:53, Martin Trautmann wrote: >> Jordan Crouse wrote: >> >>> There are some other people on this list who are also interested in >>> supporting the GX and 5535, I'll let them speak up. >>> >> >> Here I am. Personally, I got some major trouble how to understand coreboot: >> >> - Migration from v2 to v3: Is there any help and docu how code should be >> ported from v2 to v3 - or is v3 that much cleaner (that means completely >> new and different) so that it would be better to write new code from >> scratch? >> > > Reading the design document in the v3 tree and the mainboard specific > code for one mainboard will give you a pretty good overview of the v3 > structure (and to some extent, code quality). Ah, thanks. I checked http://www.coreboot.org/Documentation#Port_Guides - v2/v1 only http://www.coreboot.org/Development_Guidelines - general only http://www.coreboot.org/Developer_Manual - "It currently covers coreboot v2" http://www.coreboot.org/Coreboot_Options - does not name a version, but http://www.coreboot.org/Welcome_to_coreboot references it as [[corebootv2 Options]] http://coreboot.org/viewvc/trunk/ shows v1 and v2 only http://www.coreboot.org/Download_coreboot names "There is an archive of snapshots available at qa.coreboot.org" - which is v2 only!? I may obtain v3 docu by subversion only? I had checked coreboot-v3/doc/ which does not hold that much info. It's mainly a newboot.lyx Did I miss the essential v3 docu anywhere, e.g. as .pdf? > The architecture of v3 is completely different from v2 and porting means > a lot of refactoring. Depending on how baroque the old code is, you > might want to work from existing v3 code instead (this is especially > true for GX and CS5535 code). I hope so - but the only info I know up to now are the makefiles for coreboot-v3/ -> northbridge/amd/geodelx/ southbridge/amd/cs5536/ arch/x86/ -> geodelx and probably several from mainboard/ according to http://www.coreboot.org/Supported_Motherboards#Motherboards_supported_in_co… There's one so called tutorial http://www.coreboot.org/PC_Engines_ALIX1.C_Build_Tutorial which does not teach me very much. The best I found is http://www.coreboot.org/AMD_Geode_Porting_Guide ... but that's still far away from any docu that would teach me how to build a new port for v3. >> - Hardware info: would I need the circuit plans of a board in order to >> know what is available? I got e.g. several ports on my board which could >> be GPIO, LPC, LVDS, ... >> > > In theory, all those settings should be done in the mainboard dts. > However, there may be some settings which can not yet be done in the dts > and the recommended course of action would be to make them dts-aware. > Having board schematics eases porting somewhat, but most of the board > bringup (except specialized functions like those you mentioned and IRQ > routing) should be easily doable without schematics. That's what I hope for the first steps... >> - BIOS decompiler: Is there any BIOS decompiler which would tell me the >> current operations which have to be done? >> > > There are some tools to analyze proprietary BIOS images, but the person > doing the analysis is not allowed to use the results to write code > because it would violate clean room principles. The best advice I can > give is to avoid touching/analyzing proprietary BIOS code/images, > especially if hardware documentation is readily available. There's much of docu (too much for the beginning) for the GX2 and CS5535, but none for its bios and this special board from AMD. I got two other higher priority tasks at the moment (new born baby and a house to build), but I hope that I may find some time to learn more here. Any help is welcome where to look first for a starting point of v3. Thanks, Martin -- GMX startet ShortView.de. Hier findest Du Leute mit Deinen Interessen! Jetzt dabei sein: http://www.shortview.de/?mc=sv_ext_mf@gmx

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Problems with VIA EPIA-ME6000
by Klaus Stammermann 12 Mar '08

12 Mar '08

Hi there I have some trouble to use coreboot on my VIA EPIA-ME6000 so I hope someone could give me some hints. With epia-m and filo I can build a bios without vga. This runs till jumping to kernel. This breaks up with an error: Loading kernel... ok "Jumping to entry point... 0 coreboot-2.0.0.0-Fallback Mo 18. Feb 16:59:57 CET 2008 starting..." I tried with a PCI-VGA-card, "option CONFIG_CONSOLE_VGA = 1" and "option CONFIG_PCI_ROM_RUN=1". This breaks up with this error: "INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=102b, did=519 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0xa0 Unexpected Exception: 13 @ 10:00013808 - Halting Code: 0 eflags: 00010002 eax: 00000011 ebx: 000247d4 ecx: 00023f8c edx: 00024a70 edi: 0001a4b0 esi: 00024a70 ebp: 00023f54 esp: 00023f54" And using VGA-support with onboard device I get this message: "DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 BAD SIGNATURE 0x7f 0x45 Unexpected Exception: 13 @ 10:000130fe - Halting Code: 0 eflags: 00010006 eax: 00000000 ebx: 000247d4 ecx: 80010030 edx: 00000cfc edi: 0001a4b0 esi: 000247d4 ebp: 00023f8c esp: 00023f6c" What do I have to do to boot with a VGA-card? Are there any options which have to be set? Else, using onboard vga device I got the vga-bios by PERL-script (www.coreboot.org/VGA_support). Is it right this vga bios has to be insert in front of coreboot image? Should it be 64k big or just as big as it is in original? And on which adresses the parts of vga-bios, normal and fallback (with there payload) have to be set? Does anyone use this board with coreboot too? Could some show a Config-file for this so I may see my mistakes?

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r3134 build service
by coreboot information 12 Mar '08

12 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3134 to the coreboot source repository and caused the following changes: Change Log: Drop the useless rom.layout file. It's just an example, likely never been used in the last few years, and the contents are available in the README already anyway. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3134&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3134&device=rm4100&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3133 build service
by coreboot information 12 Mar '08

12 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3133 to the coreboot source repository and caused the following changes: Change Log: Add --list-supported option to flashrom which lists the supported ROM chips, chipsets, and mainboards (Closes #90). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3133&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3133&device=rm4100&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Possible support for Lippert Cool LiteRunner
by Frans Grotepass 12 Mar '08

12 Mar '08

Hi all, We use the Lippert Cool LiteRunner in a commercial application. The POST times of the Lippert BIOS is DISMAL to say the least. The embedded system takes 11 seconds to the lilo/grub stage. I noticed that the Cool FrontRunner has some work completed, although it is not listed as a working board. The Frontrunner is basically a LiteRunner with some extra features. Our company are considering the possibilties for a new BIOS. The following questions come to mind: Option 1: We hack coreboot. * What will this entail in work? We have some experience and equipment in house for the job. * What do we require to make life easy for us? (tools etc) Option 2: We pay someone to hack coreboot for us. * Is there someone that can do this for us? * What will this cost? Option 3: An alternative to coreboot? * Is there an alternative?? Option 4: /*Not really an option*/ We buy in one of the commercial bios solutions Best regards, Frans

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Re: [coreboot] #90: Add --list-supported option
by coreboot 12 Mar '08

12 Mar '08

#90: Add --list-supported option ----------------------------+----------------------------------------------- Reporter: uwe | Owner: somebody Type: enhancement | Status: closed Priority: major | Milestone: Enhance the flashrom utility Component: flashrom | Version: Resolution: fixed | Keywords: Dependencies: | Patchstatus: patch has been committed ----------------------------+----------------------------------------------- Changes (by uwe): * patchstatus: there is no patch => patch has been committed -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/90#comment:2> coreboot <http://www.coreboot.org/>

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[PATCH] flashrom: Drop rom.layout
by Uwe Hermann 12 Mar '08

12 Mar '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r3134 - trunk/util/flashrom
by svn＠coreboot.org 12 Mar '08

12 Mar '08

Author: uwe Date: 2008-03-12 13:28:40 +0100 (Wed, 12 Mar 2008) New Revision: 3134 Removed: trunk/util/flashrom/rom.layout Log: Drop the useless rom.layout file. It's just an example, likely never been used in the last few years, and the contents are available in the README already anyway. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ward Vandewege <ward(a)gnu.org> Deleted: trunk/util/flashrom/rom.layout =================================================================== --- trunk/util/flashrom/rom.layout 2008-03-12 11:54:51 UTC (rev 3133) +++ trunk/util/flashrom/rom.layout 2008-03-12 12:28:40 UTC (rev 3134) @@ -1,3 +0,0 @@ -00000000:00008fff gfxrom -00009000:0003ffff normal -00040000:0007ffff fallback

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coreboot March 2008