coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

Re: [coreboot] [LinuxBIOS] abit be6
by Jouni Mettälä 08 Feb '08

08 Feb '08

On Jan 14, 2008 5:30 PM, Jouni Mettälä <jtmettala(a)gmail.com> wrote: > > > On Jan 14, 2008 4:25 PM, Uwe Hermann <uwe(a)hermann-uwe.de> wrote: > > > On Sun, Jan 13, 2008 at 09:08:17PM +0200, Jouni Mettälä wrote: > > > It now boots with filo. This time with different filo Config file. # > > means > > > these lines were commented out. > > > > What did you change to make FILO boot from your disk? > > > I am not sure if commenting > #SUPPORT_PCI = 1 > #PCI_BRUTE_SCAN = 1 > out or adding > DEBUG_ALL = 1 > or using just fallback image instead of normal and fallback affected this. > > > > > Keyboard isn't working yet. Tested ps/2 keyboard. Using kernel as boot > file > > Does a USB keyboard work? (does the board have onboard-USB?) > > > I'll test USB keyboard as soon as possible (I'll hope today) > > > > > Some of the 440BX boards have problems with the PS/2 keyboard, I haven't > > yet found out if it's superio-related or some more general problem in > > the code somewhere... > > > > > > Please check the patch for the Abit BE6-II V2.0 I just (re)posted. Is > > your board identical to that one or is it really the "BE6" (without > > "II" or "V2.0")? If it's not exactly the same, please post some more > > information about it, e.g. 'lspci -tvnn', 'superiotool -dV', 'flashrom > > -V', > > and the output of 'getpir' (a file called 'irq_table.c'). > > > > ide_search_updated.patch didn't make keyboard working. > There reads ABIT-BE6 without II or V2 > > Files added using original bios. > > > <http://www.unmaintained-free-software.org> > > >

3 10

make LAR parse .bss segments and create LAR entries for them.
by ron minnich 08 Feb '08

08 Feb '08

This patch has LAR create segments for bss. ron

2 1

r580 - coreboot-v3/util/lar
by svn＠coreboot.org 08 Feb '08

08 Feb '08

Author: hailfinger Date: 2008-02-08 13:15:46 +0100 (Fri, 08 Feb 2008) New Revision: 580 Modified: coreboot-v3/util/lar/stream.c Log: Fix lar so that it parses .bss section headers. This is not terribly clean but it works. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested with a qemu boot to work correctly. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/util/lar/stream.c =================================================================== --- coreboot-v3/util/lar/stream.c 2008-02-08 11:57:07 UTC (rev 579) +++ coreboot-v3/util/lar/stream.c 2008-02-08 12:15:46 UTC (rev 580) @@ -74,8 +74,9 @@ int filelen, enum compalgo algo) { int ret; - Elf32_Phdr *phdr; + Elf32_Phdr *phdr; Elf32_Ehdr *ehdr; + Elf32_Shdr *shdr; u32 entry; int i; int size; @@ -121,11 +122,53 @@ ehdr->e_phnum, ehdr->e_shentsize, ehdr->e_shnum); - phdr = (Elf32_Phdr *)&(header[ehdr->e_phoff]); + phdr = (Elf32_Phdr *)&(header[ehdr->e_phoff]); + shdr = (Elf32_Shdr *)&(header[ehdr->e_shoff]); if (verbose()) fprintf(stderr, "%s: header %p #headers %d\n", __FUNCTION__, ehdr, headers); + entry = ehdr->e_entry; + /* bss segments are special. They are in the section headers, + * not program headers. So, sadly, we have to look at section headers. + */ + + for(i = 0; i < ehdr->e_shnum; i++) { + char *p, *q; + /* Ignore data that I don't need to handle */ + if (shdr[i].sh_type != SHT_NOBITS) { + if (verbose()) + fprintf(stderr, "Dropping non SHT_NOBITS section\n"); + continue; + } + /* might need to test flags with SHF_ALLOC */ + if (shdr[i].sh_size == 0) { + if (verbose()) + fprintf(stderr, "Dropping empty section\n"); + continue; + } + thisalgo = algo; + if (verbose()) + fprintf(stderr, "New section addr %#x size %#x\n", + (u32)shdr[i].sh_addr, (u32)shdr[i].sh_size); + /* Clean up the values */ + size = shdr[i].sh_size; + if (verbose()) { + fprintf(stderr, "(cleaned up) New section addr %p size 0x%#x\n", + (void *)shdr[i].sh_addr, (u32)shdr[i].sh_size); + } + /* ok, copy it out */ + sprintf(ename, "%s/segment%d", name, segment++); + /* just allocate a bunch of zeros */ + p = calloc(sizeof(*p), size); + q = calloc(sizeof(*q), size); + complen = lar_compress(p, size, q, &thisalgo); + ret = lar_add_entry(lar, ename, q, complen, size, + shdr[i].sh_addr, entry, thisalgo); + free(p); + free(q); + } + for(i = 0; i < headers; i++) { /* Ignore data that I don't need to handle */ if (phdr[i].p_type != PT_LOAD) {

1 0

FIRST LINUX BOOT: v3 on alix1c!
by ron minnich 08 Feb '08

08 Feb '08

With this patch to FILO: Index: i386/timer.c =================================================================== --- i386/timer.c (revision 35) +++ i386/timer.c (working copy) @@ -105,7 +105,7 @@ return (end - start) * CLOCK_TICK_RATE / (1000*LATCH); } -static unsigned long long cpu_khz; +static unsigned long long cpu_khz = 500000; void setup_timers(void) { if (!cpu_khz) { I just booted linux. First v3 boot on real hardware. There are still problems. Linux is quite busy as revealed by a POST card but we don't seem to get interrupts. Things are not wired correctly. I am attaching the console log as I think this is pretty important for v3 :-) Wow, this was a long haul, but we are very close. Thanks to you all. thanks ron

5 15

r579 - coreboot-v3/device
by svn＠coreboot.org 08 Feb '08

08 Feb '08

Author: hailfinger Date: 2008-02-08 12:57:07 +0100 (Fri, 08 Feb 2008) New Revision: 579 Modified: coreboot-v3/device/device.c Log: Remove the requirement that all ops have a constructor, since many of them just use the default. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-02-07 16:50:44 UTC (rev 578) +++ coreboot-v3/device/device.c 2008-02-08 11:57:07 UTC (rev 579) @@ -126,7 +126,7 @@ for (c = all_constructors[i]; c->ops; c++) { printk(BIOS_SPEW, "%s: cons %p, cons id %s\n", __func__, c, dev_id_string(&c->id)); - if ((!c->ops) || (!c->ops->constructor)) { + if (!c->ops) { continue; } if (id_eq(&c->id, id)) { @@ -182,8 +182,12 @@ c = find_constructor(id); printk(BIOS_SPEW, "%s: constructor is %p\n", __func__, c); - if(c && c->ops && c->ops->constructor) - c->ops->constructor(dev, c); + if(c && c->ops) { + if(c->ops->constructor) + c->ops->constructor(dev, c); + else + default_device_constructor(dev, c); + } else printk(BIOS_INFO, "No constructor called for %s.\n", dev_id_string(&c->id));

1 0

r3098 build service
by coreboot information 08 Feb '08

08 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3098 to the coreboot source repository and caused the following changes: Change Log: Improve error handling and make RCONF_DEFAULT_MSR address be a constant. Also, move a big code comment to the top of enable_flash_cs5536(). Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3098&device=serengeti_chee… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3097 build service
by coreboot information 08 Feb '08

08 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3097 to the coreboot source repository and caused the following changes: Change Log: This implements support for devices using AMD Geode companion chip CS5536 that have the Boot ROM on NOR flash that is directly connected to FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the NORF_CTL MSR register for flashrom to be able to write to it, including JEDEC probe commands. This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on the DBE61. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3097&device=serengeti_chee… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH 2/2] flashrom: cleanups to enable_flash_cs5536 function
by Mart Raudsepp 08 Feb '08

08 Feb '08

Improve error handling and make RCONF_DEFAULT_MSR address be a constant. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- chipset_enable.c | 42 +++++++++++++++++++++++++++++++++++------- 1 files changed, 35 insertions(+), 7 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index d6ef92e..f5a6612 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -228,11 +228,11 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name) static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { - #define MSR_NORF_CTL 0x51400018 + #define MSR_RCONF_DEFAULT 0x1808 + #define MSR_NORF_CTL 0x51400018 int fd_msr; unsigned char buf[8]; - unsigned int addr = 0x1808; /* Geode systems write protect the BIOS via RCONFs (cache * settings similar to MTRRs). To unlock, change MSR 0x1808 @@ -258,41 +258,69 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) perror("open msr"); return -1; } - lseek64(fd_msr, (off64_t) addr, SEEK_SET); - read(fd_msr, buf, 8); + + if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } + + if (read(fd_msr, buf, 8) != 8) { + perror("read"); + close(fd_msr); + return -1; + } printf("Enabling Geode MSR to write to flash.\n"); if (buf[7] != 0x22) { buf[7] &= 0xFB; - lseek64(fd_msr, (off64_t) addr, SEEK_SET); + if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } + if (write(fd_msr, buf, 8) < 0) { perror("msr write"); printf ("Cannot write to MSR. Make sure the msr kernel module is loaded: 'modprobe msr'\n"); + close(fd_msr); return -1; } } - lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } + if (read(fd_msr, buf, 8) != 8) { perror("read msr"); + close(fd_msr); return -1; } /* Raise WE_CS3 bit */ buf[0] |= 0x08; - lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } if (write(fd_msr, buf, 8) < 0) { perror("msr write"); printf ("Cannot write to MSR. Make sure the msr kernel module is loaded: 'modprobe msr'\n"); + close(fd_msr); return -1; } close(fd_msr); + #undef MSR_RCONF_DEFAULT #undef MSR_NORF_CTL return 0; } -- 1.5.4

2 1

r3098 - trunk/util/flashrom
by svn＠coreboot.org 08 Feb '08

08 Feb '08

Author: uwe Date: 2008-02-08 11:10:57 +0100 (Fri, 08 Feb 2008) New Revision: 3098 Modified: trunk/util/flashrom/chipset_enable.c Log: Improve error handling and make RCONF_DEFAULT_MSR address be a constant. Also, move a big code comment to the top of enable_flash_cs5536(). Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-02-08 09:59:58 UTC (rev 3097) +++ trunk/util/flashrom/chipset_enable.c 2008-02-08 10:10:57 UTC (rev 3098) @@ -226,71 +226,97 @@ return 0; } +/** + * Geode systems write protect the BIOS via RCONFs (cache settings similar + * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and + * writing to MSRs, however requires instructions rdmsr/wrmsr, which are + * ring0 privileged instructions so only the kernel can do the read/write. + * This function, therefore, requires that the msr kernel module be loaded + * to access these instructions from user space using device /dev/cpu/0/msr. + * + * This hard-coded location could have potential problems on SMP machines + * since it assumes cpu0, but it is safe on the Geode which is not SMP. + * + * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. + * To enable write to NOR Boot flash for the benefit of systems that have such + * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). + * + * This is probably not portable beyond Linux. + */ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { - #define MSR_NORF_CTL 0x51400018 + #define MSR_RCONF_DEFAULT 0x1808 + #define MSR_NORF_CTL 0x51400018 int fd_msr; unsigned char buf[8]; - unsigned int addr = 0x1808; - /* Geode systems write protect the BIOS via RCONFs (cache - * settings similar to MTRRs). To unlock, change MSR 0x1808 - * top byte to 0x22. Reading and writing to msr, however - * requires instructions rdmsr/wrmsr, which are ring0 privileged - * instructions so only the kernel can do the read/write. This - * function, therefore, requires that the msr kernel module be - * loaded to access these instructions from user space using - * device /dev/cpu/0/msr. This hard-coded driver location - * could have potential problems on SMP machines since it - * assumes cpu0, but it is safe on the Geode which is not SMP. - * - * Geode systems also write protect the NOR flash chip itself - * via MSR_NORF_CTL. To enable write to NOR Boot flash for the - * benefit of systems that have such a setup, raise - * MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). - * - * This is probably not portable beyond Linux. - */ - fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (!fd_msr) { perror("open msr"); return -1; } - lseek64(fd_msr, (off64_t) addr, SEEK_SET); - read(fd_msr, buf, 8); + if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } + + if (read(fd_msr, buf, 8) != 8) { + perror("read"); + close(fd_msr); + return -1; + } + printf("Enabling Geode MSR to write to flash.\n"); if (buf[7] != 0x22) { buf[7] &= 0xfb; - lseek64(fd_msr, (off64_t) addr, SEEK_SET); + if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } + if (write(fd_msr, buf, 8) < 0) { perror("msr write"); printf("Cannot write to MSR. Did you run 'modprobe msr'?\n"); + close(fd_msr); return -1; } } - lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } + if (read(fd_msr, buf, 8) != 8) { perror("read msr"); + close(fd_msr); return -1; } /* Raise WE_CS3 bit. */ buf[0] |= 0x08; - lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { + perror("lseek64"); + close(fd_msr); + return -1; + } if (write(fd_msr, buf, 8) < 0) { perror("msr write"); printf("Cannot write to MSR. Did you run 'modprobe msr'?\n"); + close(fd_msr); return -1; } close(fd_msr); + #undef MSR_RCONF_DEFAULT #undef MSR_NORF_CTL return 0; }

1 0

[PATCH 1/2] flashrom: add support for AMD CS5536 devices with boot flash
by Mart Raudsepp 08 Feb '08

08 Feb '08

This implements support for devices using AMD Geode companion chip CS5536 that have the Boot ROM on NOR flash that is directly connected to FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the NORF_CTL MSR register for flashrom to be able to write to it, including JEDEC probe commands. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on the DBE61 chipset_enable.c | 43 +++++++++++++++++++++++++++++++++---------- 1 files changed, 33 insertions(+), 10 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 4cbb941..d6ef92e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -228,6 +228,8 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name) static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { + #define MSR_NORF_CTL 0x51400018 + int fd_msr; unsigned char buf[8]; unsigned int addr = 0x1808; @@ -243,34 +245,55 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) * could have potential problems on SMP machines since it * assumes cpu0, but it is safe on the Geode which is not SMP. * + * Geode systems also write protects the NOR flash chip itself + * via MSR_NORF_CTL. To enable write to NOR Boot flash for the + * benefit of systems that have such a setup, raise + * MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). + * * This is probably not portable beyond Linux. */ - fd_msr = open("/dev/cpu/0/msr", O_RDONLY); + fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (!fd_msr) { perror("open msr"); return -1; } lseek64(fd_msr, (off64_t) addr, SEEK_SET); read(fd_msr, buf, 8); - close(fd_msr); + + printf("Enabling Geode MSR to write to flash.\n"); + if (buf[7] != 0x22) { - printf("Enabling Geode MSR to write to flash.\n"); buf[7] &= 0xFB; - fd_msr = open("/dev/cpu/0/msr", O_WRONLY); - if (!fd_msr) { - perror("open msr"); - return -1; - } lseek64(fd_msr, (off64_t) addr, SEEK_SET); if (write(fd_msr, buf, 8) < 0) { perror("msr write"); printf - ("Cannot write to MSR. Make sure msr kernel is loaded: 'modprobe msr'\n"); + ("Cannot write to MSR. Make sure the msr kernel module is loaded: 'modprobe msr'\n"); return -1; } - close(fd_msr); } + + lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (read(fd_msr, buf, 8) != 8) { + perror("read msr"); + return -1; + } + + /* Raise WE_CS3 bit */ + buf[0] |= 0x08; + + lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (write(fd_msr, buf, 8) < 0) { + perror("msr write"); + printf + ("Cannot write to MSR. Make sure the msr kernel module is loaded: 'modprobe msr'\n"); + return -1; + } + + close(fd_msr); + + #undef MSR_NORF_CTL return 0; } -- 1.5.4

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coreboot February 2008