coreboot February 2008

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77 participants
422 discussions

r3097 - trunk/util/flashrom
by svn＠coreboot.org 08 Feb '08

08 Feb '08

Author: uwe Date: 2008-02-08 10:59:58 +0100 (Fri, 08 Feb 2008) New Revision: 3097 Modified: trunk/util/flashrom/chipset_enable.c Log: This implements support for devices using AMD Geode companion chip CS5536 that have the Boot ROM on NOR flash that is directly connected to FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the NORF_CTL MSR register for flashrom to be able to write to it, including JEDEC probe commands. This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on the DBE61. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-02-07 22:53:53 UTC (rev 3096) +++ trunk/util/flashrom/chipset_enable.c 2008-02-08 09:59:58 UTC (rev 3097) @@ -228,6 +228,8 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { + #define MSR_NORF_CTL 0x51400018 + int fd_msr; unsigned char buf[8]; unsigned int addr = 0x1808; @@ -243,34 +245,53 @@ * could have potential problems on SMP machines since it * assumes cpu0, but it is safe on the Geode which is not SMP. * + * Geode systems also write protect the NOR flash chip itself + * via MSR_NORF_CTL. To enable write to NOR Boot flash for the + * benefit of systems that have such a setup, raise + * MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). + * * This is probably not portable beyond Linux. */ - fd_msr = open("/dev/cpu/0/msr", O_RDONLY); + fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (!fd_msr) { perror("open msr"); return -1; } lseek64(fd_msr, (off64_t) addr, SEEK_SET); read(fd_msr, buf, 8); - close(fd_msr); + + printf("Enabling Geode MSR to write to flash.\n"); + if (buf[7] != 0x22) { - printf("Enabling Geode MSR to write to flash.\n"); - buf[7] &= 0xFB; - fd_msr = open("/dev/cpu/0/msr", O_WRONLY); - if (!fd_msr) { - perror("open msr"); - return -1; - } + buf[7] &= 0xfb; lseek64(fd_msr, (off64_t) addr, SEEK_SET); if (write(fd_msr, buf, 8) < 0) { perror("msr write"); - printf - ("Cannot write to MSR. Make sure msr kernel is loaded: 'modprobe msr'\n"); + printf("Cannot write to MSR. Did you run 'modprobe msr'?\n"); return -1; } - close(fd_msr); } + + lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (read(fd_msr, buf, 8) != 8) { + perror("read msr"); + return -1; + } + + /* Raise WE_CS3 bit. */ + buf[0] |= 0x08; + + lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET); + if (write(fd_msr, buf, 8) < 0) { + perror("msr write"); + printf("Cannot write to MSR. Did you run 'modprobe msr'?\n"); + return -1; + } + + close(fd_msr); + + #undef MSR_NORF_CTL return 0; }

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With my most recent 2 patches, I am booting to a bash prompt
by ron minnich 08 Feb '08

08 Feb '08

The LAR patch and the the patch before it gets me here: This is pbx (Linux i586 2.6.23-rc8-msm800sev-faro) 07:18:16 pbx login: root pbx ~ # So this is a real boot, i.e. interactive. There are still troubles. pbx ~ # cat /proc/interrupts CPU0 0: 24051 XT-PIC-XT timer 2: 0 XT-PIC-XT cascade 4: 294 XT-PIC-XT serial 8: 0 XT-PIC-XT rtc 14: 13885 XT-PIC-XT ide0 NMI: 0 ERR: 1 no ethernet ... pbx ~ # lspci 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31) 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) well ... pbx ~ # lspci -s 0:d.0 -v -v -v 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc.: Unknown device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping+ SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (750ns min, 2000ns max), cache line size 10 Interrupt: pin A routed to IRQ 0 Region 0: I/O ports at 1000 [size=256] Region 1: Memory at febfd000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- So this is the old issue of interrupt routing. I am going to build a PIRQ table in next. ron

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[patch] [buildrom] pull latest VSA for geode builds
by Marc Jones 08 Feb '08

08 Feb '08

The Geode tutorial is also up to date with manual build instructions. http://www.coreboot.org/AMD_Geode_Porting_Guide#Manual_build Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Update buildrom to pull latest interrupt free VSA from the AMD website, nrv2b compress it, pad to 36K it, and append to Geode coreboot images. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: buildrom/packages/coreboot-v2/geode.inc =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom/packages/coreboot-v2/geode.inc 2008-02-06 15:39:42.000000000 -0700 @@ -0,0 +1,19 @@ +VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/ +VSA_URL=http://forsteri/~marcj/ +VSA_BIN=amd_vsa_lx_1.01.bin + +CBV2_VSA=lx_vsa.36k.bin +CBV2_VSA_SIZE=36864 + +$(SOURCE_DIR)/$(VSA_BIN): + @ echo "Fetching the VSA code..." + wget -P $(SOURCE_DIR) $(VSA_URL)/$(VSA_BIN).gz -O $@.gz + gunzip $@.gz + +$(SOURCE_DIR)/$(CBV2_VSA).nrv: nrv2b $(SOURCE_DIR)/$(VSA_BIN) + @ $(STAGING_DIR)/bin/nrv2b e $(SOURCE_DIR)/$(VSA_BIN) $@ + +$(SOURCE_DIR)/$(CBV2_VSA): $(SOURCE_DIR)/$(CBV2_VSA).nrv + cp $< $@ + @ (size=`stat -c %s $<`; count=`expr $(CBV2_VSA_SIZE) - $$size`; \ + dd if=/dev/zero bs=1 count=$$count >> $@) Index: buildrom/packages/coreboot-v2/norwich.mk =================================================================== --- buildrom.orig/packages/coreboot-v2/norwich.mk 2008-02-06 15:38:56.000000000 -0700 +++ buildrom/packages/coreboot-v2/norwich.mk 2008-02-06 16:10:08.000000000 -0700 @@ -1,10 +1,14 @@ # This is the Generic coreboot target ifeq ($(CONFIG_PLATFORM),y) +ifeq ($(CONFIG_CB_USE_BUILD),y) +$(warning Building from local $(CONFIG_CB_BUILDDIR)) +else ifeq ($(CBV2_TAG),) $(error You need to specify a version to pull in your platform config) else -$(warning You specified $(CBV2_TAG) a version to pull in your platform config) +$(warning You specified svn revision $(CBV2_TAG) for your platform config) +endif endif endif @@ -12,15 +16,11 @@ CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2 CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.$(CBV2_PAYLOAD_FILE_EXT) -VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/ -CBV2_VSA=lx_vsa.36k.bin TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc -$(SOURCE_DIR)/$(CBV2_VSA): - @ echo "Fetching the VSA code..." - wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz -O $@ +include $(PACKAGE_DIR)/coreboot-v2/geode.inc $(SOURCE_DIR)/$(CBV2_TARBALL): @ echo "Fetching the coreboot rev $(CBV2_TAG) code..." Index: buildrom/packages/utils/nrv2b.mk =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom/packages/utils/nrv2b.mk 2008-02-06 15:39:42.000000000 -0700 @@ -0,0 +1,46 @@ +NRV2B_URL=svn://coreboot.org/repos/trunk/coreboot-v2/util/nrv2b +NRV2B_TAG=3086 + +NRV2B_DIR=$(BUILD_DIR)/nrv2b +NRV2B_SRC_DIR=$(NRV2B_DIR)/svn +NRV2B_STAMP_DIR=$(NRV2B_DIR)/stamps +NRV2B_LOG_DIR=$(NRV2B_DIR)/logs +NRV2B_TARBALL=nrv2b-svn-$(NRV2B_TAG).tar.gz + +ifeq ($(CONFIG_VERBOSE),y) +NRV2B_BUILD_LOG=/dev/stdout +NRV2B_FETCH_LOG=/dev/stdout +else +NRV2B_BUILD_LOG=$(NRV2B_LOG_DIR)/build.log +NRV2B_FETCH_LOG=$(NRV2B_LOG_DIR)/fetch.log +endif + +$(SOURCE_DIR)/$(NRV2B_TARBALL): + mkdir -p $(SOURCE_DIR)/nrv2b + @ $(BIN_DIR)/fetchsvn.sh $(NRV2B_URL) $(SOURCE_DIR)/nrv2b \ + $(NRV2B_TAG) $@ > $(NRV2B_FETCH_LOG) 2>&1 + +$(NRV2B_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(NRV2B_TARBALL) + @ tar -C $(NRV2B_DIR) -zxf $(SOURCE_DIR)/$(NRV2B_TARBALL) + +$(NRV2B_SRC_DIR)/nrv2b: $(NRV2B_STAMP_DIR)/.unpacked + @ (unset CFLAGS; unset LDFLAGS; \ + $(MAKE) -C $(NRV2B_SRC_DIR) \ + > $(NRV2B_BUILD_LOG) 2>&1) + +$(STAGING_DIR)/bin/nrv2b: $(NRV2B_SRC_DIR)/nrv2b + mkdir -p $(STAGING_DIR)/bin + cp $< $@ + +$(NRV2B_STAMP_DIR) $(NRV2B_LOG_DIR): + @ mkdir -p $@ + +nrv2b: $(NRV2B_STAMP_DIR) $(NRV2B_LOG_DIR) $(STAGING_DIR)/bin/nrv2b + +nrv2b-clean: + @ echo "Cleaning nrv2b..." + @ $(MAKE) -c $(NRV2B_SRC_DIR) clean > /dev/null 2>&1 + +nrv2b-distclean: + @ rm -r $(NRV2B_DIR) + Index: buildrom/packages/coreboot-v2/alix1c.mk =================================================================== --- buildrom.orig/packages/coreboot-v2/alix1c.mk 2008-02-07 16:06:16.000000000 -0700 +++ buildrom/packages/coreboot-v2/alix1c.mk 2008-02-07 16:07:08.000000000 -0700 @@ -10,15 +10,11 @@ CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2 CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.$(CBV2_PAYLOAD_FILE_EXT) -VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/ -CBV2_VSA=lx_vsa.36k.bin TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc -$(SOURCE_DIR)/$(CBV2_VSA): - @ echo "Fetching the VSA code..." - wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz -O $@ +include $(PACKAGE_DIR)/coreboot-v2/geode.inc $(SOURCE_DIR)/$(CBV2_TARBALL): @ echo "Fetching the coreboot code..." Index: buildrom/packages/coreboot-v2/msm800sev.mk =================================================================== --- buildrom.orig/packages/coreboot-v2/msm800sev.mk 2008-02-07 16:07:52.000000000 -0700 +++ buildrom/packages/coreboot-v2/msm800sev.mk 2008-02-07 16:08:19.000000000 -0700 @@ -10,15 +10,11 @@ CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2 CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.$(CBV2_PAYLOAD_FILE_EXT) -VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/ -CBV2_VSA=lx_vsa.36k.bin TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc -$(SOURCE_DIR)/$(CBV2_VSA): - @ echo "Fetching the VSA code..." - wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz -O $@ +include $(PACKAGE_DIR)/coreboot-v2/geode.inc $(SOURCE_DIR)/$(CBV2_TARBALL): @ echo "Fetching the coreboot code..."

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r3096 build service
by coreboot information 08 Feb '08

08 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ward" checked in revision 3096 to the coreboot source repository and caused the following changes: Change Log: Change payload location in 'normal' - this was missed in r3992 and thus breaks buildrom. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3096&device=serengeti_chee… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Got a problem, which may fix the other problem :-)
by ron minnich 08 Feb '08

08 Feb '08

Lar does not currently process bss quite right. I kind of blame ELF, but see what you think. Here is filo. These are program headers used in Execution (the 'E' in ELF): LOAD 0x0000c0 0x00100000 0x00100000 0x11430 0x36890 RWE 0x20 LOAD 0x011500 0x001368a0 0x001368a0 0x00048 0x00048 RW 0x20 Note the LOAD sections. Here is more of FILO. These are section headers used in Linking (the 'L' in ELF') [ 2] .text PROGBITS 00100080 000140 00e667 00 WAX 0 0 16 [ 3] .rodata PROGBITS 0010e6e8 00e7a8 002b73 00 A 0 0 4 [ 4] .eh_frame PROGBITS 0011125c 01131c 000070 00 A 0 0 4 [ 5] .data PROGBITS 001112e0 0113a0 000150 00 WA 0 0 32 [ 6] .bss NOBITS 00111440 0114f0 025450 00 WA 0 0 32 [ 7] .initctx PROGBITS 001368a0 011500 000048 00 WA 0 0 32 OK, where did the LOAD sections come from? The first is a combination of .text, .rodata, .eh_frame, and .data. .initctx is the second one. What's the FILO problem? Well: ide_probe: ide_probe drive #0 ide_probe: ctrl 1188128 base f9e8 base f9e8 is the IO base for the controller. f9eh? WHAT IS THAT? Well, it is a chunk of memory that is *supposed* to be zero! it's garbage. it's in the .bss area and lar does not initialize it or anything. Why? Well: [ 6] .bss NOBITS 00111440 0114f0 025450 00 WA 0 0 32 Note that there is NO program header (LOAD above) for this area of memory! There is only this program header! So the elf processor in LAR (which I grabbed from v2) is not processing that section. I don't think it should have to: it's a section header, not a program header, but this is an esoteric argument. So I need to modify LAR to create another payload segment for .bss, which is just a zero-filled thing. I will just look for a section header named .bss and use that. Now, this will be a zero-filled LAR entry but once compressed it will be nothing -- zero's compress nicely. But should we have a LAR type BSS for this type of usage? I am wondering. The BSS type would have a base address and size, and would be taken to mean "Zero this piece of ram". Comments? ron

2 1

r3095 build service
by coreboot information 08 Feb '08

08 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3095 to the coreboot source repository and caused the following changes: Change Log: This is a trivial patch. I missed one of the ROM names when I converted them to coreboot.rom Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Myles Watson <myles(a)pel.cs.byu.edu> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3095&device=serengeti_chee… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3096 - trunk/coreboot-v2/targets/gigabyte/m57sli
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: ward Date: 2008-02-07 23:53:53 +0100 (Thu, 07 Feb 2008) New Revision: 3096 Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb Log: Change payload location in 'normal' - this was missed in r3992 and thus breaks buildrom. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb 2008-02-07 22:42:22 UTC (rev 3095) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb 2008-02-07 22:53:53 UTC (rev 3096) @@ -50,13 +50,14 @@ # payload ../../../../payloads/tg3--filo_hda2_vga.zelf # payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf # payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf - payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf +# payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf # payload ../../../payloads/tg3_com2.zelf # payload ../../../payloads/e1000--filo.zelf # payload ../../../payloads/tg3--e1000--filo.zelf # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf + payload ../payload.elf end romimage "fallback"

1 0

r3094 build service
by coreboot information 07 Feb '08

07 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ward" checked in revision 3094 to the coreboot source repository and caused the following changes: Change Log: Make the check for -fno-stack-protector fail silently, if it fails. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3094&device=serengeti_chee… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3095 - trunk/coreboot-v2/targets/emulation/qemu-x86
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: myles Date: 2008-02-07 23:42:22 +0100 (Thu, 07 Feb 2008) New Revision: 3095 Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb Log: This is a trivial patch. I missed one of the ROM names when I converted them to coreboot.rom Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Myles Watson <myles(a)pel.cs.byu.edu> Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb 2008-02-07 21:50:22 UTC (rev 3094) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb 2008-02-07 22:42:22 UTC (rev 3095) @@ -18,5 +18,5 @@ payload ../payload.elf.lzma end -buildrom ./qemu.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "image"

1 0

Run PCI rom before PCI bus scan??
by joe＠smittys.pointclark.net 07 Feb '08

07 Feb '08

Hello, Is there a way to run a PCI rom before the PCI bus scan runs??? Thanks - Joe

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coreboot February 2008