coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

r578 - in coreboot-v3: . mainboard/emulation/qemu-x86 util/kconfig
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: myles Date: 2008-02-07 17:50:44 +0100 (Thu, 07 Feb 2008) New Revision: 578 Added: coreboot-v3/mainboard/emulation/qemu-x86/defconfig Modified: coreboot-v3/Makefile coreboot-v3/util/kconfig/confdata.c coreboot-v3/util/kconfig/symbol.c Log: This patch adds support for make defconfig in v3. Those that port v3 to a board should add a defconfig in mainboard/vendor/board/defconfig. I think that the defconfig should: 1. Use the ROM size that comes with the board 2. Enable compression 3. Not include a payload This will make it easy for buildrom or anyone who wants to build it manually to use lar to add their payloads. It also allows buildrom to keep the configs in the coreboot tree. The patch also adds mainboard/emulation/qemu-x86/defconfig Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: coreboot-v3/Makefile =================================================================== --- coreboot-v3/Makefile 2008-02-07 16:17:21 UTC (rev 577) +++ coreboot-v3/Makefile 2008-02-07 16:50:44 UTC (rev 578) @@ -80,6 +80,7 @@ ARCH:=$(shell echo $(CONFIG_ARCH)) MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_NAME)) +export MAINBOARDDIR COREBOOTINCLUDE := -I$(src) -Iinclude \ -I$(src)/include \ Added: coreboot-v3/mainboard/emulation/qemu-x86/defconfig =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/defconfig (rev 0) +++ coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-02-07 16:50:44 UTC (rev 578) @@ -0,0 +1,88 @@ +# +# Automatically generated make config: don't edit +# coreboot version: 3.0.0 +# Wed Feb 6 13:55:31 2008 +# + +# +# General setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_EXPERT is not set +CONFIG_LOCALVERSION="" + +# +# Mainboard +# +# CONFIG_VENDOR_ADL is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_ARTECGROUP is not set +CONFIG_VENDOR_EMULATION=y +# CONFIG_VENDOR_PCENGINES is not set +CONFIG_MAINBOARD_NAME="emulation/qemu-x86" +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15ad +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1976 +CONFIG_BOARD_EMULATION_QEMU_X86=y +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +CONFIG_COREBOOT_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_ARCH_X86=y +CONFIG_ARCH="x86" +CONFIG_CPU_I586=y +CONFIG_OPTION_TABLE=y + +# +# Compression +# +CONFIG_COMPRESSION_LZMA=y +# CONFIG_COMPRESSION_NRV2B is not set +CONFIG_DEFAULT_COMPRESSION_LZMA=y +# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set +# CONFIG_DEFAULT_COMPRESSION_NONE is not set + +# +# Console +# +CONFIG_CONSOLE=y +CONFIG_CONSOLE_LOGLEVEL_8=y +# CONFIG_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL_COM1=y +# CONFIG_CONSOLE_SERIAL_COM2 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set + +# +# Devices +# +CONFIG_PCI_OPTION_ROM_RUN=y +# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set +CONFIG_PCI_OPTION_ROM_RUN_VM86=y +# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set +# CONFIG_MULTIPLE_VGA_INIT is not set +# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION=y +CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y +CONFIG_SUPERIO_WINBOND_W83627HF=y +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 + +# +# Payload +# +# CONFIG_PAYLOAD_PREPARSE_ELF is not set +# CONFIG_PAYLOAD_ELF is not set +CONFIG_PAYLOAD_NONE=y Modified: coreboot-v3/util/kconfig/confdata.c =================================================================== --- coreboot-v3/util/kconfig/confdata.c 2008-02-07 16:17:21 UTC (rev 577) +++ coreboot-v3/util/kconfig/confdata.c 2008-02-07 16:50:44 UTC (rev 578) @@ -22,7 +22,7 @@ const char conf_def_filename[] = ".config"; -const char conf_defname[] = "arch/$ARCH/defconfig"; +const char conf_defname[] = "mainboard/$MAINBOARDDIR/defconfig"; const char *conf_confnames[] = { ".config", Modified: coreboot-v3/util/kconfig/symbol.c =================================================================== --- coreboot-v3/util/kconfig/symbol.c 2008-02-07 16:17:21 UTC (rev 577) +++ coreboot-v3/util/kconfig/symbol.c 2008-02-07 16:50:44 UTC (rev 578) @@ -54,6 +54,13 @@ uname(&uts); + sym = sym_lookup("MAINBOARDDIR", 0); + sym->type = S_STRING; + sym->flags |= SYMBOL_AUTO; + p = getenv("MAINBOARDDIR"); + if (p) + sym_add_default(sym, p); + sym = sym_lookup("ARCH", 0); sym->type = S_STRING; sym->flags |= SYMBOL_AUTO;

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coreboot summit april in denver
by ron minnich 07 Feb '08

07 Feb '08

We need to start a program. I am thinking I might do a section on "anatomy of the v3 port to LX". I wonder if any AMD folks could talk about issues relevant to AMD. FSF -- would be nice to from you. Anyone at VIA or SiS care to talk? Intel -- I know you're out there, we'd be happy to see you if you want to discuss your ideas. demos -- any cool hardware anyone wants to bring is fine. I will bring some. Can any Artec people show up? Thanks ron

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r577 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: rminnich Date: 2008-02-07 17:17:21 +0100 (Thu, 07 Feb 2008) New Revision: 577 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: This is a subtle error. An operations struct, to work as a constructor, must initialize the .constructor struct member. This error is so subtle that we might consider changing the device code; or at least working on the documentation to make it more clear. The key question: do we ever want an operations struct that can NOT operate as a device constructor? When this code was designed over a year ago, it seemed that we might; now, it is not so certain. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-02-07 16:09:24 UTC (rev 576) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-02-07 16:17:21 UTC (rev 577) @@ -618,6 +618,7 @@ outl(0xDEADBEEF, 0xCFC); } #endif + printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__); } /** @@ -631,9 +632,11 @@ printk(BIOS_SPEW, "cs5536: %s()\n", __FUNCTION__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); + printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__); } static struct device_operations southbridge_ops = { + .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources,

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[patch] v3 stop on vsa errors
by Marc Jones 07 Feb '08

07 Feb '08

I think we should do the same patch to v2. I'll post it if this is ack'ed. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors If there is a problem loading VSA we should stop here instead of failing in PCI scan later. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/vsmsetup.c 2008-02-01 17:06:34.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-02-01 16:25:07.000000000 -0700 @@ -183,13 +183,11 @@ init_archive(&archive); if (find_file(&archive, "blob/vsa", &file)){ - printk(BIOS_ERR, "NO VSA found!\n"); - return; + die("FATAL: NO VSA found!\n"); } if (process_file(&file, (void *)VSA2_BUFFER)) { - printk(BIOS_ERR, "Processing /blob/vsa failed\n"); - return; + die("FATAL: Processing /blob/vsa failed\n"); } buf = (unsigned char *)VSA2_BUFFER; @@ -202,8 +200,7 @@ don't bother. */ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) || (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) { - printk(BIOS_ERR, "do_vsmbios: no vsainit.bin signature, skipping!\n"); - return; + die("FATAL: no vsainit.bin signature, skipping!\n"); } /* ecx gets smm, edx gets sysm */ @@ -218,7 +215,6 @@ if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n"); else - printk(BIOS_ERR, - "do_vsmbios: VSA2 VR signature not valid, install failed!\n"); + die("FATAL: VSA2 VR signature not valid, install failed!\n"); }

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r576 - coreboot-v3/northbridge/amd/geodelx
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: mjones Date: 2008-02-07 17:09:24 +0100 (Thu, 07 Feb 2008) New Revision: 576 Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c Log: If there is a problem loading VSA we should stop here instead of failing in PCI scan later. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-02-07 06:33:49 UTC (rev 575) +++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-02-07 16:09:24 UTC (rev 576) @@ -183,13 +183,11 @@ init_archive(&archive); if (find_file(&archive, "blob/vsa", &file)){ - printk(BIOS_ERR, "NO VSA found!\n"); - return; + die("FATAL: NO VSA found!\n"); } if (process_file(&file, (void *)VSA2_BUFFER)) { - printk(BIOS_ERR, "Processing /blob/vsa failed\n"); - return; + die("FATAL: Processing /blob/vsa failed\n"); } buf = (unsigned char *)VSA2_BUFFER; @@ -202,8 +200,7 @@ don't bother. */ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) || (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) { - printk(BIOS_ERR, "do_vsmbios: no vsainit.bin signature, skipping!\n"); - return; + die("FATAL: no vsainit.bin signature, skipping!\n"); } /* ecx gets smm, edx gets sysm */ @@ -218,7 +215,6 @@ if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n"); else - printk(BIOS_ERR, - "do_vsmbios: VSA2 VR signature not valid, install failed!\n"); + die("FATAL: VSA2 VR signature not valid, install failed!\n"); }

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r108 - buildrom-devel/config/platforms
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: myles Date: 2008-02-07 16:54:34 +0100 (Thu, 07 Feb 2008) New Revision: 108 Modified: buildrom-devel/config/platforms/Config.in buildrom-devel/config/platforms/serengeti_cheetah.conf Log: Here's the patch to add buildrom support for serengeti_cheetah. It's not much, because there's no actual support in v3. I'll add the defconfig and the patch for the simulator (if it's still needed) when that's done. Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/Config.in =================================================================== --- buildrom-devel/config/platforms/Config.in 2008-02-06 22:43:44 UTC (rev 107) +++ buildrom-devel/config/platforms/Config.in 2008-02-07 15:54:34 UTC (rev 108) @@ -103,7 +103,6 @@ config PLATFORM_SERENGETI_CHEETAH bool "AMD Serengeti-Cheetah" depends VENDOR_AMD - depends COREBOOT_V2 select PLATFORM select PLATFORM_SUPPORT_64BIT @@ -117,7 +116,6 @@ config PLATFORM_CHEETAH_FAM10 bool "AMD Serengeti-Cheetah with fam10 processor" depends VENDOR_AMD - depends COREBOOT_V2 select PLATFORM select PLATFORM_SUPPORT_64BIT endchoice Modified: buildrom-devel/config/platforms/serengeti_cheetah.conf =================================================================== --- buildrom-devel/config/platforms/serengeti_cheetah.conf 2008-02-06 22:43:44 UTC (rev 107) +++ buildrom-devel/config/platforms/serengeti_cheetah.conf 2008-02-07 15:54:34 UTC (rev 108) @@ -46,14 +46,18 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf +CBV3_TAG=HEAD + ifeq ($(CONFIG_PLATFORM_CHEETAH_FAM10),y) COREBOOT_BOARD=serengeti_cheetah_fam10 CBV2_TDIR=serengeti_cheetah_fam10 CBV2_TAG=3092 +CBV3_CONFIG=serengeti_cheetah_fam10-defconfig else COREBOOT_BOARD=serengeti_cheetah CBV2_TDIR=serengeti_cheetah CBV2_TAG=3092 +CBV3_CONFIG=serengeti_cheetah-defconfig endif # FILO configuration

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porting coreboot
by Mikhail Savchenko 07 Feb '08

07 Feb '08

can you assist to port on the tyan motherboard lspci 00:01.0 PCI bridge: Broadcom HT1000 PCI/PCI-X bridge 00:02.0 Host bridge: Broadcom HT1000 Legacy South Bridge 00:02.1 IDE interface: Broadcom HT1000 Legacy IDE controller 00:02.2 ISA bridge: Broadcom HT1000 LPC Bridge 00:03.0 USB Controller: Broadcom HT1000 USB Controller (rev 01) 00:03.1 USB Controller: Broadcom HT1000 USB Controller (rev 01) 00:03.2 USB Controller: Broadcom HT1000 USB Controller (rev 01) 00:04.0 Ethernet controller: Intel Corporation 82541GI/PI Gigabit Ethernet Controller (rev 05) 00:05.0 Ethernet controller: Intel Corporation 82541GI/PI Gigabit Ethernet Controller (rev 05) 00:06.0 VGA compatible controller: XGI - Xabre Graphics Inc Volari Z7 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] Miscellaneous Control 01:0d.0 PCI bridge: Broadcom HT1000 PCI/PCI-X bridge (rev c0) 01:0e.0 IDE interface: Broadcom BCM5785 (HT1000) PATA/IDE Mode 01:0e.1 IDE interface: Broadcom BCM5785 (HT1000) PATA/IDE Mode

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r575 - in coreboot-v3: mainboard/pcengines/alix1c southbridge/amd/cs5536
by svn＠coreboot.org 07 Feb '08

07 Feb '08

Author: rminnich Date: 2008-02-07 07:33:49 +0100 (Thu, 07 Feb 2008) New Revision: 575 Modified: coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: With this set of changes FILO now reliably finds the IDE controller. Press <Enter> for default boot, or <Esc> for boot prompt... boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks) malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks) file_open: dev=hda1, path=/vmlinuz ide_probe: ide_probe drive #0 ide_probe: ctrl 1188096 base 0 find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80 find_ide_controller: primary channel: compatibility mode find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4 Sadly, it locks up at this point, but this is still progress. I realize the location of the defines is a little odd, but I think it is useful to have them right next to the function that uses them. Index: southbridge/amd/cs5536/cs5536.c cs5536.c: add ide support functions from v2 Index: mainboard/pcengines/alix1c/dts Correct error in southbridge pcipath. Add enable_ide to dts. Index: southbridge/amd/cs5536/dts Add dts for enable_ide. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-06 03:12:53 UTC (rev 574) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-07 06:33:49 UTC (rev 575) @@ -40,8 +40,9 @@ }; southbridge { /config/("southbridge/amd/cs5536/dts"); - pcipath = "0xf,1"; + pcipath = "0xf,0"; enabled; + enable_ide = "1"; }; superio { /config/("superio/winbond/w83627hf/dts"); Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-02-06 03:12:53 UTC (rev 574) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-02-07 06:33:49 UTC (rev 575) @@ -541,7 +541,36 @@ } } +#define IDE_CFG 0x40 + #define CHANEN (1L << 1) + #define PWB (1L << 14) + #define CABLE (1L << 16) +#define IDE_DTC 0x48 +#define IDE_CAST 0x4C +#define IDE_ETC 0x50 + /** + * Enabled the IDE. This is code that is optionally run if the ide_enable is set + * in the mainboard dts. + * + * @param dev The device + */ +static void ide_init(struct device *dev) +{ + u32 ide_cfg; + + printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__); + /* GPIO and IRQ setup are handled in the main chipset code. */ + + // Enable the channel and Post Write Buffer + // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set + ide_cfg = pci_read_config32(dev, IDE_CFG); + ide_cfg |= CHANEN | PWB; + pci_write_config8(dev, IDE_CFG, ide_cfg); +} + + +/** * TODO. * * @param dev The device to use. @@ -576,6 +605,9 @@ enable_USB_port4(sb); + if (sb->enable_ide) + ide_init(dev); + #warning Add back in unwanted VPCI support #if 0 /* Disable unwanted virtual PCI devices. */ @@ -588,12 +620,6 @@ #endif } -static void southbridge_enable(struct device *dev) -{ - printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev); - printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev); -} - /** * A slightly different enable resources than the standard. * We grab control here as VSA has played in this chip as well. Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-02-06 03:12:53 UTC (rev 574) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-02-07 06:33:49 UTC (rev 575) @@ -37,6 +37,9 @@ /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ enable_ide_nand_flash = "0"; + /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ + enable_ide = "0"; + /* Enable USB Port 4 (0:host 1:device). */ enable_USBP4_device = "0";

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Re: [coreboot] Run PCI rom before PCI bus scan??
by joe＠smittys.pointclark.net 07 Feb '08

07 Feb '08

Quoting Peter Stuge <peter(a)stuge.se>: > On Tue, Feb 05, 2008 at 02:49:52PM -0500, Corey Osgood wrote: >> "In the LAN controller the D0 state is partitioned into two substates >> >> and >> >> "The integrated LAN controller will be disabled if no Platform LAN >> Connect component is detected (See Section 5.2.1.3)." >> >> >> Any help? > > The first one isn't that interesting since it also implies that PCI > config regs are actually available. > > The second one, or rather section 5.2.1.3, could be interesting if > "Platform LAN Connect component" is usually found in the BIOS. > > > //Peter > OK, here is what I have picked up reading, reading, and more reading: 1. When the system is powered on "At this point, the LAN controller is in the D0u state" 2. The "Platform LAN Connect component" is actually a command script (probibly a rom written in assembly) runs and sets up the CSR register (I could setup a script in the mainboard directory and run from auto.c). 3. At this point it goes into a DOa state. 3. The "Platform LAN Connect component" hands it over to the bios (coreboot) to setup "Memory, or I/O Base Registers in the PCI Configuration space" 4. nic is setup and ready to go! What do you think? Thanks - Joe

2 1

r3092 build service
by coreboot information 07 Feb '08

07 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3092 to the coreboot source repository and caused the following changes: Change Log: This patch changes the Config.lb files and adds Config-lab.lb files for architectures supported by buildrom. Myles Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3092&device=serengeti_chee… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot February 2008