coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

Cold reset in Tyan s2912
by Roman Kononov 06 Feb '08

06 Feb '08

I have difficulty cold-resetting Tyan s2912, which has mcp55. The sequence outb(0x2,0xcf9); outb(0x6,0xcf9); is a warm reset. It does not reset the HyperTransport link frequency and width. The sequence outb(0xa,0xcf9); outb(0xe,0xcf9); causes the CPU to hang but does not reset the MB. Does anybody know what is wrong? Thanks, Roman

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[PATCH] flashrom: Handle JEDEC continuation codes in SPI ID
by Carl-Daniel Hailfinger 06 Feb '08

06 Feb '08

Chris: Try this patch against latest flashrom, please. It will not detect your chip, but id1/id2 output should change. I need full output from flashrom -V with that patch to proceed further. Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors like Programmable Micro Corp need this. Both the serial and parallel flash JEDEC detection routines would benefit from a parity/sanity check of the vendor ID. Will do this later. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> http://www.hailfinger.org/ Index: flashrom-spisecondjedecpage/spi.c =================================================================== --- flashrom-spisecondjedecpage/spi.c (Revision 3086) +++ flashrom-spisecondjedecpage/spi.c (Arbeitskopie) @@ -281,8 +281,14 @@ uint8_t manuf_id; uint16_t model_id; if (!generic_spi_rdid(readarr)) { - manuf_id = readarr[0]; - model_id = (readarr[1] << 8) | readarr[2]; + /* Check if this is a continuation vendor ID */ + if (readarr[0] == 0x7f) { + manuf_id = (readarr[0] << 8) | readarr[1]; + model_id = readarr[2]; + } else { + manuf_id = readarr[0]; + model_id = (readarr[1] << 8) | readarr[2]; + } printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); if (manuf_id == flash->manufacture_id && model_id == flash->model_id) {

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v3
by ron minnich 06 Feb '08

06 Feb '08

An assumption on v3 going on was that we could run out of ROM, and be fast, since caches are our friend. That assumption is not working out. Here is another possible design. stage 0, running in ROM, turns on CAR and runs initram in the LAR. initram disables car, copies ALL of LAR to top of memory (defined as Top Of Ram - size of LAR) initram finds stage2 in LAR, uncompresses to RAM, jumps to it. stage2 finds stage3 in LAR, uncompresses to RAM, runs it. stage3 finds payload in LAR, uncompresses to RAM, runs it. So we go to a chain model instead of call/return. We stop using ROM-based code due to performance problems. Comments? ron

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Re: [coreboot] Build error with top of tree V2
by Marc Jones 06 Feb '08

06 Feb '08

Clay Jones wrote: > I found the problem. The wrong ar command was being used because the > make file does not have " $(CROSS_COMPILE)" in front of the ar command. > Good catch! Which file or can you send a patch? Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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Re: [coreboot] Build error with top of tree V2
by Carl-Daniel Hailfinger 05 Feb '08

05 Feb '08

Hi Clay, On 05.02.2008 20:00, Clay Jones wrote: > I am getting the following error when building the > Serengeti_cheetah_fam10 target: > > gcc -m32 -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld > crt0.o > nm -n coreboot | sort > coreboot.map > objcopy --gap-fill 0xff -O binary coreboot coreboot.strip > cp ../payload.elf payload > ./buildrom coreboot.strip coreboot.rom payload 0x3f000 0x7f000 > coreboot image is 258104 bytes; only 258048 allowed > Coreboot input file larger than allowed size! > : Success > make[1]: *** [coreboot.rom] Error 2 > make[1]: Leaving directory > `/home/cjones/coreboot-v2/targets/amd/serengeti_cheetah_fam10/serengeti_ > cheetah_fam10/fallback' > make: *** [fallback/coreboot.rom] Error 1 > cjones@scully:/home/cjones/coreboot-v2/targets/amd/serengeti_cheetah_fam > 10/serengeti_cheetah_fam10 > > > The coreboot image is always a little bigger that the space allowed. I > have seen this before, but I can't remember what causes it. Anybody > know? > gcc generates bigger code than expected. Another gcc version might help, although tweaking the expected size will work as well. Regards, Carl-Daniel

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r3090 build service
by coreboot information 05 Feb '08

05 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3090 to the coreboot source repository and caused the following changes: Change Log: This patch changes all rom names that aren't coreboot.rom in Config.lb files. I think that since the directory specifies the architecture and the board, it is redundant information to name it something else, and it makes it more difficult to automate the build process (buildrom). Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3090&device=serengeti_chee… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] Build error with top of tree V2
by Clay Jones 05 Feb '08

05 Feb '08

I found the problem. The wrong ar command was being used because the make file does not have " $(CROSS_COMPILE)" in front of the ar command. -----Original Message----- From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Clay Jones Sent: Tuesday, February 05, 2008 1:08 PM To: Marc Jones Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Build error with top of tree V2 I am using buildrom and have built with the following tools on centos 4.4 (redhat): gcc (GCC) 3.4.6 20060404 (Red Hat 3.4.6-3) GNU Make 3.80 GNU ld version 2.15.92.0.2 20040927 GNU objcopy 2.15.92.0.2 20040927 -----Original Message----- From: Marc Jones [mailto:marc.jones@amd.com] Sent: Tuesday, February 05, 2008 11:39 AM To: Clay Jones Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Build error with top of tree V2 Clay Jones wrote: > Hi, > > I am getting the following error when building the > Serengeti_cheetah_fam10 target: > > > gcc -m32 -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld > crt0.o > nm -n coreboot | sort > coreboot.map > objcopy --gap-fill 0xff -O binary coreboot coreboot.strip > cp ../payload.elf payload > ./buildrom coreboot.strip coreboot.rom payload 0x3f000 0x7f000 > coreboot image is 258104 bytes; only 258048 allowed > Coreboot input file larger than allowed size! > : Success > make[1]: *** [coreboot.rom] Error 2 > make[1]: Leaving directory > `/home/cjones/coreboot-v2/targets/amd/serengeti_cheetah_fam10/serengeti_ > cheetah_fam10/fallback' > make: *** [fallback/coreboot.rom] Error 1 > cjones@scully:/home/cjones/coreboot-v2/targets/amd/serengeti_cheetah_fam > 10/serengeti_cheetah_fam10 > > > The coreboot image is always a little bigger that the space allowed. I > have seen this before, but I can't remember what causes it. Anybody > know? > > > Can you post your distribution, gcc version and binutils versions? Are you using buildrom? Did you build a normal image too? did you change the mainboard or target config.lb? I get the following using buildrom on my local directory: ./buildrom coreboot.strip coreboot.rom payload 0x3f000 0x7f000 Payload: 61872 coreboot: 258048 ROM size: 520192 Left space: 200272 Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. This message contains confidential information and is intended only for the individual named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. -- coreboot mailing list coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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r3090 - in trunk/coreboot-v2/targets: agami/aruma amd/db800 amd/norwich amd/serengeti_cheetah_fam10 arima/hdama artecgroup/dbe61 emulation/qemu-i386 msi/ms9185 msi/ms9282 newisys/khepri technologic/ts5300
by svn＠coreboot.org 05 Feb '08

05 Feb '08

Author: myles Date: 2008-02-05 22:53:15 +0100 (Tue, 05 Feb 2008) New Revision: 3090 Modified: trunk/coreboot-v2/targets/agami/aruma/Config.lb trunk/coreboot-v2/targets/agami/aruma/Config1M.lb trunk/coreboot-v2/targets/amd/db800/Config.lb trunk/coreboot-v2/targets/amd/norwich/Config.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb trunk/coreboot-v2/targets/msi/ms9185/Config.lb trunk/coreboot-v2/targets/msi/ms9282/Config.lb trunk/coreboot-v2/targets/newisys/khepri/Config.lb trunk/coreboot-v2/targets/technologic/ts5300/Config.lb Log: This patch changes all rom names that aren't coreboot.rom in Config.lb files. I think that since the directory specifies the architecture and the board, it is redundant information to name it something else, and it makes it more difficult to automate the build process (buildrom). Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/coreboot-v2/targets/agami/aruma/Config.lb =================================================================== --- trunk/coreboot-v2/targets/agami/aruma/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/agami/aruma/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -26,4 +26,4 @@ payload ../../../../../../filo.elf end -buildrom ./agami_aruma.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Modified: trunk/coreboot-v2/targets/agami/aruma/Config1M.lb =================================================================== --- trunk/coreboot-v2/targets/agami/aruma/Config1M.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/agami/aruma/Config1M.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -21,4 +21,4 @@ payload ../../../../../../linux.elf end -buildrom ./agami_aruma.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/db800/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/amd/db800/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -46,4 +46,4 @@ payload ../payload.elf end -buildrom ./db800.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/norwich/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/amd/norwich/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -46,4 +46,4 @@ payload ../payload.elf end -buildrom ./norwich.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -65,6 +65,6 @@ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./amd-cheetah-fam10.rom ROM_SIZE "normal" "fallback" "failover" -buildrom ./amd-cheetah-fam10.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" Modified: trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -100,4 +100,4 @@ # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf end -buildrom ./luxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -31,4 +31,4 @@ payload ../payload.elf end -buildrom ./dbe61.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -18,5 +18,5 @@ payload __PAYLOAD__ end -buildrom ./qemu-bios.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "image" Modified: trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -16,5 +16,5 @@ payload /home/stepan/core.img end -buildrom ./qemu-bios.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "image" Modified: trunk/coreboot-v2/targets/msi/ms9185/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9185/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/msi/ms9185/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -91,4 +91,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./ms9185.lxb ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Modified: trunk/coreboot-v2/targets/msi/ms9282/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9282/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/msi/ms9282/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -88,4 +88,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./ms9282.lxb ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Modified: trunk/coreboot-v2/targets/newisys/khepri/Config.lb =================================================================== --- trunk/coreboot-v2/targets/newisys/khepri/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/newisys/khepri/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -42,4 +42,4 @@ payload ../../../payloads/tg3--ide_disk.zelf end -buildrom ./khepri.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Modified: trunk/coreboot-v2/targets/technologic/ts5300/Config.lb =================================================================== --- trunk/coreboot-v2/targets/technologic/ts5300/Config.lb 2008-02-05 09:21:46 UTC (rev 3089) +++ trunk/coreboot-v2/targets/technologic/ts5300/Config.lb 2008-02-05 21:53:15 UTC (rev 3090) @@ -29,4 +29,4 @@ payload /home/stepan/filo-ts5300.elf end -buildrom ./technologic_ts5300.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"

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Re: [coreboot] Build error with top of tree V2
by Marc Jones 05 Feb '08

05 Feb '08

Clay Jones wrote: > Hi, > > I am getting the following error when building the > Serengeti_cheetah_fam10 target: > > > gcc -m32 -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld > crt0.o > nm -n coreboot | sort > coreboot.map > objcopy --gap-fill 0xff -O binary coreboot coreboot.strip > cp ../payload.elf payload > ./buildrom coreboot.strip coreboot.rom payload 0x3f000 0x7f000 > coreboot image is 258104 bytes; only 258048 allowed > Coreboot input file larger than allowed size! > : Success > make[1]: *** [coreboot.rom] Error 2 > make[1]: Leaving directory > `/home/cjones/coreboot-v2/targets/amd/serengeti_cheetah_fam10/serengeti_ > cheetah_fam10/fallback' > make: *** [fallback/coreboot.rom] Error 1 > cjones@scully:/home/cjones/coreboot-v2/targets/amd/serengeti_cheetah_fam > 10/serengeti_cheetah_fam10 > > > The coreboot image is always a little bigger that the space allowed. I > have seen this before, but I can't remember what causes it. Anybody > know? > > > Can you post your distribution, gcc version and binutils versions? Are you using buildrom? Did you build a normal image too? did you change the mainboard or target config.lb? I get the following using buildrom on my local directory: ./buildrom coreboot.strip coreboot.rom payload 0x3f000 0x7f000 Payload: 61872 coreboot: 258048 ROM size: 520192 Left space: 200272 Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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tyan s2895 how to?
by r00ter＠uboot.com 05 Feb '08

05 Feb '08

hello, first, thanks for your work. i'am very interested in your project and want to install coreboot with a kernel as payload on my tyan s2895 and using a addon graphiccard(geforce 6600 gt). my current system is running gentoo (kernel 2.6.24 x64). i read the amd64 doc and want to start. i only want to ask if there's a image of the tyan and a geforce 6600gt. and are there some tutorials in german? or german users or developers who can help me? Thank you ----- community mit gratis blog, chat, video, foto, gallery, sms, mail www.uboot.com

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coreboot February 2008