coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

CK804 interrupt steering - SATA fix
by jakllsch＠kollasch.net 04 Feb '08

04 Feb '08

Hi, I've reverse engineered some registers in the CK804. I believe with this information all SATA ports can be enabled without any lost interrupts. More on fixing the SATA issue later on, now what I've found. ---- LPC bridge PCI config registers: 0x7c:0x0000ffff - bitmap of masked pci irqs? - PIRQ[ABCD] possibly? 0x7c:0x00f00000 - sata at f8 - port 1 0x7c:0x0f000000 - sata at f7 - port 1 0x80:0xf0000000 - sata at f7 - port 0 0x80:0x0f000000 - sata at f8 - port 0 0x80:0x0000f000 - EHCI 0x84:0x00000f00 - NIC 0x84:0x0000000f - OHCI known values of nibbles: 0 - unrouted? 1 - irq 23 8 - irq 20 c - irq 12 d - irq 21 e - irq 14 f - irq 15 ----- When the interrupts of both SATA ports on each controller are routed the same, the regular drivers should work. I've only tested this with NetBSD's viaide(4), I have no idea if these may also apply to the ADMA mode. On many boards these registers are set in mptable.c. I hope someone can make good use of this. Jonathan Kollasch

2 2

r572 - in coreboot-v3: arch/x86 arch/x86/geodelx northbridge/amd/geodelx
by svn＠coreboot.org 04 Feb '08

04 Feb '08

Author: rminnich Date: 2008-02-04 17:16:16 +0100 (Mon, 04 Feb 2008) New Revision: 572 Modified: coreboot-v3/arch/x86/Makefile coreboot-v3/arch/x86/geodelx/stage1.c coreboot-v3/northbridge/amd/geodelx/Makefile coreboot-v3/northbridge/amd/geodelx/geodelx.c coreboot-v3/northbridge/amd/geodelx/geodelxinit.c Log: This change moves the geodelxinit code from stage2 to stage1, which in turn gets cache turned on much sooner. The system boots a bit faster. We're still far too slow, perhaps because we are not caching ROM? Index: arch/x86/Makefile Add ../../northbridge/amd/geodelx/geodelxinit.o object Index: arch/x86/geodelx/geodelxinit.c add sizeram function. Index: arch/x86/geodelx/stage1.c add called to northbridge_init_early() Index: northbridge/amd/geodelx/Makefile remove geodelxinit.o object Index: northbridge/amd/geodelx/geodelx.c remove call to northbridge_init_early() remove sizeram function. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-02-01 20:35:53 UTC (rev 571) +++ coreboot-v3/arch/x86/Makefile 2008-02-04 16:16:16 UTC (rev 572) @@ -117,6 +117,7 @@ ifeq ($(CONFIG_CPU_AMD_GEODELX),y) STAGE0_CAR_OBJ = geodelx/stage0.o STAGE0_ARCH_X86_OBJ += geodelx/stage1.o + STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o else STAGE0_CAR_OBJ = stage0_i586.o endif Modified: coreboot-v3/arch/x86/geodelx/stage1.c =================================================================== --- coreboot-v3/arch/x86/geodelx/stage1.c 2008-02-01 20:35:53 UTC (rev 571) +++ coreboot-v3/arch/x86/geodelx/stage1.c 2008-02-04 16:16:16 UTC (rev 572) @@ -55,6 +55,7 @@ */ void disable_car(void) { + extern void northbridge_init_early(void); int i; for (i = 0; i < ARRAY_SIZE(msr_table); i++) @@ -67,5 +68,6 @@ __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); __asm__ __volatile__ ("wbinvd\n"); banner(BIOS_DEBUG, "Disable_car: done wbinvd"); + northbridge_init_early(); banner(BIOS_DEBUG, "disable_car: done"); } Modified: coreboot-v3/northbridge/amd/geodelx/Makefile =================================================================== --- coreboot-v3/northbridge/amd/geodelx/Makefile 2008-02-01 20:35:53 UTC (rev 571) +++ coreboot-v3/northbridge/amd/geodelx/Makefile 2008-02-04 16:16:16 UTC (rev 572) @@ -22,7 +22,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ - $(obj)/northbridge/amd/geodelx/geodelxinit.o \ $(obj)/northbridge/amd/geodelx/vsmsetup.o endif Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-01 20:35:53 UTC (rev 571) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-04 16:16:16 UTC (rev 572) @@ -142,49 +142,6 @@ }; /** - * Size up ram. - * - * All we need to do here is read the MSR for DRAM and grab out the sizing - * bits. Note that this code depends on initram having run. It uses the MSRs, - * not the SPDs, and the MSRs of course are set up by initram. - * - * @return TODO - */ -int sizeram(void) -{ - struct msr msr; - int sizem = 0; - u32 dimm; - - /* Get the RAM size from the memory controller as calculated - * and set by auto_size_dimm(). - */ - msr = rdmsr(MC_CF07_DATA); - printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, - msr.lo); - - /* DIMM 0 */ - dimm = msr.hi; - /* Installed? */ - if ((dimm & 7) != 7) { - /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ - sizem = 4 << ((dimm >> 12) & 0x0F); - } - - /* DIMM 1 */ - dimm = msr.hi >> 16; - /* Installed? */ - if ((dimm & 7) != 7) { - /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ - sizem += 4 << ((dimm >> 12) & 0x0F); - } - - printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem); - - return sizem; -} - -/** * Currently not set up. * * @param dev The nortbridge device. @@ -317,7 +274,7 @@ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - northbridge_init_early(); +// northbridge_init_early(); chipsetinit(); setup_realmode_idt(); Modified: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-01 20:35:53 UTC (rev 571) +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-04 16:16:16 UTC (rev 572) @@ -25,7 +25,6 @@ #include <amd_geodelx.h> /* Function prototypes */ -extern int sizeram(void); struct gliutable { unsigned long desc_name; @@ -142,6 +141,49 @@ } /** + * Size up ram. + * + * All we need to do here is read the MSR for DRAM and grab out the sizing + * bits. Note that this code depends on initram having run. It uses the MSRs, + * not the SPDs, and the MSRs of course are set up by initram. + * + * @return TODO + */ +int sizeram(void) +{ + struct msr msr; + int sizem = 0; + u32 dimm; + + /* Get the RAM size from the memory controller as calculated + * and set by auto_size_dimm(). + */ + msr = rdmsr(MC_CF07_DATA); + printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, + msr.lo); + + /* DIMM 0 */ + dimm = msr.hi; + /* Installed? */ + if ((dimm & 7) != 7) { + /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ + sizem = 4 << ((dimm >> 12) & 0x0F); + } + + /* DIMM 1 */ + dimm = msr.hi >> 16; + /* Installed? */ + if ((dimm & 7) != 7) { + /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ + sizem += 4 << ((dimm >> 12) & 0x0F); + } + + printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem); + + return sizem; +} + +/** * Set up the system memory registers, i.e. memory that can be used * for non-VSM (or SMM) purposes. *

1 0

Flashing problem on the SST49LF004B
by Lalitha V.N. 04 Feb '08

04 Feb '08

Hello all ............ we are working on the coreboot project ..... Initially we are copied the BIOS(PM49FL004) content that is present in the motherboard( ASRock K8Upgrade-VM800) in a file name called jan-14 and tried to flash(write) the content in the filename jan-14 on to a new flashrom SST49LF004B.. but flash is not happened properly .. these are the steps we followed ... [root@turtle9 flashrom]# flashrom Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). No operations were specified. *Reading the original Bios content in to the file jan14:* [root@turtle9 flashrom]# flashrom -r jan14 Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Reading Flash...done [root@turtle9 flashrom]# flashrom -v jan14 Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. ***Then we removed the original Bios chip and inserted the new flashrom SST49LF004B and tried to flash(write) the content present in the filename jan14 ,but finally we got the result as bellow ........ *Writing on to the new Bios chip (SST49LF004B):* [root@turtle9 flashrom]# flashrom -w jan14 Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 *Then we varified .....* [root@turtle9 flashrom]# flashrom -v jan14 Calibrating delay loop... okNo LinuxBIOS table found.Found chipset "VT8237": Enabling flash write... OK.SST49LF004A/B found at physical address: 0xfff80000Flash part is SST49LF004A/B (512 KB)Flash image seems to be a legacy BIOS. Disabling checks.Verifying flash - FAILED So we tried to change the flashrom utility code..so first we downloaded coreboot code from the coreboot.org then in that we tried to change the code in util/flashrom file but stil we are unable to get the way where we need to change the code such that the flash can happen ... we are also gone through the datasheet of SST49LF004B and PM49FL004 but we are not getting any exact idea ....... please guide us............... with regards, lalitha

2 1

VIA EPIA CN100000 is finally Working all.
by Urbez Santana Roma 04 Feb '08

04 Feb '08

Finally works, my mainboard complete, with the IDE +dma, network, usb, etc... I must only add the same that y have commented in my last email, for working the access of IDE , network, etc. Mainboard: VIA EPIA CN10000. Chipsets: VT8237 and CN700 Cpu: C7 Ram: 512MB DDR2 KVR533D2N4 Linux Kernel: 2.6.22 1. Make a clone of the last posted code for CN700/C7 jetway mainboard of Corey Osgood, for your mainboard. 2. Set to 1 the 20 bit in the function sdram_enable() to all MRS RAM Commands. If not, the Kingstom Memory not initiates correctly. 3. comment the call to the function disable_sata(), if not, your normal ide not appears in the PCI config space. 4. Add the follow code to the end of the function main() in auto.c: if not, your normal IDE cannot use DMA and via-rhine, usb's, etc, not works. //This enable the access of PCI devices to the PCI bus master? pci_write_config8(cn700->d0f7, 0x57, 0x20);//was 0x01 5. If you will that the FILO not confuses scanning PCI, you must add, to the end of main() in auto.c: pci_write_config8(cn700->d1f0,0x19,0x1,CF8);//enable PCI-BRIGDE SECONDARY BUS pci_write_config8(cn700->d1f0,0x1a,0x1,CF8); 6. If you want that your BIOS, runs at the maximum CPU speed, in my case, the CPU starts with 800MHz, and i needed in the bios that works with 1000MHz. You can add this if u will: #define MSR_IA32_PERF_STATUS 0x00000198 #define MSR_IA32_PERF_CTL 0x00000199 #define MSR_IA32_MISC_ENABLE 0x000001a0 msr_t msr; print_debug("Enabling C7 Power Save\r\n"); msr=rdmsr(MSR_IA32_MISC_ENABLE); if (!(msr.lo & 0x10000)) {msr.lo| 0x10000;wrmsr(MSR_IA32_MISC_ENABLE,msr); msr=rdmsr(MSR_IA32_PERF_STATUS); //TODO: wait CPU not busy bit 16 & 17 off (STATUS) wrmsr(MSR_IA32_PERF_CTL, 0, (hi&0xff00)| ((hi>>16)&0x00ff)); //Max multi Factor, and minimum voltage //TODO: wait CPU transition bit 16 & 17 off (STATUS) 7. If you will, you can generate your fadt.c and dsdt.c with the genfadt and gendsdt tool, or generate one new. 8. Force the ACPI in the kernel if not uses it with acpi=force 9. If you want that your kernel recognises lapic, you must change the kernel driver, for not ignore another Vendors differs of AMD and Intel, in the function "static int __init detect_init_APIC (void)" of the file ./arch/i386/kernel/apic.c End.

5 9

Re: [coreboot] igel-132 xm smart
by Jeffrey Thompson 04 Feb '08

04 Feb '08

Hi All, New to this and hope someone can direct me. I have acquired a few "igel-132 xm smart" thin clients that have admin passwords and are not able to be reset to default configs. I am hoping I can somehow get linux on these units and have no support from Igel. I did notice a couple posts for Igel thin clients but I don't see how to do any hardware mods if they are required. Thanks for you patience and looking forward to any assistance. JT

1 0

memtest running on alix1c!
by ron minnich 03 Feb '08

03 Feb '08

it was a minicom/terminal size issue. A big minicom caused memtest to get a divide by zero. It's running! It has confusion: L1 Cache: Unknown | Test #6 [Moving inversions, 32 bit pattern] L2 Cache: Unknown | Testing: 120K - 256M 255M but hey ... ron

3 2

memtest on lx on v3: working
by ron minnich 03 Feb '08

03 Feb '08

turned out the problem was some weirdness between minicom/memtest on serial. I resized the terminal window that minicom was in and memtest has been running fine for almost 5 hours. I also have mode cache enable around so that it happens in disable_car. This helps a bit. But I still feel we're not caching ROM. ron

2 1

[LinuxBIOS] [patch] MSI MS-7135 (this time with attachment)
by jakllsch＠kollasch.net 03 Feb '08

03 Feb '08

Initial support for MSI MS-7135 (K8N Neo3) mainboard. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>

4 8

Re: [coreboot] #70: fix util/getpir so that the output will compile
by coreboot 03 Feb '08

03 Feb '08

#70: fix util/getpir so that the output will compile ------------------------------------------------------+--------------------- Reporter: Jon Dufresne <jon.dufresne(a)gmail.com> | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: patch needs work ------------------------------------------------------+--------------------- Comment (by jon.dufresne(a)gmail.com): Signed-off-by: Jon Dufresne <jon.dufresne(a)gmail.com> -- Ticket URL: <http://tracker.linuxbios.org/trac/coreboot/ticket/70#comment:2> coreboot <http://www.coreboot.org/>

1 0

Re: [coreboot] #69: Fix mptable util so the output will compile
by coreboot 03 Feb '08

03 Feb '08

#69: Fix mptable util so the output will compile ------------------------------------------------------+--------------------- Reporter: Jon Dufresne <jon.dufresne(a)gmail.com> | Owner: somebody Type: defect | Status: closed Priority: major | Milestone: Component: code | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: patch has been committed ------------------------------------------------------+--------------------- Comment (by anonymous): Signed-off-by: Jon Dufresne <jon.dufresne(a)gmail.com> -- Ticket URL: <http://tracker.linuxbios.org/trac/coreboot/ticket/69#comment:3> coreboot <http://www.coreboot.org/>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2008