VIA EPIA CN100000 is finally Working all.

[Urbez Santana Roma]

Finally works, my mainboard complete, with the IDE +dma, network, usb,
etc...

I must only add the same that y have commented in my last email, for
working the access of IDE , network, etc.

Mainboard: VIA EPIA CN10000.
Chipsets: VT8237 and CN700
Cpu: C7 
Ram: 512MB DDR2 KVR533D2N4
Linux Kernel: 2.6.22

1. Make a clone of the last posted code for CN700/C7 jetway mainboard of
Corey Osgood, for your mainboard.

2. Set to 1 the 20 bit in the function sdram_enable() to all MRS RAM
Commands. If not, the Kingstom
Memory not initiates correctly.

3. comment the call to the function disable_sata(), if not, your normal
ide not appears in the PCI config space.

4. Add the follow code to the end of the function main() in auto.c: if
not, your normal IDE cannot use DMA and via-rhine, usb's, etc, not
works.
    
        //This enable the access of PCI devices to the PCI bus master?
        pci_write_config8(cn700->d0f7, 0x57, 0x20);//was 0x01

5. If you will that the FILO not confuses scanning PCI, you must add, to
the end of main() in auto.c:

pci_write_config8(cn700->d1f0,0x19,0x1,CF8);//enable PCI-BRIGDE
SECONDARY BUS
    pci_write_config8(cn700->d1f0,0x1a,0x1,CF8);

6. If you want that your BIOS, runs at the maximum CPU speed, in my
case, the CPU starts
with 800MHz, and i needed in the bios that works with 1000MHz. You can
add this if u will:

#define MSR_IA32_PERF_STATUS                    0x00000198
#define MSR_IA32_PERF_CTL                       0x00000199
#define MSR_IA32_MISC_ENABLE                    0x000001a0

msr_t msr;
        print_debug("Enabling C7 Power Save\r\n");
        msr=rdmsr(MSR_IA32_MISC_ENABLE);
        if (!(msr.lo & 0x10000)) {msr.lo|
0x10000;wrmsr(MSR_IA32_MISC_ENABLE,msr);
        msr=rdmsr(MSR_IA32_PERF_STATUS);
        //TODO: wait CPU not busy bit 16 & 17 off (STATUS)
        wrmsr(MSR_IA32_PERF_CTL, 0,  (hi&0xff00)| ((hi>>16)&0x00ff));
        //Max multi Factor, and minimum voltage
        //TODO: wait CPU transition bit 16 & 17 off (STATUS)

7. If you will, you can generate your fadt.c and dsdt.c with the genfadt
and gendsdt tool, or generate one new.

8. Force the ACPI in the kernel if not uses it with acpi=force

9. If you want that your kernel recognises lapic, you must change the
kernel driver, for not ignore
another Vendors differs of AMD and Intel, in the function "static int
__init detect_init_APIC (void)" of the file ./arch/i386/kernel/apic.c

End.

[Rudolf Marek]

Hi Urbez,
> Add the follow code to the end of the function main() in auto.c: if
>
> not, your normal IDE cannot use DMA and via-rhine, usb's, etc, not
> works.
>     //This enable the access of PCI devices to the PCI bus master?
>     pci_write_config8(cn700->d0f7, 0x57, 0x20);//was 0x01

I think this is connected to some last DRAM address stuff. DMA may not work if 
this is incorrect. Consult some similar datasheet 
jjj.ivn.pbz.gj!ra!qbjaybnqf!qngnfurrgf!puvcfrgf!QF_PA400_118.mvc
It may be the last bank ending address??? Perhaps this must be copied from 
function 3 maybe?
> If you will that the FILO not confuses scanning PCI, you must add, to
>
> the end of main() in auto.c:
> pci_write_config8(cn700->d1f0,0x19,0x1,CF8);//enable PCI-BRIGDE
>
> SECONDARY BUS
>     pci_write_config8(cn700->d1f0,0x1a,0x1,CF8);

Perhaps is something translating configuration cycles?

Rudolf

[Corey Osgood]

On Feb 3, 2008 1:52 PM, Rudolf Marek  wrote:
> Hi Urbez,
> > Add the follow code to the end of the function main() in auto.c: if
> >
> > not, your normal IDE cannot use DMA and via-rhine, usb's, etc, not
> > works.
> >     //This enable the access of PCI devices to the PCI bus master?
> >     pci_write_config8(cn700->d0f7, 0x57, 0x20);//was 0x01
>
> I think this is connected to some last DRAM address stuff. DMA may not
> work if
> this is incorrect. Consult some similar datasheet
> jjj.ivn.pbz.gj!ra!qbjaybnqf!qngnfurrgf!puvcfrgf!QF_PA400_118.mvc
> It may be the last bank ending address??? Perhaps this must be copied from
> function 3 maybe?

Exactly
> > If you will that the FILO not confuses scanning PCI, you must add, to
> >
> > the end of main() in auto.c:
> > pci_write_config8(cn700->d1f0,0x19,0x1,CF8);//enable PCI-BRIGDE
> >
> > SECONDARY BUS
> >     pci_write_config8(cn700->d1f0,0x1a,0x1,CF8);
>
> Perhaps is something translating configuration cycles?
>
> Rudolf

Nope, secondary and subordinate bus number. But what's up with the CF8 at
the end of these commands?

-Corey

[Corey Osgood]

On Feb 3, 2008 10:49 AM, Urbez Santana Roma  wrote:
> Finally works, my mainboard complete, with the IDE +dma, network, usb,
> etc...
>
> I must only add the same that y have commented in my last email, for
> working the access of IDE , network, etc.
>
> Mainboard: VIA EPIA CN10000.
> Chipsets: VT8237 and CN700
> Cpu: C7
> Ram: 512MB DDR2 KVR533D2N4
> Linux Kernel: 2.6.22
> Make a clone of the last posted code for CN700/C7 jetway mainboard of
>
> Corey Osgood, for your mainboard.
> Set to 1 the 20 bit in the function sdram_enable() to all MRS RAM
>
> Commands. If not, the Kingstom
> Memory not initiates correctly.
> comment the call to the function disable_sata(), if not, your normal
>
> ide not appears in the PCI config space.

Weird. This USED to work, I'm still trying to figure out how I messed it up.

4. Add the follow code to the end of the function main() in auto.c: if
> not, your normal IDE cannot use DMA and via-rhine, usb's, etc, not
> works.
>    //This enable the access of PCI devices to the PCI bus master?
>    pci_write_config8(cn700->d0f7, 0x57, 0x20);//was 0x01

As Rudolf said, this is supposed to be the address of the last dram bank, IE
how much ram the system has. Interestingly enough, although these registers
are in the northbridge's config space, they're actually set on the
southbridge, through the vlink. That's why some registers have to be set
both in d0f3 and d0f7. I'm setting this up now in d0f3 during raminit, so I
can just copy it over.

5. If you will that the FILO not confuses scanning PCI, you must add, to
> the end of main() in auto.c:
>
> pci_write_config8(cn700->d1f0,0x19,0x1,CF8);//enable PCI-BRIGDE
> SECONDARY BUS
>    pci_write_config8(cn700->d1f0,0x1a,0x1,CF8);

Huh? I think these are already set somewhere, perhaps c7_cpu_setup(). Might
not be in the older patch.
> If you want that your BIOS, runs at the maximum CPU speed, in my
>
> case, the CPU starts
> with 800MHz, and i needed in the bios that works with 1000MHz. You can
> add this if u will:
>
> #define MSR_IA32_PERF_STATUS                    0x00000198
> #define MSR_IA32_PERF_CTL                       0x00000199
> #define MSR_IA32_MISC_ENABLE                    0x000001a0
>    msr_t msr;
>    print_debug("Enabling C7 Power Save\r\n");
>    msr=rdmsr(MSR_IA32_MISC_ENABLE);
>    if (!(msr.lo & 0x10000)) {msr.lo|
>
> 0x10000;wrmsr(MSR_IA32_MISC_ENABLE,msr);
>        msr=rdmsr(MSR_IA32_PERF_STATUS);
>        //TODO: wait CPU not busy bit 16 & 17 off (STATUS)
>        wrmsr(MSR_IA32_PERF_CTL, 0,  (hi&0xff00)| ((hi>>16)&0x00ff));
>        //Max multi Factor, and minimum voltage
>        //TODO: wait CPU transition bit 16 & 17 off (STATUS)

OK, I'll add this, thanks! Is this CPU-specific, or does this set any CPU to
the max speed?
> If you will, you can generate your fadt.c and dsdt.c with the genfadt
>
> and gendsdt tool, or generate one new.
>
> Force the ACPI in the kernel if not uses it with acpi=force
>
> If you want that your kernel recognises lapic, you must change the
>
> kernel driver, for not ignore
> another Vendors differs of AMD and Intel, in the function "static int
> __init detect_init_APIC (void)" of the file ./arch/i386/kernel/apic.c
>
> End.

Thanks, this should be very helpful. I'll take your changes into account,
and have a fresh patch sometime soon. Watching the super bowl atm, but I
should have some time tomorrow.

-Corey

[Peter Stuge]

On Sun, Feb 03, 2008 at 08:19:26PM -0500, Corey Osgood wrote:
> Thanks, this should be very helpful. I'll take your changes into
> account, and have a fresh patch sometime soon.

I'll test on my CN10k board as well when you do.
> Watching the super bowl atm

Heh, had an eye on it while doing some soldering. What a come-back.

//Peter

[Corey Osgood]

Urbez, can you send a patch against svn? Or at least your auto.c and
vt8237r_ide.c? I've been trying for the last several hours now, and I can't
get FILO to detect my IDE drive, without disabling SATA, so I'm
assuming/hoping you've changed something that I've missed. Works fine with
SATA disabled though. Thanks!

On Feb 4, 2008 12:09 AM, Peter Stuge  wrote:
> On Sun, Feb 03, 2008 at 08:19:26PM -0500, Corey Osgood wrote:
> > Thanks, this should be very helpful. I'll take your changes into
> > account, and have a fresh patch sometime soon.
>
> I'll test on my CN10k board as well when you do.
> > Watching the super bowl atm
>
> Heh, had an eye on it while doing some soldering. What a come-back.

Ugh, tell me about it.

*Is from New England, and a Patriots fan*

-Corey
> //Peter

[Rudolf Marek]

Corey Osgood wrote:
> Urbez, can you send a patch against svn? Or at least your auto.c and 
> vt8237r_ide.c? I've been trying for the last several hours now, and I 
> can't get FILO to detect my IDE drive, without disabling SATA, so I'm 
> assuming/hoping you've changed something that I've missed. Works fine 
> with SATA disabled though. Thanks!

Yep this needs to be documented.  If you have SATA ports and 2xIDE FILO thinks 
like this:

hda - SATA0
hdb - dummySATA0
hdc - SATA1
hdd - dummySATA1
hde - PriMaster IDE
hdf - PriSlave IDE
hdg - SecMaster IDE
hdh - SecSlave IDE

Rudolf

[Corey Osgood]

Couple questions:

On Feb 3, 2008 10:49 AM, Urbez Santana Roma  wrote:
>
> If you want that your BIOS, runs at the maximum CPU speed, in my
>
> case, the CPU starts
> with 800MHz, and i needed in the bios that works with 1000MHz. You can
> add this if u will:
>
> #define MSR_IA32_PERF_STATUS                    0x00000198
> #define MSR_IA32_PERF_CTL                       0x00000199
> #define MSR_IA32_MISC_ENABLE                    0x000001a0
>    msr_t msr;
>    print_debug("Enabling C7 Power Save\r\n");
>    msr=rdmsr(MSR_IA32_MISC_ENABLE);
>    if (!(msr.lo & 0x10000)) {msr.lo|
>
> 0x10000;

msr.lo |= 0x10000?
> wrmsr(MSR_IA32_MISC_ENABLE,msr);
>        msr=rdmsr(MSR_IA32_PERF_STATUS);
>        //TODO: wait CPU not busy bit 16 & 17 off (STATUS)
>        wrmsr(MSR_IA32_PERF_CTL, 0,  (hi&0xff00)| ((hi>>16)&0x00ff));
>        //Max multi Factor, and minimum voltage
>        //TODO: wait CPU transition bit 16 & 17 off (STATUS)

}

I'm about to test out the rest of the changes.

Thanks,
Corey

[Corey Osgood]

On Feb 3, 2008 10:56 PM, Corey Osgood  wrote:
> Couple questions:
>
> On Feb 3, 2008 10:49 AM, Urbez Santana Roma 
> wrote:
> >
> > If you want that your BIOS, runs at the maximum CPU speed, in my
> >
> > case, the CPU starts
> > with 800MHz, and i needed in the bios that works with 1000MHz. You can
> > add this if u will:
> >
> > #define MSR_IA32_PERF_STATUS                    0x00000198
> > #define MSR_IA32_PERF_CTL                       0x00000199
> > #define MSR_IA32_MISC_ENABLE                    0x000001a0
> >    msr_t msr;
> >    print_debug("Enabling C7 Power Save\r\n");
> >    msr=rdmsr(MSR_IA32_MISC_ENABLE);
> >    if (!(msr.lo & 0x10000)) {msr.lo|
> >
> > 0x10000;
>
> msr.lo |= 0x10000?
> > wrmsr(MSR_IA32_MISC_ENABLE,msr);
> >        msr=rdmsr(MSR_IA32_PERF_STATUS);
> >        //TODO: wait CPU not busy bit 16 & 17 off (STATUS)
> >        wrmsr(MSR_IA32_PERF_CTL, 0,  (hi&0xff00)| ((hi>>16)&0x00ff));
> >        //Max multi Factor, and minimum voltage
> >        //TODO: wait CPU transition bit 16 & 17 off (STATUS)
>
> }

Dammit, this was supposed to be:
}? Or is the if supposed to end after the first wrmsr?

Sorry!
-Corey

Sorry :))) i have read this and yes, after the wrmsr, must have a }
problem with cut and paste to the email , the 80 character console :)

if (!(msr.lo & 0x10000)) {msr.lo|=0x10000;wrmsr(MSR_IA32_MISC_ENABLE,msr);}

And it works with C7 cpu, and uses the minimum voltage that accepts your CPU
and the maximum Speed Multiplier of your CPU.
I'm not sure if works on another CPU.

Mmm, i must download the last svn, for compare with that i have, with a diff.
Is different the auto.c, that i use, i cray for fit into the ROM_SIZE.
Initially i have working with a separate v8237 driver copied from another via
, but, finally, if i remember i use the entire v8237r version of Rudolf Marek.
I confirm that, when i can generate the pach for epia-cn, i'm at work :)

The CF8, is a missed parameter that i use in another program.
I use normally another PCI routines, i not remember why. I cray, for pass the
size as a parameter, better, if you use tables.
Ignore the CF8, and cut it :)

It is possible that your mainboard, starts with diferent parameters in the
bridge that not afect mine?

But wait for the DIFF results with the last version of SVN, to confirm if are
more easy the problem, and i can have forgotten extra changes.

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