coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

buildrom trac
by Ward Vandewege 02 Feb '08

02 Feb '08

Stepan gracefully configured trac for buildrom at http://tracker.coreboot.org/trac/buildrom Thanks! Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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[patch] add MSI MS-7135 support, try two
by jakllsch＠kollasch.net 02 Feb '08

02 Feb '08

Initial support for MSI MS-7135 (K8N Neo3) mainboard. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>

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v3 loads and starts filo on alix1c!
by ron minnich 02 Feb '08

02 Feb '08

Closer ... it's dying in pci init somewhere. It gets to 0:f.7 and then no more output. ron

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Testing results CN10000, Via chipsets CN700 and VT8237 with a C7 CPU, and a Kingstom DDR2 memory.
by Urbez Santana Roma 02 Feb '08

02 Feb '08

With my project RemoteBIOS and one elf portion of coreboot, i have tested the CN10000 mainboard, with the RAM initialization routines, written by Corey Osgood, and the code of VT8237R written by Rudolf Marek. I have found the first problem, that i have resolved, the memory initialization must use the 20 bit active when use a CBR memory comand: do_ram_command( RAM_COMMAND_MRS, 0x0022d8); must be: do_ram_command( RAM_COMMAND_MRS, 0x1022d8); do_ram_command( RAM_COMMAND_MRS, 0x21c20); must be: do_ram_command( RAM_COMMAND_MRS, 0x121c20); do_ram_command( RAM_COMMAND_MRS, 0x20020); must be: do_ram_command( RAM_COMMAND_MRS, 0x120020); Without the 20 bit active, the Kingstom Memory not works. The detection of SPD: The ram returns: SPD_DENSITY_OF_EACH_ROW_ON_MODULE=0x80 SPD_NUM_BANKS_PER_SDRAM=0x04 With the last code of corey, the result of configuration for PCI(0,0,3)[0x40] are 0x08, and is the correct value for the 512MB RAM that i have. Be careful, with that, i not use ROMCC for generate the code of the function sdram_set_spd_registers() written by Corey, i use directly gcc with xmmstack. The code of disable SATA works, but the normal IDE does not apear too, with the disable_sata() function. If you use the function, SATA and IDE goes disabled, i have ignored at the moment these function, y must investigate what happends. I have generated the fadt and the dsdt with the genfadt and gendsdt and, ACPI works fine. I must force the kernel with acpi=force, and enable lapic, changing the code of the Linux kernel, that do not support for Centaur Vendors, and then both ACPI and the LAPIC works. All IRQ's works good, and the linux works. What not works? the control of the Memory in the SuperIO, none of the features, can control the memory with DMA, for example VIA-Rhine, and VIA VT82xxx IDE. Then i must in the kernel write the parameter ide=nodma. And then the Linux works, without DMA, and without complete work with the Ethernet, are detected, but fails in the first interrupt. I are testing more, how to enable the access of the southbrigde to the memory, for DMA actions, but i not have documentation, but can test the southbrigde PCI configurations, with relative speed, only changing a script, for test. I say us, if i have luck. Thanks all for read this.

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LinuxWorld Expo 2008 San Francisco Aug 4-7
by joe＠smittys.pointclark.net 02 Feb '08

02 Feb '08

Hello, Just wanted to let any of you Californians (you know who you are) that LinuxWorld Expo 2008 is coming and if you wanted to participate you probibly should get on board. I think this would be a great way for coreboot to get some exposure. Thanks - Joe

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LinuxBIOS on VIA EPIA EN15000
by bernhard.maenner＠mail.cablevision.at 02 Feb '08

02 Feb '08

I own a VIA EPIA EN15000 Motherboard see http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i… and I'd like to give LinuxBIOS a try. Linux lspci output is: 00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge 00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI Bridge 00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) 00:0e.0 Ethernet controller: VIA Technologies, Inc. VT6120/VT6121/VT6122 Gigabit Ethernet Adapter (rev 11) 00:0f.0 IDE interface: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller (rev 80) 00:0f.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86) 00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] 00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller (rev 60) 00:14.0 Multimedia video controller: Internext Compression Inc iTVC15 MPEG-2 Encoder (rev 01) 01:00.0 VGA compatible controller: VIA Technologies, Inc. UniChrome Pro IGP (rev 01) Super I/O chip is Winbond W83697HG BIOS chip is SST49LF004B The "Supported Device List" includes all main devices but I can't find C7/CN700 support in the current stable version coreboot v2 nor in coreboot v3. Is there a chance to get my board working ? Can anybody tell me what to do ?

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r3088 build service
by coreboot information 02 Feb '08

02 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ward" checked in revision 3088 to the coreboot source repository and caused the following changes: Change Log: This patch fixes the decoding of the IO address range 0x0820->0x0827 into the LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI interface of the IT8716 SIO chip. Changes : 1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some functions of a PNP device can have more than 12 resources (ex the GPIO function of IT8716f), in which case one could have an "array overflow" inside the device structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at device init time..) 2) - define resource masks for the GPIO function in src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO ranges which are set into the LPC bridge of the SB are very strange (f.ex.: 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching by the init code 3) - enable the flash SPI interface into src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource into the GPIO function). I know that this is problematic because not all m57sli boards are SPI, but .. do anyone have a better idea how to handle this?.. Signed-off-by: Florentin Demetrescu <echelon(a)free.fr> I (Ward) have verified your patch on a rev2 of this board (it works!) as well as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse side effects that I noticed, so I think this patch should go in. Acked-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3088&device=serengeti_chee… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] (resend2) fix the flashrom problem on m57sli boards with SPI flash
by Florentin Demetrescu 02 Feb '08

02 Feb '08

This patch fixes the decoding of the IO address range 0x0820->0x0827 into the LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI interface of the IT8716 SIO chip. Changes : 1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some functions of a PNP device can have more than 12 resources (ex the GPIO function of IT8716f), in which case one could have an "array overflow" inside the device structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at device init time..) 2) - define resource masks for the GPIO function in src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO ranges which are set into the LPC bridge of the SB are very strange (f.ex.: 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching by the init code 3) - enable the flash SPI interface into src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource into the GPIO function). I know that this is problematic because not all m57sli boards are SPI, but .. do anyone have a better idea how to handle this?.. Signed-off-by: Florentin Demetrescu <echelon(a)free.fr> Patch file attached. Thanks, Florentin PS: By the way, with all due respect, Gentlemen, I think that keeping 2 (potentially incoherent) sets of resource definitions for PNP devices in 2 different places (<mobo>/Config.lb vs. <sio>/superio.c) is trully brain dammaging.. Juste my 2 (euro-)cents

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r3087 build service
by coreboot information 02 Feb '08

02 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ward" checked in revision 3087 to the coreboot source repository and caused the following changes: Change Log: This patch reverses an erroneous change that sneaked in during r2972, and broke flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3087&device=serengeti_chee… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] #87: flashrom issues on m57sli-s4
by coreboot 02 Feb '08

02 Feb '08

#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: closed Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by ward): * status: assigned => closed * resolution: => fixed Comment: PLCC-based flashing was accidentally broken in r2972. This was fixed in r3087. SPI-based flashing is now also fixed since r3088, thanks to Florentin Demetrescu. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/87#comment:6> coreboot <http://www.coreboot.org/>

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coreboot February 2008