coreboot February 2008

coreboot@coreboot.org

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422 discussions

Re: [coreboot] #70: fix util/getpir so that the output will compile
by coreboot 09 Feb '08

09 Feb '08

#70: fix util/getpir so that the output will compile ------------------------------------------------------+--------------------- Reporter: Jon Dufresne <jon.dufresne(a)gmail.com> | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: patch needs review ------------------------------------------------------+--------------------- Changes (by hailfinger): * patchstatus: patch needs work => patch needs review Comment: Signoff is there, can someone review? -- Ticket URL: <http://tracker.linuxbios.org/trac/coreboot/ticket/70#comment:3> coreboot <http://www.coreboot.org/>

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r3099 build service
by coreboot information 09 Feb '08

09 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3099 to the coreboot source repository and caused the following changes: Change Log: Flashrom: Add board enable for VIA EPIA SP. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3099&device=serengeti_chee… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] flashrom: Add board enable for VIA EPIA SP.
by Corey Osgood 09 Feb '08

09 Feb '08

Wonder if it's possible to set gmail's default reply to reply all. Anyways, forgotten again, but I'll add some extra info to make it worthwhile. Here's lspci -xxx from the vt8237r's lpc controller, on jetway j7f2w running ubuntu (I think): 00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] 00: 06 11 27 32 87 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 27 32 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 c0 f8 0b 00 00 00 00 0c 20 00 00 04 00 0a 08 50: 80 99 09 00 00 00 00 00 62 80 00 08 00 00 00 00 60: 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 00 70: 06 11 27 32 00 00 00 00 00 00 00 00 20 00 00 00 80: 20 84 59 00 b2 30 00 00 01 04 00 00 06 18 00 00 90: 00 40 08 88 a0 c0 38 00 00 c1 20 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 05 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 09 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 0b 00 00 00 00 00 00 00 00 00 On Feb 6, 2008 3:30 PM, Corey Osgood <corey.osgood(a)gmail.com> wrote: > On Feb 6, 2008 3:17 PM, Luc Verhaegen <libv(a)skynet.be> wrote: > > > On Wed, Feb 06, 2008 at 07:59:48PM +0100, Luc Verhaegen wrote: > > > On Wed, Feb 06, 2008 at 07:05:46PM +0100, Uwe Hermann wrote: > > > > On Tue, Feb 05, 2008 at 09:47:18PM +0100, Luc Verhaegen wrote: > > > > > + dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ > > > > > > > > Is this really meant to be VT8237 or should it be VT8237R? > > > > > > Hrm... Took the disk out already :( Chip itself is covered by a > > > heatsink. > > > > > > The machine i needed to flash the bios for has a VT8237A, and this has > > > 0x3337 for the ISA bridge. > > > > > > pciids.sf.net has the SP device down for a plain VT8237, confirms > > > the VT8237A and has 0x3372 for VT8237S. > > > > > > I'll guess i'll just give in and install a new suse for the p4m900 and > > > return the other disk to its original owner (the SP). > > > > > > > Nope... lspci lists nothing VT8237Rish... Just plain VT8237. > > > > Luc Verhaegen. > > SUSE/Novell X Driver Developer. > > > > > I'm looking at the datasheets and my own lspcis (I have removed the > heatsink on one board), and 0x3227 is indeed the VT8237R/R Plus (not sure > what the Plus adds, but I've got it). Via's website should also say, if you > dig through the marketing garbage. > > -Corey >

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r3099 - trunk/util/flashrom
by svn＠coreboot.org 09 Feb '08

09 Feb '08

Author: hailfinger Date: 2008-02-09 03:03:06 +0100 (Sat, 09 Feb 2008) New Revision: 3099 Modified: trunk/util/flashrom/board_enable.c Log: Flashrom: Add board enable for VIA EPIA SP. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-02-08 10:10:57 UTC (rev 3098) +++ trunk/util/flashrom/board_enable.c 2008-02-09 02:03:06 UTC (rev 3099) @@ -3,7 +3,7 @@ * * Copyright (C) 2005-2007 coresystems GmbH <stepan(a)coresystems.de> * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007 Luc Verhaegen <libv(a)skynet.be> + * Copyright (C) 2007-2008 Luc Verhaegen <libv(a)skynet.be> * Copyright (C) 2007 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify @@ -213,6 +213,28 @@ } /** + * Suited for VIAs EPIA SP. + */ +static int board_via_epia_sp(const char *name) +{ + struct pci_dev *dev; + uint8_t val; + + dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); + return -1; + } + + /* All memory cycles, not just ROM ones, go to LPC */ + val = pci_read_byte(dev, 0x59); + val &= ~0x80; + pci_write_byte(dev, 0x59, val); + + return 0; +} + +/** * Suited for ASUS P5A. * * This is rather nasty code, but there's no way to do this cleanly. @@ -393,6 +415,8 @@ NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx}, + {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, + NULL, NULL, "VIA EPIA SP", board_via_epia_sp}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx}, {0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000,

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goal for march summit
by ron minnich 08 Feb '08

08 Feb '08

I think our goal should be to get our first v3 port to the k8. We need a good, simple, cheap, target board with really common IO (i.e. PATA, serial, etc.) Any ideas? ron

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Geode LX/CS5536 VSA
by Marc Jones 08 Feb '08

08 Feb '08

Geode LX/CS5536 VSA has been updated. The source and binary are attached. With this release we have changed how the binary is packaged. Previously it was posted alread compressed with nrv2b and padded to size. Going forward it is GZipd and will need to be compressed and padded by hand or by buildrom. Instructions available here: http://www.coreboot.org/AMD_Geode_Porting_Guide The following changes were made: Remove int15 callbacks removed. CPU and memory are calculated by VSA. VSA no longer takes all the MFGPTs. Two are now available for OS use. The VSA binary is always available here: http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.… buildrom and v2 patches to follow. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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Which BIOS Savior for IWILL DK8_HTX ?
by Marco Zavaroni 08 Feb '08

08 Feb '08

Hi All, I have an HP Prolient DL145 server on order and want to use coreboot with it. It uses the IWILL DK8_HTX motherboard and I want to order a BIOS savior. Can someone please confirm that this IWILL motherboard uses a SST 49LF004B Flash ? Thanks, Marco

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alix1c current state
by ron minnich 08 Feb '08

08 Feb '08

This patch (which is NOT signed off) adds (or tries to) PIRQ support for the alix1c. it crashes and burns badly, however, I don' t know why. Marc, is 0xf0000 set up as memory in the v3 port? I am not sure. It dies at a strange point: PCI: devfn 0x9, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev 0x00000000(c) PCI: devfn 0xa pci_scan_get_dev: list is 0x00087eb8, *list is 0x0000b060 pci_scan_get_dev: check dev southbridge pci_scan_get_dev: check dev southbridge it has devfn 0x78 pci_scan_get_dev: check dev superio superio: Unknown device path type: 0 pci_scan_get_dev: child superio() not a pci device: it's type 0 PCI: pci_scan_bus pci_scan_get_dev returns dev None (no dev in tree yet) new_device: devcnt 1 I can't see why it would die here. At the same time, I am not sure that we're not losing what's in the serial FIFO. Lots of FIFO action here. In fact, to help serial out run faster, I do this: cat /dev/ttyS0 instead of running minicom! I have seen minicom buffering almost 30-40 seconds of serial output once I turn the alix off. Or, something is buffering it. Flow control is OFF in minicom. Note that if I comment out this line: select PIRQ_TABLE in mainboard/pcengines/Kconfig, this bios builds and runs fine. weird. ron

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r581 - coreboot-v3/device
by svn＠coreboot.org 08 Feb '08

08 Feb '08

Author: rminnich Date: 2008-02-08 16:57:02 +0100 (Fri, 08 Feb 2008) New Revision: 581 Modified: coreboot-v3/device/pci_device.c Log: Trivial patch: for an id, use DEVICE_ID_PCI, not DEVICE_PATH_PCI. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2008-02-08 12:15:46 UTC (rev 580) +++ coreboot-v3/device/pci_device.c 2008-02-08 15:57:02 UTC (rev 581) @@ -972,7 +972,7 @@ devfn, id); return NULL; } - devid.type = DEVICE_PATH_PCI; + devid.type = DEVICE_ID_PCI; devid.u.pci.vendor = id & 0xffff; devid.u.pci.device = id >> 16; dev = alloc_dev(bus, &dummy.path, &devid);

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Coreboot-v2 qemu target rename
by Myles Watson 08 Feb '08

08 Feb '08

Coreboot-v3 calls the qemu board qemu-x86, but Coreboot-v2 calls it qemu-i386. I think that qemu-x86 should be the preferred name. Does anyone have any reservations about the switch to qemu-x86 in Coreboot-v2? Thanks, Myles

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coreboot February 2008