coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

dts proposal
by ron minnich 11 Feb '08

11 Feb '08

This is a possible dts for alix1c. This actually builds and works, but linux panics, so that's an issue, but how does it look? ron

2 2

is ACPI a superset of _MP_ or not?
by ron minnich 11 Feb '08

11 Feb '08

I thought ACPI was a superset of _MP_. I have a friend who claims not: "0xffffffffffff0390 A P I C Local APIC Address 0xfee00000, flags 0x00000001 type 0, length 8 ACPI Processor ID 1 APIC ID 0 Flags 0x00000001 type 0, length 8 ACPI Processor ID 2 APIC ID 1 Flags 0x00000001 type 0, length 8 ACPI Processor ID 3 APIC ID 2 Flags 0x00000001 type 0, length 8 ACPI Processor ID 4 APIC ID 3 Flags 0x00000001 type 1, length 12 I/O APIC ID 4 I/O APIC Address 0xfec00000 Global System Interrupt Base 0x00000000 type 1, length 12 I/O APIC ID 5 I/O APIC Address 0xfe6fe000 Global System Interrupt Base 0x00000018 type 1, length 12 I/O APIC ID 6 I/O APIC Address 0xfe6ff000 Global System Interrupt Base 0x0000001c type 2, length 10 IRQ 0 Global System Interrupt 0x00000002 Flags 0x0000 type 2, length 10 IRQ 0 Global System Interrupt 0x00000002 Flags 0x0000 there's not enough info there to actually do anything." Is he missing something? Is this old information? I'd like to know. thanks ron

5 19

Re: [coreboot] LBv2: asus A8NE - Filling 2 pci slots --> no VGA/boot
by Baski 10 Feb '08

10 Feb '08

> rom address for PCI: 01:06.0 = f4080000 > PCI Expansion ROM, signature 0xaa55, INIT size 0x8000, data ptr 0x0144 > PCI ROM Image, Vendor 5333, Device 8a01, > PCI ROM Image, Class Code 000003, Code Type 00 > Class Code mismatch ROM 00000003, dev 00030000 > copying non-VGA ROM Image from 0xf4080000 to 0xd0000, 0x8000 bytes This is an S3 Virge graphics card. Could you try with a different graphics card too? I'll try. I don't have any other right now. > entering emulator > un-inited int vector > halt_sys: file /home/xxxx/Desktop/coreboot-v2-3100/src/devices/emulator/x86emu/ops.c, line 4387 And while un-inited int vector means that some int call in the ROM was unsuccessful the ROM seems to exit as it should. > PCI: 01:07.0 init > rom address for PCI: 01:07.0 = f4000000 > PCI Expansion ROM, signature 0xaa55, INIT size 0xc000, data ptr 0x0038 > PCI ROM Image, Vendor 1095, Device 0680, > PCI ROM Image, Class Code 010400, Code Type 00 > copying non-VGA ROM Image from 0xf4000000 to 0xd8000, 0xc000 bytes > entering emulator Here coreboot tries to execute also the ROM on the Silicon Image PCI0680 ATA-133 controller, and if this is the last output you get on serial, it fails. Removing the ATA card really doesn't change anything? //Peter After removing the ATA card, the system boots to Linux. But I need to use that card. Thx - baski --------------------------------- Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now.

2 1

r587 - in coreboot-v3: arch/x86 include/arch/x86
by svn＠coreboot.org 10 Feb '08

10 Feb '08

Author: hailfinger Date: 2008-02-11 02:30:24 +0100 (Mon, 11 Feb 2008) New Revision: 587 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/stage0_i586.S coreboot-v3/include/arch/x86/amd_geodelx.h Log: CAR size and CAR base defines are scattered all over the place. Set them centrally from Kconfig, but keep the Kconfig variables hidden. That way, they are available everywhere, you don't have to try to guess where they are set, and they come with help text if you look at arch/x86/Kconfig. No semantic changes, although some of the settings really could use an overhaul. This also is a requirement for my printk buffer patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-02-11 00:41:17 UTC (rev 586) +++ coreboot-v3/arch/x86/Kconfig 2008-02-11 01:30:24 UTC (rev 587) @@ -69,4 +69,17 @@ coreboot work correctly on symmetric multi processor systems. It is usually set in mainboard/*/Kconfig. - + +config CARBASE + hex + default 0x8f000 if CPU_I586 + default 0x80000 if CPU_AMD_GEODELX + help + This option sets the base address of the area used for CAR. + +config CARSIZE + hex + default 0x1000 if CPU_I586 + default 0x8000 if CPU_AMD_GEODELX + help + This option sets the size of the area used for CAR. Modified: coreboot-v3/arch/x86/stage0_i586.S =================================================================== --- coreboot-v3/arch/x86/stage0_i586.S 2008-02-11 00:41:17 UTC (rev 586) +++ coreboot-v3/arch/x86/stage0_i586.S 2008-02-11 01:30:24 UTC (rev 587) @@ -183,18 +183,9 @@ * the other is very similar to the AMD CAR, except remove amd specific msr */ -#ifndef CONFIG_CARSIZE -#define CacheSize 4096 -#else #define CacheSize CONFIG_CARSIZE -#endif -/* pick a safer value for default -- i.e. not the C segment! */ -#ifndef CONFIG_CARBASE -#define CacheBase (0x90000 - CacheSize) -#else #define CacheBase CONFIG_CARBASE -#endif #define ASSEMBLY #include "mtrr.h" Modified: coreboot-v3/include/arch/x86/amd_geodelx.h =================================================================== --- coreboot-v3/include/arch/x86/amd_geodelx.h 2008-02-11 00:41:17 UTC (rev 586) +++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-02-11 01:30:24 UTC (rev 587) @@ -565,8 +565,8 @@ #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ /* ------------------------ */ -#define DCACHE_RAM_SIZE 0x08000 -#define DCACHE_RAM_BASE 0x80000 +#define DCACHE_RAM_SIZE CONFIG_CARSIZE +#define DCACHE_RAM_BASE CONFIG_CARBASE /* This is where the DCache will be mapped and be used as stack. It would be * cool if it was the same base as coreboot normal stack. */

1 0

LBv2: asus A8NE - Filling 2 pci slots --> no VGA/boot
by Baski 10 Feb '08

10 Feb '08

Hi, In my asus a8ne, if I add any PCI card in addition to aPCI VGA card, there is no VGA output. Linux doesn't boot either. Tried different slots. There is a debug print "un-inited int vector". This debug print comes even when VGA card alone was present. The additional card is a PCI CF-ide card with Vendor id 1095, Device id 0680. Any help would be appreciated very much. Thanks. ----------------- serial out with debug_level 9 -------------------- coreboot-2.0.0_Fallback Sun Feb 10 12:32:03 PST 2008 starting... Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: 01 SBLink=00 NC node|link=00 ht reset - coreboot-2.0.0_Fallback Sun Feb 10 12:32:03 PST 2008 starting... Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: 01 SBLink=00 NC node|link=00 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 200Mhz Interleaved RAM: 0x00100000 KB Ram3 Initializing memory: done Ram4 v_esp=000ced4c testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Copying coreboot to RAM. src=fffdf000 dst=00004000 linxbios_ram.nrv2b length = 0000dfe2 linxbios_ram.bin length = 0002690c Jumping to coreboot. coreboot-2.0.0_Fallback Sun Feb 10 12:32:03 PST 2008 booting... Enumerating buses... scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled malloc Enter, size 1100, free_mem_ptr 00032000 malloc 0x00032000 CPU: APIC: 01 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: devfn 0xc4, bad id 0xffffffff PCI: devfn 0xc5, bad id 0xffffffff PCI: devfn 0xc6, bad id 0xffffffff PCI: devfn 0xc7, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: 00:00.0 [10de/005e] ops PCI: 00:00.0 [10de/005e] enabled Capability: 0x08 @ 0x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 000f PCI: 00:00.0 [10de/005e] enabled next_unitid: 000f PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/005e] enabled PCI: 00:01.0 [10de/0050] bus ops PCI: 00:01.0 [10de/0050] enabled PCI: 00:01.1 [10de/0052] bus ops PCI: 00:01.1 [10de/0052] enabled PCI: devfn 0xa, bad id 0xffffffff PCI: devfn 0xb, bad id 0xffffffff PCI: devfn 0xc, bad id 0xffffffff PCI: devfn 0xd, bad id 0xffffffff PCI: devfn 0xe, bad id 0xffffffff PCI: devfn 0xf, bad id 0xffffffff PCI: 00:02.0 [10de/005a] ops PCI: 00:02.0 [10de/005a] enabled PCI: 00:02.1 [10de/005b] ops PCI: 00:02.1 [10de/005b] enabled PCI: devfn 0x12, bad id 0xffffffff PCI: devfn 0x13, bad id 0xffffffff PCI: devfn 0x14, bad id 0xffffffff PCI: devfn 0x15, bad id 0xffffffff PCI: devfn 0x16, bad id 0xffffffff PCI: devfn 0x17, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: 00:04.0 [10de/0059] ops PCI: 00:04.0 [10de/0059] disabled PCI: 00:04.1 [10de/0058] ops PCI: 00:04.1 [10de/0058] disabled PCI: devfn 0x22, bad id 0xffffffff PCI: devfn 0x23, bad id 0xffffffff PCI: devfn 0x24, bad id 0xffffffff PCI: devfn 0x25, bad id 0xffffffff PCI: devfn 0x26, bad id 0xffffffff PCI: devfn 0x27, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: 00:06.0 [10de/0053] ops PCI: 00:06.0 [10de/0053] enabled PCI: 00:07.0 [10de/0054] ops PCI: 00:07.0 [10de/0054] enabled PCI: 00:08.0 [10de/0055] ops PCI: 00:08.0 [10de/0055] enabled PCI: 00:09.0 [10de/005c] bus ops PCI: 00:09.0 [10de/005c] enabled PCI: 00:0a.0 [10de/0056] ops PCI: 00:0a.0 [10de/0056] enabled PCI: 00:0b.0 [10de/005d] bus ops PCI: 00:0b.0 [10de/005d] enabled PCI: 00:0c.0 [10de/005d] bus ops PCI: 00:0c.0 [10de/005d] enabled PCI: 00:0d.0 [10de/005d] bus ops PCI: 00:0d.0 [10de/005d] enabled PCI: 00:0e.0 [10de/005d] bus ops PCI: 00:0e.0 [10de/005d] enabled scan_static_bus for PCI: 00:01.0 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.1 scan_static_bus for PCI: 00:01.1 done do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 01 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff malloc Enter, size 1100, free_mem_ptr 0003244c malloc 0x0003244c PCI: 01:06.0 [5333/8a01] enabled malloc Enter, size 1100, free_mem_ptr 00032898 malloc 0x00032898 PCI: 01:07.0 [1095/0680] enabled PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 02 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 03 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 04 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:0e.0 PCI: pci_scan_bus for bus 05 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:09.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 01:07.0 20 * [0x00000000 - 0x0000000f] io PCI: 01:07.0 10 * [0x00000010 - 0x00000017] io PCI: 01:07.0 18 * [0x00000020 - 0x00000027] io PCI: 01:07.0 14 * [0x00000030 - 0x00000033] io PCI: 01:07.0 1c * [0x00000040 - 0x00000043] io PCI: 00:09.0 compute_allocate_io: base: 00000044 size: 00001000 align: 12 gran: 12 done PCI: 00:09.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 00:09.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:09.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 00:09.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:09.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:09.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 01:06.0 10 * [0x00000000 - 0x03ffffff] mem PCI: 01:07.0 30 * [0x04000000 - 0x0407ffff] mem PCI: 01:06.0 30 * [0x04080000 - 0x0408ffff] mem PCI: 01:07.0 24 * [0x04090000 - 0x040900ff] mem PCI: 00:09.0 compute_allocate_mem: base: 04090100 size: 04100000 align: 26 gran: 20 done PCI: 00:0b.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:0b.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 done PCI: 00:0b.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 02 io PCI: 00:0b.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0b.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0b.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:0b.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0b.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0b.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0c.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0c.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:0c.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0c.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 done PCI: 00:0c.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 03 io PCI: 00:0c.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0c.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0c.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0c.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0c.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:0c.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0c.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0c.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0c.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0c.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:0d.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0d.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:0d.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0d.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 done PCI: 00:0d.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 04 io PCI: 00:0d.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0d.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0d.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0d.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0d.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0d.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:0e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:0e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:0e.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:0e.0 compute_allocate_io: base: fffff000 size: 00000000 align: 12 gran: 12 done PCI: 00:0e.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 05 io PCI: 00:0e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:0e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:0e.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:0e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:0e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:0e.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:09.0 1c * [0x00000000 - 0x00000fff] io PCI: 00:01.0 60 * [0x00001000 - 0x000010ff] io PCI: 00:01.0 64 * [0x00001400 - 0x000014ff] io PCI: 00:01.0 68 * [0x00001800 - 0x000018ff] io PCI: 00:01.0 10 * [0x00001c00 - 0x00001c7f] io PCI: 00:01.1 20 * [0x00001c80 - 0x00001cbf] io PCI: 00:01.1 24 * [0x00001cc0 - 0x00001cff] io PCI: 00:01.1 10 * [0x00002000 - 0x0000201f] io PCI: 00:06.0 20 * [0x00002020 - 0x0000202f] io PCI: 00:07.0 20 * [0x00002030 - 0x0000203f] io PCI: 00:08.0 20 * [0x00002040 - 0x0000204f] io PCI: 00:07.0 10 * [0x00002050 - 0x00002057] io PCI: 00:07.0 18 * [0x00002060 - 0x00002067] io PCI: 00:08.0 10 * [0x00002070 - 0x00002077] io PCI: 00:08.0 18 * [0x00002080 - 0x00002087] io PCI: 00:0a.0 14 * [0x00002090 - 0x00002097] io PCI: 00:07.0 14 * [0x000020a0 - 0x000020a3] io PCI: 00:07.0 1c * [0x000020b0 - 0x000020b3] io PCI: 00:08.0 14 * [0x000020c0 - 0x000020c3] io PCI: 00:08.0 1c * [0x000020d0 - 0x000020d3] io PCI: 00:18.0 compute_allocate_io: base: 000020d4 size: 00003000 align: 12 gran: 12 done PCI: 00:18.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:09.0 20 * [0x00000000 - 0x040fffff] mem PCI: 00:01.0 14 * [0x04100000 - 0x04100fff] mem PCI: 00:02.0 10 * [0x04101000 - 0x04101fff] mem PCI: 00:07.0 24 * [0x04102000 - 0x04102fff] mem PCI: 00:08.0 24 * [0x04103000 - 0x04103fff] mem PCI: 00:0a.0 10 * [0x04104000 - 0x04104fff] mem PCI: 00:02.1 10 * [0x04105000 - 0x041050ff] mem PCI: 00:18.0 compute_allocate_mem: base: 04105100 size: 04200000 align: 26 gran: 20 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:18.0 1d8 * [0x00001000 - 0x00003fff] io Root Device compute_allocate_io: base: 00004000 size: 00003c00 align: 12 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:18.0 1b0 * [0x00000000 - 0x041fffff] mem PCI: 00:18.3 94 * [0x08000000 - 0x0bffffff] mem PCI: 00:18.0 1b8 * [0x0c000000 - 0x0bffffff] prefmem Root Device compute_allocate_mem: base: 0c000000 size: 0c000000 align: 26 gran: 0 done Done reading resources. Allocating VGA resource PCI: 01:06.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00003c00 align: 12 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:18.0 1d8 * [0x00001000 - 0x00003fff] io Root Device compute_allocate_io: base: 00004000 size: 00003000 align: 12 gran: 0 done Root Device compute_allocate_mem: base: f0000000 size: 0c000000 align: 26 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:18.0 1b0 * [0xf0000000 - 0xf41fffff] mem PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem PCI: 00:18.0 1b8 * [0xfc000000 - 0xfbffffff] prefmem Root Device compute_allocate_mem: base: fc000000 size: 0c000000 align: 26 gran: 0 done Root Device assign_resources, bus 0 link: 0 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 compute_allocate_io: base: 00001000 size: 00003000 align: 12 gran: 12 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:09.0 1c * [0x00001000 - 0x00001fff] io PCI: 00:01.0 60 * [0x00002000 - 0x000020ff] io PCI: 00:01.0 64 * [0x00002400 - 0x000024ff] io PCI: 00:01.0 68 * [0x00002800 - 0x000028ff] io PCI: 00:01.0 10 * [0x00002c00 - 0x00002c7f] io PCI: 00:01.1 20 * [0x00002c80 - 0x00002cbf] io PCI: 00:01.1 24 * [0x00002cc0 - 0x00002cff] io PCI: 00:01.1 10 * [0x00003000 - 0x0000301f] io PCI: 00:06.0 20 * [0x00003020 - 0x0000302f] io PCI: 00:07.0 20 * [0x00003030 - 0x0000303f] io PCI: 00:08.0 20 * [0x00003040 - 0x0000304f] io PCI: 00:07.0 10 * [0x00003050 - 0x00003057] io PCI: 00:07.0 18 * [0x00003060 - 0x00003067] io PCI: 00:08.0 10 * [0x00003070 - 0x00003077] io PCI: 00:08.0 18 * [0x00003080 - 0x00003087] io PCI: 00:0a.0 14 * [0x00003090 - 0x00003097] io PCI: 00:07.0 14 * [0x000030a0 - 0x000030a3] io PCI: 00:07.0 1c * [0x000030b0 - 0x000030b3] io PCI: 00:08.0 14 * [0x000030c0 - 0x000030c3] io PCI: 00:08.0 1c * [0x000030d0 - 0x000030d3] io PCI: 00:18.0 compute_allocate_io: base: 000030d4 size: 00003000 align: 12 gran: 12 done amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link <NULL> PCI: 00:18.0 1d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link 0> PCI: 00:18.0 compute_allocate_prefmem: base: fc000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_prefmem: base: fc000000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fbffffff] size 0x00000000 gran 0x14 prefmem <node 0 link 0> PCI: 00:18.0 compute_allocate_mem: base: f0000000 size: 04200000 align: 26 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:09.0 20 * [0xf0000000 - 0xf40fffff] mem PCI: 00:01.0 14 * [0xf4100000 - 0xf4100fff] mem PCI: 00:02.0 10 * [0xf4101000 - 0xf4101fff] mem PCI: 00:07.0 24 * [0xf4102000 - 0xf4102fff] mem PCI: 00:08.0 24 * [0xf4103000 - 0xf4103fff] mem PCI: 00:0a.0 10 * [0xf4104000 - 0xf4104fff] mem PCI: 00:02.1 10 * [0xf4105000 - 0xf41050ff] mem PCI: 00:18.0 compute_allocate_mem: base: f4105100 size: 04200000 align: 26 gran: 20 done PCI: 00:18.0 1b0 <- [0x00f0000000 - 0x00f41fffff] size 0x04200000 gran 0x14 mem <node 0 link 0> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x0000002c00 - 0x0000002c7f] size 0x00000080 gran 0x07 io PCI: 00:01.0 14 <- [0x00f4100000 - 0x00f4100fff] size 0x00001000 gran 0x0c mem PCI: 00:01.0 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io PNP: 002e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 71 <- [0x0000000002 - 0x0000000001] size 0x00000000 gran 0x00 irq PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.6 71 <- [0x0000000002 - 0x0000000001] size 0x00000000 gran 0x00 irq PNP: 002e.7 25 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 io PNP: 002e.7 27 <- [0x0000002540 - 0x000000253f] size 0x00000000 gran 0x00 io PNP: 002e.7 b2 <- [0x0000002100 - 0x00000020ff] size 0x00000000 gran 0x00 io PNP: 002e.7 ba <- [0x0000000100 - 0x00000000ff] size 0x00000000 gran 0x00 io PNP: 002e.7 c0 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 io PNP: 002e.7 c2 <- [0x0000002540 - 0x000000253f] size 0x00000000 gran 0x00 io PNP: 002e.7 c8 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 io PNP: 002e.7 ca <- [0x0000000500 - 0x00000004ff] size 0x00000000 gran 0x00 io PCI: 00:01.0 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io PCI: 00:01.1 20 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000002cc0 - 0x0000002cff] size 0x00000040 gran 0x06 io PCI: 00:02.0 10 <- [0x00f4101000 - 0x00f4101fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00f4105000 - 0x00f41050ff] size 0x00000100 gran 0x08 mem PCI: 00:06.0 20 <- [0x0000003020 - 0x000000302f] size 0x00000010 gran 0x04 io PCI: 00:07.0 10 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io PCI: 00:07.0 14 <- [0x00000030a0 - 0x00000030a3] size 0x00000004 gran 0x02 io PCI: 00:07.0 18 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io PCI: 00:07.0 1c <- [0x00000030b0 - 0x00000030b3] size 0x00000004 gran 0x02 io PCI: 00:07.0 20 <- [0x0000003030 - 0x000000303f] size 0x00000010 gran 0x04 io PCI: 00:07.0 24 <- [0x00f4102000 - 0x00f4102fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 10 <- [0x0000003070 - 0x0000003077] size 0x00000008 gran 0x03 io PCI: 00:08.0 14 <- [0x00000030c0 - 0x00000030c3] size 0x00000004 gran 0x02 io PCI: 00:08.0 18 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io PCI: 00:08.0 1c <- [0x00000030d0 - 0x00000030d3] size 0x00000004 gran 0x02 io PCI: 00:08.0 20 <- [0x0000003040 - 0x000000304f] size 0x00000010 gran 0x04 io PCI: 00:08.0 24 <- [0x00f4103000 - 0x00f4103fff] size 0x00001000 gran 0x0c mem PCI: 00:09.0 compute_allocate_io: base: 00001000 size: 00001000 align: 12 gran: 12 PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 01:07.0 20 * [0x00001000 - 0x0000100f] io PCI: 01:07.0 10 * [0x00001010 - 0x00001017] io PCI: 01:07.0 18 * [0x00001020 - 0x00001027] io PCI: 01:07.0 14 * [0x00001030 - 0x00001033] io PCI: 01:07.0 1c * [0x00001040 - 0x00001043] io PCI: 00:09.0 compute_allocate_io: base: 00001044 size: 00001000 align: 12 gran: 12 done PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:09.0 compute_allocate_mem: base: f0000000 size: 04100000 align: 26 gran: 20 PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 01:06.0 10 * [0xf0000000 - 0xf3ffffff] mem PCI: 01:07.0 30 * [0xf4000000 - 0xf407ffff] mem PCI: 01:06.0 30 * [0xf4080000 - 0xf408ffff] mem PCI: 01:07.0 24 * [0xf4090000 - 0xf40900ff] mem PCI: 00:09.0 compute_allocate_mem: base: f4090100 size: 04100000 align: 26 gran: 20 done PCI: 00:09.0 20 <- [0x00f0000000 - 0x00f40fffff] size 0x04100000 gran 0x14 bus 01 mem PCI: 00:09.0 assign_resources, bus 1 link: 0 PCI: 01:06.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a mem PCI: 01:06.0 30 <- [0x00f4080000 - 0x00f408ffff] size 0x00010000 gran 0x10 romem PCI: 01:07.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 01:07.0 14 <- [0x0000001030 - 0x0000001033] size 0x00000004 gran 0x02 io PCI: 01:07.0 18 <- [0x0000001020 - 0x0000001027] size 0x00000008 gran 0x03 io PCI: 01:07.0 1c <- [0x0000001040 - 0x0000001043] size 0x00000004 gran 0x02 io PCI: 01:07.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 01:07.0 24 <- [0x00f4090000 - 0x00f40900ff] size 0x00000100 gran 0x08 mem PCI: 01:07.0 30 <- [0x00f4000000 - 0x00f407ffff] size 0x00080000 gran 0x13 romem PCI: 00:09.0 assign_resources, bus 1 link: 0 PCI: 00:0a.0 10 <- [0x00f4104000 - 0x00f4104fff] size 0x00001000 gran 0x0c mem PCI: 00:0a.0 14 <- [0x0000003090 - 0x0000003097] size 0x00000008 gran 0x03 io PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 10f1/2891 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 10f1/2891 PCI: 00:01.0 cmd <- 0f ck804 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff ck804 lpc decode:PNP: 002e.3, base=0x00000378, end=0x0000037f ck804 lpc decode:PNP: 002e.4, base=0x00000290, end=0x00000297 ck804 lpc decode:PNP: 002e.4, base=0x00000000, end=0x00000007 ck804 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000067 ck804 lpc decode:PNP: 002e.5, base=0x00000064, end=0x0000006b ck804 lpc decode:PNP: 002e.7, base=0x00000000, end=0xffffffff ck804 lpc decode:PNP: 002e.7, base=0x00002540, end=0x0000253f ck804 lpc decode:PNP: 002e.7, base=0x00002100, end=0x000020ff ck804 lpc decode:PNP: 002e.7, base=0x00000100, end=0x000000ff ck804 lpc decode:PNP: 002e.7, base=0x00000000, end=0xffffffff ck804 lpc decode:PNP: 002e.7, base=0x00002540, end=0x0000253f ck804 lpc decode:PNP: 002e.7, base=0x00000000, end=0xffffffff ck804 lpc decode:PNP: 002e.7, base=0x00000500, end=0x000004ff PCI: 00:01.1 subsystem <- 10f1/2891 PCI: 00:01.1 cmd <- 01 PCI: 00:02.0 subsystem <- 10f1/2891 PCI: 00:02.0 cmd <- 02 PCI: 00:02.1 subsystem <- 10f1/2891 PCI: 00:02.1 cmd <- 02 PCI: 00:06.0 subsystem <- 10f1/2891 PCI: 00:06.0 cmd <- 01 PCI: 00:07.0 subsystem <- 10f1/2891 PCI: 00:07.0 cmd <- 03 PCI: 00:08.0 subsystem <- 10f1/2891 PCI: 00:08.0 cmd <- 03 PCI: 00:09.0 bridge ctrl <- 000b PCI: 00:09.0 cmd <- 07 PCI: 01:06.0 cmd <- 03 PCI: 01:07.0 cmd <- 03 PCI: 00:0a.0 subsystem <- 10f1/2891 PCI: 00:0a.0 cmd <- 03 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 00 PCI: 00:0e.0 bridge ctrl <- 0003 PCI: 00:0e.0 cmd <- 00 PCI: 00:18.1 subsystem <- 10f1/2891 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 10f1/2891 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device 20fb1 CPU: family 0f, model 2b, stepping 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent rev id = 0x0210, current patch id = 0x00000000 microcode: rev id does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: rev id does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: patch id to apply = 0x0000004d microcode: updated to patch id = 0x0000004d success CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4200+ Setting up local apic... apic_id: 0x00 done. ECC Disabled CPU #0 Initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 20fb1 Sending STARTUP #2 to 1. After apic_write. CPU: family 0f, model 2b, stepping 01 Startup point 1. Waiting for send to finish... +Enabling cache After Startup. Setting fixed MTRRs(0-88) type: UC Waiting for 1 CPUS to stop Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent rev id = 0x0210, current patch id = 0x00000000 microcode: rev id does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: rev id does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: patch id to apply = 0x0000004d microcode: updated to patch id = 0x0000004d success CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4200+ Setting up local apic... apic_id: 0x01 done. CPU #1 Initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:01.0 init for IRQ, reg 0x00000000 value 0x00000700 0x00000000 for IRQ, reg 0x00000001 value 0x00010000 0x00000000 for IRQ, reg 0x00000002 value 0x00010000 0x00000000 for IRQ, reg 0x00000003 value 0x00010000 0x00000000 for IRQ, reg 0x00000004 value 0x00010000 0x00000000 for IRQ, reg 0x00000005 value 0x00010000 0x00000000 for IRQ, reg 0x00000006 value 0x00010000 0x00000000 for IRQ, reg 0x00000007 value 0x00010000 0x00000000 for IRQ, reg 0x00000008 value 0x00010000 0x00000000 for IRQ, reg 0x00000009 value 0x00010000 0x00000000 for IRQ, reg 0x0000000a value 0x00010000 0x00000000 for IRQ, reg 0x0000000b value 0x00010000 0x00000000 for IRQ, reg 0x0000000c value 0x00010000 0x00000000 for IRQ, reg 0x0000000d value 0x00010000 0x00000000 for IRQ, reg 0x0000000e value 0x00010000 0x00000000 for IRQ, reg 0x0000000f value 0x00010000 0x00000000 for IRQ, reg 0x00000010 value 0x00010000 0x00000000 for IRQ, reg 0x00000011 value 0x00010000 0x00000000 for IRQ, reg 0x00000012 value 0x00010000 0x00000000 for IRQ, reg 0x00000013 value 0x00010000 0x00000000 for IRQ, reg 0x00000014 value 0x00010000 0x00000000 for IRQ, reg 0x00000015 value 0x00010000 0x00000000 for IRQ, reg 0x00000016 value 0x00010000 0x00000000 for IRQ, reg 0x00000017 value 0x00010000 0x00000000 set power on after power fail RTC Init Invalid CMOS LB checksum PNP: 002e.1 init PNP: 002e.3 init PNP: 002e.4 init PNP: 002e.5 init Keyboard init... PNP: 002e.6 init PNP: 002e.7 init PCI: 00:02.0 init PCI: 00:02.1 init PCI: 00:06.0 init IDE1 IDE0 PCI: 00:07.0 init SATA S SATA P PCI: 00:08.0 init SATA S SATA P PCI: 00:09.0 init dev_root mem base = 0x00f0000000 [0x50] <-- 0xf0000000 PCI: 00:0a.0 init PCI: 00:0b.0 init PCI: 00:0c.0 init PCI: 00:0d.0 init PCI: 00:0e.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 01:06.0 init rom address for PCI: 01:06.0 = f4080000 PCI Expansion ROM, signature 0xaa55, INIT size 0x8000, data ptr 0x0144 PCI ROM Image, Vendor 5333, Device 8a01, PCI ROM Image, Class Code 000003, Code Type 00 Class Code mismatch ROM 00000003, dev 00030000 copying non-VGA ROM Image from 0xf4080000 to 0xd0000, 0x8000 bytes entering emulator un-inited int vector halt_sys: file /home/gurpreet/Desktop/coreboot-v2-3100/src/devices/emulator/x86emu/ops.c, line 4387 PCI: 01:07.0 init rom address for PCI: 01:07.0 = f4000000 PCI Expansion ROM, signature 0xaa55, INIT size 0xc000, data ptr 0x0038 PCI ROM Image, Vendor 1095, Device 0680, PCI ROM Image, Class Code 010400, Code Type 00 copying non-VGA ROM Image from 0xf4000000 to 0xd8000, 0xc000 bytes entering emulator --------------------------------- Looking for last minute shopping deals? Find them fast with Yahoo! Search.

2 1

r586 - in coreboot-v3: arch/x86 include
by svn＠coreboot.org 10 Feb '08

10 Feb '08

Author: hailfinger Date: 2008-02-11 01:41:17 +0100 (Mon, 11 Feb 2008) New Revision: 586 Modified: coreboot-v3/arch/x86/stage1.c coreboot-v3/include/console.h Log: Add dump_mem_range to dump a memory range. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-02-10 22:52:39 UTC (rev 585) +++ coreboot-v3/arch/x86/stage1.c 2008-02-11 00:41:17 UTC (rev 586) @@ -66,6 +66,19 @@ // FIXME check integrity } + +void dump_mem_range(int msg_level, unsigned char *buf, int size) +{ + int i; + printk(msg_level, "dumping memrange %p size %i:\n", buf, size); + for (i = 0; i < size; i++) { + printk(msg_level, "%02x ", buf[i]); + if (i % 16 == 15) + printk(msg_level, "\n"); + } + return; +} + /* until we get rid of elf */ int legacy(struct mem_file *archive, char *name, void *where, struct lb_memory *mem) { Modified: coreboot-v3/include/console.h =================================================================== --- coreboot-v3/include/console.h 2008-02-10 22:52:39 UTC (rev 585) +++ coreboot-v3/include/console.h 2008-02-11 00:41:17 UTC (rev 586) @@ -49,5 +49,6 @@ SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))), int msg_level, const char *fmt, ...); SHARED(banner, void, int msg_level, const char *msg); +SHARED(dump_mem_range, void, int msg_level, unsigned char *buf, int size); #endif /* CONSOLE_H */

1 0

[PATCH] v3: make dev_phase2() output prettier
by Carl-Daniel Hailfinger 10 Feb '08

10 Feb '08

Make dev_phase2() output prettier. Remove redundant function name printing and double newlines. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-phase2_pretty/device/device.c =================================================================== --- LinuxBIOSv3-phase2_pretty/device/device.c (Revision 584) +++ LinuxBIOSv3-phase2_pretty/device/device.c (Arbeitskopie) @@ -742,17 +742,16 @@ post_code(POST_STAGE2_PHASE2_ENTER); printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { - printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname); - printk(BIOS_SPEW, "%s: ops %p ops->phase2_setup_scan_bus %p\n", - __FUNCTION__, dev->ops, + printk(BIOS_SPEW, + "%s: dev %s: ops %p ops->phase2_setup_scan_bus %p\n", + __FUNCTION__, dev->dtsname, dev->ops, dev->ops? dev->ops->phase2_setup_scan_bus : NULL); if (dev->ops && dev->ops->phase2_setup_scan_bus) { printk(BIOS_SPEW, - "Calling phase2 phase2_setup_scan_bus..."); + "Calling phase2 phase2_setup_scan_bus...\n"); dev->ops->phase2_setup_scan_bus(dev); - printk(BIOS_SPEW, " done"); + printk(BIOS_SPEW, "phase2_setup_scan_bus done\n"); } - printk(BIOS_SPEW, "\n"); } post_code(POST_STAGE2_PHASE2_DONE); -- http://www.hailfinger.org/

2 2

r585 - coreboot-v3/device
by svn＠coreboot.org 10 Feb '08

10 Feb '08

Author: hailfinger Date: 2008-02-10 23:52:39 +0100 (Sun, 10 Feb 2008) New Revision: 585 Modified: coreboot-v3/device/device.c Log: Make dev_phase2() output prettier. Remove redundant function name printing and double newlines. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-02-10 16:44:32 UTC (rev 584) +++ coreboot-v3/device/device.c 2008-02-10 22:52:39 UTC (rev 585) @@ -742,17 +742,16 @@ post_code(POST_STAGE2_PHASE2_ENTER); printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { - printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname); - printk(BIOS_SPEW, "%s: ops %p ops->phase2_setup_scan_bus %p\n", - __FUNCTION__, dev->ops, + printk(BIOS_SPEW, + "%s: dev %s: ops %p ops->phase2_setup_scan_bus %p\n", + __FUNCTION__, dev->dtsname, dev->ops, dev->ops? dev->ops->phase2_setup_scan_bus : NULL); if (dev->ops && dev->ops->phase2_setup_scan_bus) { printk(BIOS_SPEW, - "Calling phase2 phase2_setup_scan_bus..."); + "Calling phase2 phase2_setup_scan_bus...\n"); dev->ops->phase2_setup_scan_bus(dev); - printk(BIOS_SPEW, " done"); + printk(BIOS_SPEW, "phase2_setup_scan_bus done\n"); } - printk(BIOS_SPEW, "\n"); } post_code(POST_STAGE2_PHASE2_DONE);

1 0

[PATCH] v3: fix bug in ad-hoc archive finding code in mc146818rtc.c
by Carl-Daniel Hailfinger 10 Feb '08

10 Feb '08

I found another bug in LAR handling of the option table by staring at the logs. (Yes, I read logs.) Looking at the log of a qemu x86 boot, I'd say something is really broken. Look at the excerpts of my log quoted below: > [...] > LAR: Attempting to open 'fallback/initram/segment0'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > [...] > LAR: Attempting to open 'normal/initram/segment0'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: CHECK normal/initram/segment0 @ 0xfff040d0 > [...] > LAR: Attempting to open 'normal/stage2/segment0'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: CHECK normal/stage2/segment0 @ 0xfff00400 > [...] > LAR: Attempting to open 'normal/stage2/segment1'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: CHECK normal/stage2/segment1 @ 0xfff004c0 > [...] > LAR: Attempting to open 'normal/stage2/segment2'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: CHECK normal/stage2/segment2 @ 0xfff03f40 > [...] > LAR: Attempting to open 'normal/stage2/segment3'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > [...] > LAR: Attempting to open 'normal/option_table'. > LAR: Start 0xfffc0000 len 0x3c000 WTF?!? This start address is obviously very wrong. > LAR: seen member bootblock > LAR: File not found! Which results in not finding the option table. > [...] > LAR: Attempting to open 'normal/payload'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > [...] > LAR: Attempting to open 'normal/payload/segment0'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > [...] Short version of the above: > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfffc0000 len 0x3c000 <------BUG! > LAR: Start 0xfff00000 len 0x100000 > LAR: Start 0xfff00000 len 0x100000 The bug is in arch/x86/mc146818rtc.c: > struct cmos_option_table *get_option_table(void) > { > struct mem_file result, archive; > int ret; > > // FIXME - i want to be dynamic. > archive.len=(CONFIG_COREBOOT_ROMSIZE_KB-16)*1024; len is wrong. > archive.start=(void *)(0UL-(CONFIG_COREBOOT_ROMSIZE_KB*1024)); start is even more wrong. > ret = find_file(&archive, "normal/option_table", &result); > if (ret) { > printk(BIOS_ERR, "No such file '%s'.\n", > "normal/option_table"); > return (struct cmos_option_table *)NULL; > } > return (struct cmos_option_table *) result.start; > } Use the existing init_archive function to find the LAR in memory. This fixes the case where the option table was not found depending on a few unrelated parameters. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-optiontable/arch/x86/mc146818rtc.c =================================================================== --- LinuxBIOSv3-optiontable/arch/x86/mc146818rtc.c (Revision 583) +++ LinuxBIOSv3-optiontable/arch/x86/mc146818rtc.c (Arbeitskopie) @@ -183,9 +183,7 @@ struct mem_file result, archive; int ret; - // FIXME - i want to be dynamic. - archive.len=(CONFIG_COREBOOT_ROMSIZE_KB-16)*1024; - archive.start=(void *)(0UL-(CONFIG_COREBOOT_ROMSIZE_KB*1024)); + init_archive(&archive); ret = find_file(&archive, "normal/option_table", &result); if (ret) { Regards, Carl-Daniel -- http://www.hailfinger.org/

3 7

r584 - coreboot-v3/arch/x86
by svn＠coreboot.org 10 Feb '08

10 Feb '08

Author: hailfinger Date: 2008-02-10 17:44:32 +0100 (Sun, 10 Feb 2008) New Revision: 584 Modified: coreboot-v3/arch/x86/mc146818rtc.c Log: I found another bug in LAR handling of the option table by staring at the logs. (Yes, I read logs.) Looking at the log of a qemu x86 boot with a 1024 kB image, I'd say something is really broken. Excerpts of my log quoted below: > [...] > LAR: Attempting to open 'fallback/initram/segment0'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > [...] > LAR: Attempting to open 'normal/initram/segment0'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: CHECK normal/initram/segment0 @ 0xfff040d0 > [...] > LAR: Attempting to open 'normal/option_table'. > LAR: Start 0xfffc0000 len 0x3c000 WTF?!? This start address is obviously very wrong. > LAR: seen member bootblock > LAR: File not found! Which results in not finding the option table. > [...] > LAR: Attempting to open 'normal/payload'. > LAR: Start 0xfff00000 len 0x100000 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/stage2/segment2 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > [...] The bug is in arch/x86/mc146818rtc.c: > struct cmos_option_table *get_option_table(void) > { > struct mem_file result, archive; > int ret; > > // FIXME - i want to be dynamic. > archive.len=(CONFIG_COREBOOT_ROMSIZE_KB-16)*1024; We can't calculate len like that. Reasons: - We can't know at compile time how big the archive is going to be. - Subtracting 16 kB from the ROM size was needed when the bootblock was not part of the LAR. These times are long gone. > archive.start=(void *)(0UL-(CONFIG_COREBOOT_ROMSIZE_KB*1024)); Since the len calculation above is invalid, start is wrong as well. > ret = find_file(&archive, "normal/option_table", &result); > if (ret) { > printk(BIOS_ERR, "No such file '%s'.\n", > "normal/option_table"); > return (struct cmos_option_table *)NULL; > } > return (struct cmos_option_table *) result.start; > } Use the existing init_archive function to find the LAR in memory. This fixes the case where the option table was not found depending on a few unrelated parameters. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/mc146818rtc.c =================================================================== --- coreboot-v3/arch/x86/mc146818rtc.c 2008-02-09 21:16:42 UTC (rev 583) +++ coreboot-v3/arch/x86/mc146818rtc.c 2008-02-10 16:44:32 UTC (rev 584) @@ -183,9 +183,7 @@ struct mem_file result, archive; int ret; - // FIXME - i want to be dynamic. - archive.len=(CONFIG_COREBOOT_ROMSIZE_KB-16)*1024; - archive.start=(void *)(0UL-(CONFIG_COREBOOT_ROMSIZE_KB*1024)); + init_archive(&archive); ret = find_file(&archive, "normal/option_table", &result); if (ret) {

1 0

← Newer
1
...
26
27
28
29
30
31
32
...
43
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2008