coreboot February 2008

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77 participants
422 discussions

r609 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 18 Feb '08

18 Feb '08

Author: hailfinger Date: 2008-02-18 18:20:47 +0100 (Mon, 18 Feb 2008) New Revision: 609 Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts Log: Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The target does not yet compile due to initram breakage, but the breakage is really old. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-02-18 16:37:58 UTC (rev 608) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-02-18 17:20:47 UTC (rev 609) @@ -84,8 +84,26 @@ pci@1,0 { /config/("northbridge/amd/geodelx/pci"); }; - pci@1,1 { + pci@15,0 { /config/("southbridge/amd/cs5536/dts"); + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x00001002"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000effd"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + /* COM1 settings */ + com1_enable = "0"; + com1_address = "0x2f8"; + com1_irq = "3"; + /* COM2 settings */ + com2_enable = "1"; + com2_address = "0x3f8"; + com2_irq = "4"; }; }; };

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license header question
by Jonathan Sturges 18 Feb '08

18 Feb '08

I've been meaning to contribute a new Geode target I created some months ago but never got around to sending in. My target is based on another Geode GX1 target (Eaglelion 5BCM). Since this target's source was already missing the required license headers, do I go ahead and add the headers to the new target's files, or submit without? It seems unlikely the patch would be accepted without license headers, yet I can't vouch for the origin of the Eaglelion source files, so it would seem presumptuous of me to put a GPL license header in my target's files. What's the recommended way to handle this situation? thanks, Jonathan

4 3

[v3][patch] remove dead Geode defines
by Marc Jones 18 Feb '08

18 Feb '08

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Remove dead Geode defines. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelx.c 2008-02-15 14:33:16.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-15 15:47:51.000000000 -0700 @@ -32,114 +32,6 @@ extern void northbridge_init_early(void); extern void setup_realmode_idt(void); -/* Here is programming for the various MSRs. */ -#define IM_QWAIT 0x100000 - -/* Set in high nibble. */ -#define DMCF_WRITE_SERIALIZE_REQUEST (2 << 12) /* 2 outstanding */ - -#define DMCF_SERIAL_LOAD_MISSES 2 /* Enabled */ - -/* These are the 8-bit attributes for controlling RCONF registers. - * - * RCONF is Region CONFiguration, and controls caching and other - * attributes of a region. Just like MTRRs, only different. - */ -#define CACHE_DISABLE (1 << 0) -#define WRITE_ALLOCATE (1 << 1) -#define WRITE_PROTECT (1 << 2) -#define WRITE_THROUGH (1 << 3) -#define WRITE_COMBINE (1 << 4) -#define WRITE_SERIALIZE (1 << 5) - -/* RAM has none of this stuff. */ -#define RAM_PROPERTIES 0 -#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) -#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) -#define MSR_WS_CD_DEFAULT 0x21212121 - -/* RCONF registers 1810-1817 give you 8 registers with which to - * program protection regions the are region configuration range - * registers, or RRCF in msr terms, the are a straight base, top - * address assign, since they are 4k aligned. - */ -/* So no left-shift needed for top or base. */ -#define RRCF_LOW(base, properties) (base | (1 << 8) | properties) -#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) - -/* Build initializer for P2D MSR. - * - * This is complex enough that you are going to need to RTFM if you - * really want to understand it. - */ -#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pbase >> 24), \ - .lo = (pbase << 8) | pmask}} -#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \ - (poffset << 8) | (pbase >> 24), \ - .lo = (pbase << 8) | pmask}} -#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pmax >> 12), \ - .lo = (pmax << 20) | pmin}} -#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \ - (poffset << 8) | (pmax >> 12), \ - .lo = (pmax << 20) | pmin}} -#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (wen), \ - .lo = (ren << 16) | (pscbase >> 18)}} -#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (ibase >> 12), \ - .lo = (ibase << 20) | imask}} -#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28), \ - .lo = (en << 24) | (wen << 21) | \ - (ren << 20) | (ibase << 3)}} - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -/* TODO: Not used!? */ -static const struct msrinit msr_defaults[] = { - { 0x1700, {.hi = 0,.lo = IM_QWAIT}}, - { 0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, - .lo = DMCF_SERIAL_LOAD_MISSES}}, - - /* 1808 will be done down below, so we have to do 180a->1817 - * (well, 1813 really). - */ - /* For 180a, for now, we assume VSM will configure it. */ - /* 180b is left at reset value, a0000-bffff is non-cacheable. */ - /* 180c, c0000-dffff is set to write serialize and non-cachable. */ - /* Oops, 180c will be set by CPU bug handling in cpubug.c. */ - /* TODO: There's no cpubug.c. */ - // {0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, - /* 180d is left at default, e0000-fffff is non-cached. */ - /* We will assume 180e, the ssm region configuration, is left - * at default or set by VSM. - */ - /* We will not set 0x180f, the DMM, yet. */ - - // {0x1810, {.hi = 0xee7ff000, - // .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - // {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - // {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - // {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, - - /* Now for GLPCI routing. */ - - /* GLIU0 */ - P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - - /* GLIU1 */ - P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - - {0}, -}; /** * Currently not set up.

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r608 - coreboot-v3/northbridge/amd/geodelx
by svn＠coreboot.org 18 Feb '08

18 Feb '08

Author: mjones Date: 2008-02-18 17:37:58 +0100 (Mon, 18 Feb 2008) New Revision: 608 Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c Log: Remove dead Geode defines. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-18 01:43:50 UTC (rev 607) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-18 16:37:58 UTC (rev 608) @@ -32,115 +32,7 @@ extern void northbridge_init_early(void); extern void setup_realmode_idt(void); -/* Here is programming for the various MSRs. */ -#define IM_QWAIT 0x100000 -/* Set in high nibble. */ -#define DMCF_WRITE_SERIALIZE_REQUEST (2 << 12) /* 2 outstanding */ - -#define DMCF_SERIAL_LOAD_MISSES 2 /* Enabled */ - -/* These are the 8-bit attributes for controlling RCONF registers. - * - * RCONF is Region CONFiguration, and controls caching and other - * attributes of a region. Just like MTRRs, only different. - */ -#define CACHE_DISABLE (1 << 0) -#define WRITE_ALLOCATE (1 << 1) -#define WRITE_PROTECT (1 << 2) -#define WRITE_THROUGH (1 << 3) -#define WRITE_COMBINE (1 << 4) -#define WRITE_SERIALIZE (1 << 5) - -/* RAM has none of this stuff. */ -#define RAM_PROPERTIES 0 -#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) -#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) -#define MSR_WS_CD_DEFAULT 0x21212121 - -/* RCONF registers 1810-1817 give you 8 registers with which to - * program protection regions the are region configuration range - * registers, or RRCF in msr terms, the are a straight base, top - * address assign, since they are 4k aligned. - */ -/* So no left-shift needed for top or base. */ -#define RRCF_LOW(base, properties) (base | (1 << 8) | properties) -#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) - -/* Build initializer for P2D MSR. - * - * This is complex enough that you are going to need to RTFM if you - * really want to understand it. - */ -#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pbase >> 24), \ - .lo = (pbase << 8) | pmask}} -#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \ - (poffset << 8) | (pbase >> 24), \ - .lo = (pbase << 8) | pmask}} -#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pmax >> 12), \ - .lo = (pmax << 20) | pmin}} -#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \ - (poffset << 8) | (pmax >> 12), \ - .lo = (pmax << 20) | pmin}} -#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (wen), \ - .lo = (ren << 16) | (pscbase >> 18)}} -#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (ibase >> 12), \ - .lo = (ibase << 20) | imask}} -#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \ - {msr, {.hi = (pdid1 << 29) | (bizarro << 28), \ - .lo = (en << 24) | (wen << 21) | \ - (ren << 20) | (ibase << 3)}} - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -/* TODO: Not used!? */ -static const struct msrinit msr_defaults[] = { - { 0x1700, {.hi = 0,.lo = IM_QWAIT}}, - { 0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, - .lo = DMCF_SERIAL_LOAD_MISSES}}, - - /* 1808 will be done down below, so we have to do 180a->1817 - * (well, 1813 really). - */ - /* For 180a, for now, we assume VSM will configure it. */ - /* 180b is left at reset value, a0000-bffff is non-cacheable. */ - /* 180c, c0000-dffff is set to write serialize and non-cachable. */ - /* Oops, 180c will be set by CPU bug handling in cpubug.c. */ - /* TODO: There's no cpubug.c. */ - // {0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, - /* 180d is left at default, e0000-fffff is non-cached. */ - /* We will assume 180e, the ssm region configuration, is left - * at default or set by VSM. - */ - /* We will not set 0x180f, the DMM, yet. */ - - // {0x1810, {.hi = 0xee7ff000, - // .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - // {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - // {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - // {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, - - /* Now for GLPCI routing. */ - - /* GLIU0 */ - P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - - /* GLIU1 */ - P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - - {0}, -}; - /** * Currently not set up. *

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x86emu boot message
by joe＠smittys.pointclark.net 18 Feb '08

18 Feb '08

Can anyone help me why I am getting this boot message from x86emu?? halt_sys: file /home/joe/coreboot-v2/src/devices/emulator/x86emu/ops.c, line 4387 Thanks - Joe

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[PATCH] v3: update mainboard dts files to new style
by Carl-Daniel Hailfinger 17 Feb '08

17 Feb '08

Update mainboard dts files to new style. Untested, but I tried to keep the new settings as close as possible to the old settings. All GeodeLX-based boards now include the geodelx/domain, geodelx/apic and geodelx/pci dts files. Remove "enabled" keyword from the alix.1c main dts. (That's the only possibly critical change because it affects a working target. Tests on hardware appreciated. Should be harmless, though.) Compile tested only, and the situation is better than without the patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-dtsconversion/mainboard/adl/msm800sev/dts =================================================================== --- LinuxBIOSv3-dtsconversion/mainboard/adl/msm800sev/dts (Revision 605) +++ LinuxBIOSv3-dtsconversion/mainboard/adl/msm800sev/dts (Arbeitskopie) @@ -23,22 +23,19 @@ /{ mainboard-vendor = "Advanced Digital Logic"; mainboard-name = "MSM800SEV"; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; - superio { + ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; }; Index: LinuxBIOSv3-dtsconversion/mainboard/amd/norwich/dts =================================================================== --- LinuxBIOSv3-dtsconversion/mainboard/amd/norwich/dts (Revision 605) +++ LinuxBIOSv3-dtsconversion/mainboard/amd/norwich/dts (Arbeitskopie) @@ -19,23 +19,19 @@ */ /{ - enabled; mainboard-vendor = "AMD"; mainboard-name = "Norwich"; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; }; }; Index: LinuxBIOSv3-dtsconversion/mainboard/artecgroup/dbe61/dts =================================================================== --- LinuxBIOSv3-dtsconversion/mainboard/artecgroup/dbe61/dts (Revision 605) +++ LinuxBIOSv3-dtsconversion/mainboard/artecgroup/dbe61/dts (Arbeitskopie) @@ -75,21 +75,17 @@ /{ mainboard-vendor = "Artec Group"; mainboard-name = "DBE61"; - enabled; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; }; }; Index: LinuxBIOSv3-dtsconversion/mainboard/pcengines/alix1c/dts =================================================================== --- LinuxBIOSv3-dtsconversion/mainboard/pcengines/alix1c/dts (Revision 605) +++ LinuxBIOSv3-dtsconversion/mainboard/pcengines/alix1c/dts (Arbeitskopie) @@ -19,7 +19,6 @@ */ /{ - enabled; mainboard-vendor = "PC Engines"; mainboard-name = "ALIX1.C"; cpus { }; -- http://www.hailfinger.org/

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r607 - in coreboot-v3/mainboard: adl/msm800sev amd/norwich artecgroup/dbe61 pcengines/alix1c
by svn＠coreboot.org 17 Feb '08

17 Feb '08

Author: hailfinger Date: 2008-02-18 02:43:50 +0100 (Mon, 18 Feb 2008) New Revision: 607 Modified: coreboot-v3/mainboard/adl/msm800sev/dts coreboot-v3/mainboard/amd/norwich/dts coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/pcengines/alix1c/dts Log: Update mainboard dts files to new style. Untested, but I tried to keep the new settings as close as possible to the old settings. All GeodeLX-based boards now include the geodelx/domain, geodelx/apic and geodelx/pci dts files. Remove "enabled" keyword from the alix.1c main dts. (That's the only possibly critical change because it affects a working target. Tests on hardware appreciated. Should be harmless, though.) Compile tested only for msm800sev, norwich and dbe61, and the situation is better than without the patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested and boots a working linux on alix1c. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/adl/msm800sev/dts =================================================================== --- coreboot-v3/mainboard/adl/msm800sev/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/adl/msm800sev/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -23,22 +23,19 @@ /{ mainboard-vendor = "Advanced Digital Logic"; mainboard-name = "MSM800SEV"; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; - superio { + ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; }; Modified: coreboot-v3/mainboard/amd/norwich/dts =================================================================== --- coreboot-v3/mainboard/amd/norwich/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/amd/norwich/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -19,23 +19,19 @@ */ /{ - enabled; mainboard-vendor = "AMD"; mainboard-name = "Norwich"; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; }; }; Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -75,21 +75,17 @@ /{ mainboard-vendor = "Artec Group"; mainboard-name = "DBE61"; - enabled; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; }; }; Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -19,7 +19,6 @@ */ /{ - enabled; mainboard-vendor = "PC Engines"; mainboard-name = "ALIX1.C"; cpus { };

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[PATCH] v3: print name of compression algorithm
by Carl-Daniel Hailfinger 17 Feb '08

17 Feb '08

Print name of compression algorithm in addition to the corresponding number during boot. Convert process_file() to use enum compalgo instead of hardcoded "1","2","3" and change the control structure from a series of if() statements to a switch() statement. Compile and boot tested on Qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-algonaming/include/lar.h =================================================================== --- LinuxBIOSv3-algonaming/include/lar.h (Revision 605) +++ LinuxBIOSv3-algonaming/include/lar.h (Arbeitskopie) @@ -74,6 +74,24 @@ u64 loadaddress; }; +enum compalgo { + none = 0, + lzma = 1, + nrv2b = 2, + zeroes = 3, + /* invalid should always be the last entry. */ + invalid +}; + +static const char *algo_name[] = { + "", + "lzma", + "nrv2b", + "zeroes", + /* invalid should always be the last entry. */ + "invalid" +}; + struct mem_file { void *start; int len; Index: LinuxBIOSv3-algonaming/lib/lar.c =================================================================== --- LinuxBIOSv3-algonaming/lib/lar.c (Revision 605) +++ LinuxBIOSv3-algonaming/lib/lar.c (Arbeitskopie) @@ -147,36 +147,41 @@ int process_file(const struct mem_file *archive, void *where) { - printk(BIOS_SPEW, "LAR: Compression algorithm #%i used\n", archive->compression); + const char *algoname = algo_name[(archive->compression >= invalid) + ? invalid : archive->compression]; + printk(BIOS_SPEW, "LAR: Compression algorithm #%i (%s) used\n", + archive->compression, algoname); + switch (archive->compression) { /* no compression */ - if (archive->compression == 0) { + case none: memcpy(where, archive->start, archive->len); return 0; - } #ifdef CONFIG_COMPRESSION_LZMA /* lzma */ - unsigned long ulzma(unsigned char *src, unsigned char *dst); - if (archive->compression == 1) { + case lzma: { + unsigned long ulzma(unsigned char *src, unsigned char *dst); ulzma(archive->start, where); return 0; } #endif #ifdef CONFIG_COMPRESSION_NRV2B /* nrv2b */ - unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); - if (archive->compression == 2) { + case nrv2b: { + unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); unsigned long tmp; unrv2b(archive->start, where, &tmp); return 0; } #endif /* zeroes */ - if (archive->compression == 3) { + case zeroes: memset(where, 0, archive->reallen); return 0; + default: + printk(BIOS_INFO, "LAR: Compression algorithm #%i (%s) not" + " supported!\n", archive->compression, algoname); + return -1; } - printk(BIOS_INFO, "LAR: Compression algorithm #%i not supported!\n", archive->compression); - return -1; } /** Index: LinuxBIOSv3-algonaming/util/lar/lar.h =================================================================== --- LinuxBIOSv3-algonaming/util/lar/lar.h (Revision 605) +++ LinuxBIOSv3-algonaming/util/lar/lar.h (Arbeitskopie) @@ -92,7 +92,14 @@ u32 size; /**< Size of the mmaped file */ }; -enum compalgo { none = 0, lzma = 1, nrv2b = 2, zeroes = 3 }; +enum compalgo { + none = 0, + lzma = 1, + nrv2b = 2, + zeroes = 3, + /* invalid should always be the last entry. */ + invalid +}; typedef void (*compress_func) (char *, int, char *, int *); typedef void (*uncompress_func) (char *, int, char *, int); @@ -128,4 +135,6 @@ "lzma", "nrv2b", "zeroes", + /* invalid should always be the last entry. */ + "invalid" }; -- http://www.hailfinger.org/

3 5

r606 - in coreboot-v3: include lib util/lar
by svn＠coreboot.org 17 Feb '08

17 Feb '08

Author: hailfinger Date: 2008-02-18 01:48:25 +0100 (Mon, 18 Feb 2008) New Revision: 606 Modified: coreboot-v3/include/lar.h coreboot-v3/lib/lar.c coreboot-v3/util/lar/lar.c coreboot-v3/util/lar/lar.h coreboot-v3/util/lar/stream.c Log: Print name of compression algorithm in addition to the corresponding number during boot. Convert process_file() to use enum compalgo instead of hardcoded "1","2","3" and change the control structure from a series of if() statements to a switch() statement. Uppercasing enum compalgo also found a name clash between NONE as compression algo and NONE as operation mode of util/lar. Compile and boot tested on Qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/include/lar.h =================================================================== --- coreboot-v3/include/lar.h 2008-02-16 19:18:32 UTC (rev 605) +++ coreboot-v3/include/lar.h 2008-02-18 00:48:25 UTC (rev 606) @@ -74,6 +74,15 @@ u64 loadaddress; }; +enum compalgo { + ALGO_NONE = 0, + ALGO_LZMA = 1, + ALGO_NRV2B = 2, + ALGO_ZEROES = 3, + /* invalid should always be the last entry. */ + ALGO_INVALID +}; + struct mem_file { void *start; int len; Modified: coreboot-v3/lib/lar.c =================================================================== --- coreboot-v3/lib/lar.c 2008-02-16 19:18:32 UTC (rev 605) +++ coreboot-v3/lib/lar.c 2008-02-18 00:48:25 UTC (rev 606) @@ -31,6 +31,15 @@ #define ntohl(x) (x) #endif +static const char *algo_name[] = { + "none", + "lzma", + "nrv2b", + "zeroes", + /* invalid should always be the last entry. */ + "invalid" +}; + /** * run_address is passed the address of a function taking no parameters and * jumps to it, returning the result. @@ -147,36 +156,41 @@ int process_file(const struct mem_file *archive, void *where) { - printk(BIOS_SPEW, "LAR: Compression algorithm #%i used\n", archive->compression); + const char *algoname = algo_name[(archive->compression >= ALGO_INVALID) + ? ALGO_INVALID : archive->compression]; + printk(BIOS_SPEW, "LAR: Compression algorithm #%i (%s) used\n", + archive->compression, algoname); + switch (archive->compression) { /* no compression */ - if (archive->compression == 0) { + case ALGO_NONE: memcpy(where, archive->start, archive->len); return 0; - } #ifdef CONFIG_COMPRESSION_LZMA /* lzma */ - unsigned long ulzma(unsigned char *src, unsigned char *dst); - if (archive->compression == 1) { + case ALGO_LZMA: { + unsigned long ulzma(unsigned char *src, unsigned char *dst); ulzma(archive->start, where); return 0; } #endif #ifdef CONFIG_COMPRESSION_NRV2B /* nrv2b */ - unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); - if (archive->compression == 2) { + case ALGO_NRV2B: { + unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); unsigned long tmp; unrv2b(archive->start, where, &tmp); return 0; } #endif /* zeroes */ - if (archive->compression == 3) { + case ALGO_ZEROES: memset(where, 0, archive->reallen); return 0; + default: + printk(BIOS_INFO, "LAR: Compression algorithm #%i (%s) not" + " supported!\n", archive->compression, algoname); + return -1; } - printk(BIOS_INFO, "LAR: Compression algorithm #%i not supported!\n", archive->compression); - return -1; } /** Modified: coreboot-v3/util/lar/lar.c =================================================================== --- coreboot-v3/util/lar/lar.c 2008-02-16 19:18:32 UTC (rev 605) +++ coreboot-v3/util/lar/lar.c 2008-02-18 00:48:25 UTC (rev 606) @@ -40,7 +40,7 @@ static int iselfparse = 0; static long larsize = 0; static char *bootblock = NULL; -enum compalgo algo = none; +enum compalgo algo = ALGO_NONE; static void usage(char *name) { @@ -272,10 +272,10 @@ break; case 'C': if (strcasecmp("lzma", optarg) == 0) { - algo = lzma; + algo = ALGO_LZMA; } if (strcasecmp("nrv2b", optarg) == 0) { - algo = nrv2b; + algo = ALGO_NRV2B; } break; case 'l': Modified: coreboot-v3/util/lar/lar.h =================================================================== --- coreboot-v3/util/lar/lar.h 2008-02-16 19:18:32 UTC (rev 605) +++ coreboot-v3/util/lar/lar.h 2008-02-18 00:48:25 UTC (rev 606) @@ -92,7 +92,14 @@ u32 size; /**< Size of the mmaped file */ }; -enum compalgo { none = 0, lzma = 1, nrv2b = 2, zeroes = 3 }; +enum compalgo { + ALGO_NONE = 0, + ALGO_LZMA = 1, + ALGO_NRV2B = 2, + ALGO_ZEROES = 3, + /* invalid should always be the last entry. */ + ALGO_INVALID +}; typedef void (*compress_func) (char *, int, char *, int *); typedef void (*uncompress_func) (char *, int, char *, int); @@ -124,8 +131,10 @@ }; static const char *algo_name[] = { - "", + "none", "lzma", "nrv2b", "zeroes", + /* invalid should always be the last entry. */ + "invalid" }; Modified: coreboot-v3/util/lar/stream.c =================================================================== --- coreboot-v3/util/lar/stream.c 2008-02-16 19:18:32 UTC (rev 605) +++ coreboot-v3/util/lar/stream.c 2008-02-18 00:48:25 UTC (rev 606) @@ -147,7 +147,7 @@ fprintf(stderr, "Dropping empty section\n"); continue; } - thisalgo = zeroes; + thisalgo = ALGO_ZEROES; if (verbose()) fprintf(stderr, "New section addr %#x size %#x\n", (u32)shdr[i].sh_addr, (u32)shdr[i].sh_size); @@ -565,7 +565,7 @@ if (file_in_list(files, filename)) { printf(" %s ", filename); - if (ntohl(header->compression) == none) { + if (ntohl(header->compression) == ALGO_NONE) { printf("(%d bytes @0x%lx);", ntohl(header->len), (unsigned long)(ptr - lar->map) + @@ -669,7 +669,7 @@ if (file_in_list(files, filename)) { - if (ntohl(header->compression) == none) { + if (ntohl(header->compression) == ALGO_NONE) { ret = _write_file(filename, (u8 *) (ptr + ntohl(header->offset)), (u32) ntohl(header->len)); @@ -730,7 +730,7 @@ if (!strncmp(name, "nocompress:",11)) { filename += 11; - *thisalgo = none; + *thisalgo = ALGO_NONE; } /* this is dangerous */ @@ -846,8 +846,8 @@ int complen; compress_functions[*thisalgo](ptr, size, temp, &complen); - if (complen >= size && (*thisalgo != none)) { - *thisalgo = none; + if (complen >= size && (*thisalgo != ALGO_NONE)) { + *thisalgo = ALGO_NONE; compress_functions[*thisalgo](ptr, size, temp, &complen); } return complen;

1 0

EPIA MII Cannot load ELF image.
by Jacek Chruscik 17 Feb '08

17 Feb '08

Hi everybody, This is my first attempt to replace legacy BIOS with coreboot. I test on via epia m2 board, and I managed to compile fallback image with filo payload. ROM was programmed and verified OK. I ended up with a problem "loading" payload. The payload is in ROM image (beginning of file) and it is in ELF format. I decided to skip VGA bios at this time to exclude any potential failures, but I know it works (managed to merge vga bios to the rom image and it initialized the video). Second weird thing is that before I see any log on my serial console, it takes like 6-7 seconds from power-up. Is this normal? If you have any experience with such problem, I'll appreciate any help. Thanks I logged the boot process through serial console, here's the transcript: ---------------------------------------------------------------------------------------------------------------------------------------- coreboot-2.0.0.0-Fallback Sat Feb 16 00:26:20 CST 2008 starting... In auto.c:main() Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0b MA type e0 Bank 0 (*16 Mb) 20 No Physical Banks 01 Total Memory (*16 Mb) 20 CAS Supported 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 tRP 3c tRCD 3c tRAS 28 Low Bond 16 High Bondd3 Setting DQS delay94vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 20 20 20 20 00 00 60:02 ff 00 30 62 32 01 20 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 10 10 80:0f 6c 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Leaving auto.c:main() Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0.0-Fallback Sat Feb 16 00:26:20 CST 2008 booting... clocks_per_usec: 2412 Enumerating buses... Finding PCI configuration type. Disabling static device: PCI: 00:10.3 done Allocating resources... Reading resources... Done reading resources. Setting resources... Done setting resources. Done allocating resources. Enabling resources... done. Initializing devices... Initializing CPU #0 Enabling cache Disabling local apic...done. CPU #0 Initialized pci_routing_fixup: dev is 000103b8 setting firewire setting usb setting vt8235 setting ethernet setting vga setting pci slot setting cardbus slot setting riser slot Enabling VIA IDE. ide_init: enabling compatibility IDE addresses BIOSINT: Unsupport int #0x10 Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... done. ACPI: Writing ACPI tables at f0400... ACPI: done. Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 Can not load ELF Image. ------------------------------------------------------------------------------------------------------------------------------------

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coreboot February 2008