coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

r119 - buildrom-devel/config/platforms
by svn＠coreboot.org 19 Feb '08

19 Feb '08

Author: jcrouse Date: 2008-02-19 16:47:25 +0100 (Tue, 19 Feb 2008) New Revision: 119 Modified: buildrom-devel/config/platforms/db800.conf buildrom-devel/config/platforms/dbe61.conf buildrom-devel/config/platforms/norwich.conf Log: [BUILDROM] Update Coreboot revision for Geode platforms The Geode platforms needed a coreboot revision bump to pull in Myle's renaming of the ROM file to the consistant coreboot.rom. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/config/platforms/db800.conf =================================================================== --- buildrom-devel/config/platforms/db800.conf 2008-02-15 19:16:50 UTC (rev 118) +++ buildrom-devel/config/platforms/db800.conf 2008-02-19 15:47:25 UTC (rev 119) @@ -33,7 +33,7 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf CBV2_TDIR=db800 -CBV2_TAG=3079 +CBV2_TAG=3090 # FILO configuration # Use a new FILO config for the DB800 to autoload an image Modified: buildrom-devel/config/platforms/dbe61.conf =================================================================== --- buildrom-devel/config/platforms/dbe61.conf 2008-02-15 19:16:50 UTC (rev 118) +++ buildrom-devel/config/platforms/dbe61.conf 2008-02-19 15:47:25 UTC (rev 119) @@ -32,7 +32,7 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf CBV2_TDIR=dbe61 -CBV2_TAG=3079 +CBV2_TAG=3090 # FILO configuration Modified: buildrom-devel/config/platforms/norwich.conf =================================================================== --- buildrom-devel/config/platforms/norwich.conf 2008-02-15 19:16:50 UTC (rev 118) +++ buildrom-devel/config/platforms/norwich.conf 2008-02-19 15:47:25 UTC (rev 119) @@ -31,7 +31,7 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf CBV2_TDIR=norwich -CBV2_TAG=3079 +CBV2_TAG=3090 # FILO configuration

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Re: [coreboot] v3 patch rm elfboot
by Myles Watson 19 Feb '08

19 Feb '08

Sorry I've been out of the loop. Here are Stefan's emails and my responses. As I stated in one of my previous emails, I think that this confusion of having two places where we parse ELF is enough reason to get rid of elfboot in v3. On Fri, Feb 15, 2008 at 12:50 PM, Myles Watson <mylesgw(a)gmail.com> wrote: > ron minnich wrote: > > per stefan's comment, let's see how much space we save. This is > > bootblock space, which could be significant, but can we see a number? > > > Elfboot still uses bootblock space if it is disabled in Kconfig? That's > definitely something we need to fix. That space is tight. PAYLOAD_NONE doesn't mean no elfboot. Elfboot is included always so that if someone adds an ELF to the lar later it will still work. My contention is that we should make people preparse the ELF when adding it to the lar, so that v3 doesn't have to understand ELF. That doesn't mean that lar shouldn't. Just the opposite. > > > ... as long as they do not remove functionality that is still used. > > Please don't just remove this code. If you don't like to compile it in, > create a config option to disable it. (There is such a config option > already, so I really don't see the gain) I didn't see one. > > I say: NACK. > > Why? > > Because with this patch it is no longer possible to unpack a lar. v3 doesn't unpack a lar. lar unpacks them. > Please don't do stuff like that with levity. > > Stefan > > ron minnich wrote: > > Stefan, one thing I don't understand, why does removing elfboot make > > it so we can't unpack LAR? > > > > > Because the LAR header information is lost, things like the entry point. > > You unpack it, repack it, and the segments become ordinary files with > their lar headers containing bogus information. > > So either we recreate an ELF file on unpack, or we dump the metadata to > a MANIFEST file. > > Or we forget about lars having the feature to be unpacked. Not sure that > its ever needed, except when you want to migrate a payload from one > image to another one. This is a lar problem, not a v3 problem. > Stefan. > I hope this clears up some of the confusion. I'm looking forward to understanding your concerns better. I thought this would be an easy choice. Thanks, Myles

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r3108 build service
by coreboot information 19 Feb '08

19 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3108 to the coreboot source repository and caused the following changes: Change Log: Should be part of changeset 3106. This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are changed, but also a SPI flash interface which has enable on bit1 and not bit0. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3108&device=serengeti_chee… Configuration of asus:a8v-e_se has been fixed Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3108&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3108&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3108&device=briq&vendor=to… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3107 build service
by coreboot information 19 Feb '08

19 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3107 to the coreboot source repository and caused the following changes: Change Log: Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN device) and sets the chipset voltage from 1.6V to 1.5V. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3107&device=serengeti_chee… Configuration of asus:a8v-e_se is still broken Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3107&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3107&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3107&device=briq&vendor=to… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3106 build service
by coreboot information 19 Feb '08

19 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3106 to the coreboot source repository and caused the following changes: Change Log: This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are changed, but also a SPI flash interface which has enable on bit1 and not bit0. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3106&device=serengeti_chee… Configuration of asus:a8v-e_se is still broken Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3106&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3106&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3106&device=briq&vendor=to… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] v3: make header files self-contained
by Carl-Daniel Hailfinger 19 Feb '08

19 Feb '08

A lot of the v3 header files require other header files to be #included before they can be #included. That is completely counter-intuitive. Add necessary #includes to the header files themselves. Fix a few cases where nonexisting files were #included. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-includecleanup/include/device/smbus.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/smbus.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/smbus.h (working copy) @@ -18,7 +18,6 @@ #ifndef DEVICE_SMBUS_H #define DEVICE_SMBUS_H -#include <stdint.h> #include <device/device.h> #include <device/path.h> #include <device/smbus_def.h> Index: LinuxBIOSv3-includecleanup/include/device/pcix.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/pcix.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/pcix.h (working copy) @@ -18,6 +18,8 @@ #ifndef DEVICE_PCIX_H #define DEVICE_PCIX_H +#include <device/device.h> + /* (c) 2005 Linux Networx GPL see COPYING for details */ unsigned int pcix_scan_bus(struct bus *bus, Index: LinuxBIOSv3-includecleanup/include/device/hypertransport.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/hypertransport.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/hypertransport.h (working copy) @@ -18,6 +18,7 @@ #ifndef DEVICE_HYPERTRANSPORT_H #define DEVICE_HYPERTRANSPORT_H +#include <device/device.h> #include <device/hypertransport_def.h> unsigned int hypertransport_scan_chain(struct bus *bus, Index: LinuxBIOSv3-includecleanup/include/device/agp.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/agp.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/agp.h (working copy) @@ -19,6 +19,8 @@ #ifndef DEVICE_AGP_H #define DEVICE_AGP_H +#include <device/device.h> + unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int agp_scan_bridge(struct device *dev, unsigned int max); Index: LinuxBIOSv3-includecleanup/include/device/pcie.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/pcie.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/pcie.h (working copy) @@ -20,6 +20,8 @@ #ifndef DEVICE_PCIE_H #define DEVICE_PCIE_H +#include <device/device.h> + unsigned int pcie_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int pcie_scan_bridge(struct device *dev, unsigned int max); Index: LinuxBIOSv3-includecleanup/include/device/cardbus.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/cardbus.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/cardbus.h (working copy) @@ -19,6 +19,8 @@ #ifndef DEVICE_CARDBUS_H #define DEVICE_CARDBUS_H +#include <device/device.h> + void cardbus_read_resources(struct device *dev); unsigned int cardbus_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); Index: LinuxBIOSv3-includecleanup/include/device/pci_rom.h =================================================================== --- LinuxBIOSv3-includecleanup/include/device/pci_rom.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/device/pci_rom.h (working copy) @@ -19,6 +19,7 @@ #include <types.h> #include <byteorder.h> +#include <device/device.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (u32) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) Index: LinuxBIOSv3-includecleanup/include/tables.h =================================================================== --- LinuxBIOSv3-includecleanup/include/tables.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/tables.h (working copy) @@ -23,6 +23,8 @@ #ifndef TABLES_H #define TABLES_H +#include <types.h> + /* * Table management structs and prototypes for coreboot. * Index: LinuxBIOSv3-includecleanup/include/post_code.h =================================================================== --- LinuxBIOSv3-includecleanup/include/post_code.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/post_code.h (working copy) @@ -21,6 +21,7 @@ #ifndef POST_CODE_H #define POST_CODE_H +#include <types.h> #include <shared.h> SHARED(post_code, void, u8 value); Index: LinuxBIOSv3-includecleanup/include/spd.h =================================================================== --- LinuxBIOSv3-includecleanup/include/spd.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/spd.h (working copy) @@ -36,6 +36,8 @@ #ifndef _SPD_H_ #define _SPD_H_ +#include <types.h> + /* Byte numbers. */ #define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ #define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ Index: LinuxBIOSv3-includecleanup/include/arch/x86/pci_ops.h =================================================================== --- LinuxBIOSv3-includecleanup/include/arch/x86/pci_ops.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/arch/x86/pci_ops.h (working copy) @@ -17,6 +17,8 @@ #ifndef ARCH_X86_PCI_OPS_H #define ARCH_X86_PCI_OPS_H +#include <device/device.h> + extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_cf8_conf2; Index: LinuxBIOSv3-includecleanup/include/arch/x86/msr.h =================================================================== --- LinuxBIOSv3-includecleanup/include/arch/x86/msr.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/arch/x86/msr.h (working copy) @@ -20,6 +20,8 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H +#include <types.h> + /* standard MSR operations, everyone has written these one hundred times */ struct msr { u32 lo; Index: LinuxBIOSv3-includecleanup/include/arch/x86/pirq_routing.h =================================================================== --- LinuxBIOSv3-includecleanup/include/arch/x86/pirq_routing.h (revision 609) +++ LinuxBIOSv3-includecleanup/include/arch/x86/pirq_routing.h (working copy) @@ -21,6 +21,8 @@ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +#include <types.h> + #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) #define PIRQ_VERSION 0x0100 Index: LinuxBIOSv3-includecleanup/device/smbus_ops.c =================================================================== --- LinuxBIOSv3-includecleanup/device/smbus_ops.c (revision 609) +++ LinuxBIOSv3-includecleanup/device/smbus_ops.c (working copy) @@ -20,7 +20,6 @@ */ #include <console.h> -#include <stdint.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> Index: LinuxBIOSv3-includecleanup/northbridge/intel/i440bxemulation/i440bx.h =================================================================== --- LinuxBIOSv3-includecleanup/northbridge/intel/i440bxemulation/i440bx.h (revision 609) +++ LinuxBIOSv3-includecleanup/northbridge/intel/i440bxemulation/i440bx.h (working copy) @@ -21,6 +21,8 @@ #ifndef NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H #define NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H +#include <device/device.h> + /* * Datasheet: * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller -- http://www.hailfinger.org/

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r611 - in coreboot-v3: device include include/arch/x86 include/device northbridge/intel/i440bxemulation
by svn＠coreboot.org 19 Feb '08

19 Feb '08

Author: hailfinger Date: 2008-02-19 01:34:32 +0100 (Tue, 19 Feb 2008) New Revision: 611 Modified: coreboot-v3/device/smbus_ops.c coreboot-v3/include/arch/x86/msr.h coreboot-v3/include/arch/x86/pci_ops.h coreboot-v3/include/arch/x86/pirq_routing.h coreboot-v3/include/device/agp.h coreboot-v3/include/device/cardbus.h coreboot-v3/include/device/hypertransport.h coreboot-v3/include/device/pci_rom.h coreboot-v3/include/device/pcie.h coreboot-v3/include/device/pcix.h coreboot-v3/include/device/smbus.h coreboot-v3/include/post_code.h coreboot-v3/include/spd.h coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h Log: A lot of the v3 header files require other header files to be #included before they can be #included. That is completely counter-intuitive. Add necessary #includes to the header files themselves. Fix a few cases where nonexisting files were #included. Compile tested on Qemu and Alix1C. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/device/smbus_ops.c =================================================================== --- coreboot-v3/device/smbus_ops.c 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/device/smbus_ops.c 2008-02-19 00:34:32 UTC (rev 611) @@ -20,7 +20,6 @@ */ #include <console.h> -#include <stdint.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> Modified: coreboot-v3/include/arch/x86/msr.h =================================================================== --- coreboot-v3/include/arch/x86/msr.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/arch/x86/msr.h 2008-02-19 00:34:32 UTC (rev 611) @@ -20,6 +20,8 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H +#include <types.h> + /* standard MSR operations, everyone has written these one hundred times */ struct msr { u32 lo; Modified: coreboot-v3/include/arch/x86/pci_ops.h =================================================================== --- coreboot-v3/include/arch/x86/pci_ops.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/arch/x86/pci_ops.h 2008-02-19 00:34:32 UTC (rev 611) @@ -17,6 +17,8 @@ #ifndef ARCH_X86_PCI_OPS_H #define ARCH_X86_PCI_OPS_H +#include <device/device.h> + extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_cf8_conf2; Modified: coreboot-v3/include/arch/x86/pirq_routing.h =================================================================== --- coreboot-v3/include/arch/x86/pirq_routing.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/arch/x86/pirq_routing.h 2008-02-19 00:34:32 UTC (rev 611) @@ -21,6 +21,8 @@ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +#include <types.h> + #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) #define PIRQ_VERSION 0x0100 Modified: coreboot-v3/include/device/agp.h =================================================================== --- coreboot-v3/include/device/agp.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/agp.h 2008-02-19 00:34:32 UTC (rev 611) @@ -19,6 +19,8 @@ #ifndef DEVICE_AGP_H #define DEVICE_AGP_H +#include <device/device.h> + unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int agp_scan_bridge(struct device *dev, unsigned int max); Modified: coreboot-v3/include/device/cardbus.h =================================================================== --- coreboot-v3/include/device/cardbus.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/cardbus.h 2008-02-19 00:34:32 UTC (rev 611) @@ -19,6 +19,8 @@ #ifndef DEVICE_CARDBUS_H #define DEVICE_CARDBUS_H +#include <device/device.h> + void cardbus_read_resources(struct device *dev); unsigned int cardbus_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); Modified: coreboot-v3/include/device/hypertransport.h =================================================================== --- coreboot-v3/include/device/hypertransport.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/hypertransport.h 2008-02-19 00:34:32 UTC (rev 611) @@ -18,6 +18,7 @@ #ifndef DEVICE_HYPERTRANSPORT_H #define DEVICE_HYPERTRANSPORT_H +#include <device/device.h> #include <device/hypertransport_def.h> unsigned int hypertransport_scan_chain(struct bus *bus, Modified: coreboot-v3/include/device/pci_rom.h =================================================================== --- coreboot-v3/include/device/pci_rom.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/pci_rom.h 2008-02-19 00:34:32 UTC (rev 611) @@ -19,6 +19,7 @@ #include <types.h> #include <byteorder.h> +#include <device/device.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (u32) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) Modified: coreboot-v3/include/device/pcie.h =================================================================== --- coreboot-v3/include/device/pcie.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/pcie.h 2008-02-19 00:34:32 UTC (rev 611) @@ -20,6 +20,8 @@ #ifndef DEVICE_PCIE_H #define DEVICE_PCIE_H +#include <device/device.h> + unsigned int pcie_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int pcie_scan_bridge(struct device *dev, unsigned int max); Modified: coreboot-v3/include/device/pcix.h =================================================================== --- coreboot-v3/include/device/pcix.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/pcix.h 2008-02-19 00:34:32 UTC (rev 611) @@ -18,6 +18,8 @@ #ifndef DEVICE_PCIX_H #define DEVICE_PCIX_H +#include <device/device.h> + /* (c) 2005 Linux Networx GPL see COPYING for details */ unsigned int pcix_scan_bus(struct bus *bus, Modified: coreboot-v3/include/device/smbus.h =================================================================== --- coreboot-v3/include/device/smbus.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/device/smbus.h 2008-02-19 00:34:32 UTC (rev 611) @@ -18,7 +18,6 @@ #ifndef DEVICE_SMBUS_H #define DEVICE_SMBUS_H -#include <stdint.h> #include <device/device.h> #include <device/path.h> #include <device/smbus_def.h> Modified: coreboot-v3/include/post_code.h =================================================================== --- coreboot-v3/include/post_code.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/post_code.h 2008-02-19 00:34:32 UTC (rev 611) @@ -21,6 +21,7 @@ #ifndef POST_CODE_H #define POST_CODE_H +#include <types.h> #include <shared.h> SHARED(post_code, void, u8 value); Modified: coreboot-v3/include/spd.h =================================================================== --- coreboot-v3/include/spd.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/include/spd.h 2008-02-19 00:34:32 UTC (rev 611) @@ -36,6 +36,8 @@ #ifndef _SPD_H_ #define _SPD_H_ +#include <types.h> + /* Byte numbers. */ #define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ #define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h =================================================================== --- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h 2008-02-18 20:44:54 UTC (rev 610) +++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h 2008-02-19 00:34:32 UTC (rev 611) @@ -21,6 +21,8 @@ #ifndef NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H #define NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H +#include <device/device.h> + /* * Datasheet: * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller

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Re: [coreboot] r610 - coreboot-v3/mainboard/artecgroup/dbe61
by Peter Stuge 19 Feb '08

19 Feb '08

On Mon, Feb 18, 2008 at 09:44:54PM +0100, svn(a)coreboot.org wrote: > Completely replace DBE61 initram code by Alix.1C initram code. > +/* The part is a Hynix hy5du121622ctp-d43. Still true? //Peter

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r3105 build service
by coreboot information 18 Feb '08

18 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3105 to the coreboot source repository and caused the following changes: Change Log: Use virtual LDNs. It enables the GPIOs correctly (it preserves the GPIO5/2 from a sio_setup. As side effect I can now have GAME and MIDI portsenabled. It has been tested with my board. It produces same results. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3105&device=serengeti_chee… Configuration of asus:a8v-e_se has been broken Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3105&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3105&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3105&device=briq&vendor=to… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3104 build service
by coreboot information 18 Feb '08

18 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3104 to the coreboot source repository and caused the following changes: Change Log: Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, like mine W83627EHF. This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but maps to original LDN and bit position in register 0x30. VirtualLDN = origLDN[7:0] | bitpos[10:8] Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3104&device=serengeti_chee… Compilation of embeddedplanet:ep405pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3104&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3104&device=sandpointx3_al… Compilation of totalimpact:briq has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3104&device=briq&vendor=to… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot February 2008