coreboot February 2008

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[patch] add MSI MS-7135 support, try three
by jakllsch＠kollasch.net 20 Feb '08

20 Feb '08

Initial support for MSI MS-7135 (K8N Neo3) mainboard. Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>

3 3

r3111 - in trunk/coreboot-v2: src/mainboard/msi src/mainboard/msi/ms7135 targets/msi targets/msi/ms7135
by svn＠coreboot.org 20 Feb '08

20 Feb '08

Author: stepan Date: 2008-02-20 16:59:30 +0100 (Wed, 20 Feb 2008) New Revision: 3111 Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms7135/chip.h trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c trunk/coreboot-v2/src/mainboard/msi/ms7135/irq_tables.c trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c trunk/coreboot-v2/src/mainboard/msi/ms7135/mptable.c trunk/coreboot-v2/targets/msi/ms7135/ trunk/coreboot-v2/targets/msi/ms7135/Config.lb Log: Initial support for MSI MS-7135 (K8N Neo3) mainboard. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,306 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) +## Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> +## (Thanks to LSRA University of Mannheim for their support) +## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) +else + if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) + else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) + default ROM_SECTION_OFFSET = 0 + end +end + +## +## Compute the start location and size size of the coreboot bootloader. +## +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot ROM. +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can be cached to speed up coreboot +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE = (64 * 1024) + +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/ati/ragexl + +# Needed by irq_tables and mptable and acpi_tables. +object get_bus_conf.o + +if HAVE_MP_TABLE + object mptable.o +end + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if USE_DCACHE_RAM + if CONFIG_USE_INIT + makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + else + makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end + end +end + +## +## Build our 16 bit and 32 bit coreboot entry code. +## +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +end + +mainboardinit cpu/x86/32bit/entry32.inc + +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (this is where coreboot is entered). +## +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +end + +if USE_DCACHE_RAM +else + ### Should this be in the northbridge code? + mainboardinit arch/i386/lib/cpu_reset.inc +end + +## +## Include an ID string (for safe flashing). +## +mainboardinit southbridge/nvidia/ck804/id.inc +ldscript /southbridge/nvidia/ck804/id.lds + +## +## ROMSTRAP table for CK804 +## +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end +end + +if USE_DCACHE_RAM + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc +end + + +### +### This is the early phase of coreboot startup. +### Things are delicate and we test to see if we should +### failover to another image. +### +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover_failover.lds + end + end +else + if USE_FALLBACK_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds + end + end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + if CONFIG_USE_INIT + initobject auto.o + else + mainboardinit ./auto.inc + end +end + +## +## Include the secondary configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + +chip northbridge/amd/amdk8/root_complex # Root complex + device apic_cluster 0 on # APIC cluster + chip cpu/amd/socket_754 # Socket 754 CPU + device apic 0 on end # APIC + end + end + + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 0 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # non-existant or undocumented + device pnp 2e.7 off end # Game, MIDI, GPIO 1, GPIO 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 off end # GPIO 3, GPIO 4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # env monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1.1 on end # SMbus + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI) -- not wired out + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 -- not wired out + device pci c.0 off end # PCI E 2 -- not wired out + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # register "mac_eeprom_smbus" = "3" + # register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,321 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> +## (Thanks to LSRA University of Mannheim for their support) +## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses USE_FAILOVER_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_FAILOVER_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses FAILOVER_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses COREBOOT_EXTRA_VERSION +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_CONSOLE_BTEXT +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses HW_MEM_HOLE_SIZEK + +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses CONFIG_USE_INIT +uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_AP_CODE_IN_CAR +uses MEM_TRAIN_SEQ +uses WAIT_BEFORE_CPUS_INIT + +uses ENABLE_APIC_EXT_ID +uses APIC_ID_OFFSET +uses LIFT_BSP_APIC_ID + +uses CONFIG_PCI_64BIT_PREF_MEM + +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_LB_MEM_TOPK + + +## ROM_SIZE is the size of boot ROM that this board will use. +## ---> 512 Kbytes +default ROM_SIZE=(512*1024) + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +default FALLBACK_SIZE=(252*1024) + +#FAILOVER: 4K +default FAILOVER_SIZE=(4*1024) + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 +default HAVE_FAILOVER_BOOT=1 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=13 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default coreboot cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_PHYSICAL_CPUS=1 +default CONFIG_LOGICAL_CPUS=1 + +#1G memory hole +default HW_MEM_HOLE_SIZEK=0x100000 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x10 + +#make the SB HT chain on bus 0, default is not (0) +default SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + +#BTEXT Console +#default CONFIG_CONSOLE_BTEXT=1 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +#default DCACHE_RAM_BASE=0xcf000 +#default DCACHE_RAM_SIZE=0x1000 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 +default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_INIT=0 + +default CONFIG_AP_CODE_IN_CAR=0 +default MEM_TRAIN_SEQ=2 +default WAIT_BEFORE_CPUS_INIT=0 + +## APIC stuff +#default ENABLE_APIC_EXT_ID=0 +#default APIC_ID_OFFSET=0x10 +#default LIFT_BSP_APIC_ID=0 + + +#default CONFIG_PCI_64BIT_PREF_MEM=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" +default MAINBOARD_VENDOR="MSI" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = (64*1024) +#65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) + +## +## coreboot C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +### End Options.lb +end Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +/* Used by raminit. */ +#define QRANK_DIMM_SUPPORT 1 + +/* Turn this on for SMBus debugging output. */ +#define DEBUG_SMBUS 0 + +#if CONFIG_LOGICAL_CPUS == 1 +#define SET_NB_CFG_54 1 +#endif + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +#if USE_FAILOVER_IMAGE == 0 + +/* Used by ck804_early_setup(). */ +#define CK804_NUM 1 +#define CK804_USE_NIC 1 +#define CK804_USE_ACI 1 + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include <cpu/amd/model_fxx_rev.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "northbridge/amd/amdk8/debug.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "cpu/amd/dualcore/dualcore.c" + +static void memreset_setup(void) +{ + /* FIXME: Nothing to do? */ +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + /* FIXME: Nothing to do? */ +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* FIXME: Nothing to do? */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/raminit.c" +#include "sdram/generic_sdram.c" +#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" +#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" + +#endif /* USE_FAILOVER_IMAGE */ + +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ + || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) + +#include "southbridge/nvidia/ck804/ck804_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +static void sio_setup(void) +{ + unsigned value; + uint32_t dword; + uint8_t byte; + + /* Subject decoding */ + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1 << 0) | (1 << 1); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); +} + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + + /* Is this a deliberate reset by the BIOS? */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + + /* This is the primary CPU. How should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } else { + goto fallback_image; + } + +normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ + ); + +fallback_image: + +#if HAVE_FAILOVER_BOOT == 1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ + ) +#endif + ; +} + +#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ +#if HAVE_FAILOVER_BOOT == 1 +#if USE_FAILOVER_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#else + real_main(bist, cpu_init_detectedx); +#endif +#else +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); +#endif +} + +#if USE_FAILOVER_IMAGE == 0 +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + (0xa << 3) | 0, (0xa << 3) | 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }; + + int needs_reset; + unsigned bsp_apicid = 0; + + struct mem_controller ctrl[8]; + unsigned nodes; + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx); + } + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); +#endif + + needs_reset = setup_coherent_ht_domain(); + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + needs_reset |= ht_setup_chains_x(); + + needs_reset |= ck804_early_setup_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + + enable_smbus(); + +#if 0 + dump_spd_registers(&ctrl[0]); + dump_smbus_registers(); +#endif + + memreset_setup(); + sdram_initialize(nodes, ctrl); + +#if 0 + print_pci_devices(); + dump_pci_devices(); +#endif + + post_cache_as_ram(); +} +#endif /* USE_FAILOVER_IMAGE */ Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/chip.h 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_msi_ms7135_ops; + +struct mainboard_ms7135_config { + int nothing; +}; Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS == 1 +#include <cpu/amd/dualcore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> + +/* Global variables for MB layouts and these will be shared by irqtable, + * mptable and acpi_tables. + */ +/* busnum is default */ +unsigned char bus_isa; +unsigned char bus_ck804[6]; +unsigned apicid_ck804; + +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, //no HTIO for ms7135 +}; +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, //ms7135 has only one ht-chain +}; +unsigned bus_type[256]; + +extern void get_sblk_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + unsigned apicid_base; + + device_t dev; + unsigned sbdn; + int i, j; + + if (get_bus_conf_done == 1) + return; //do it only once + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + for (i = 0; i < 6; i++) { + bus_ck804[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; + } + + bus_type[0] = 1; //pci + + bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff; + + bus_type[bus_ck804[0]] = 1; + + /* CK804 */ + int dn = -1; + for (i = 1; i < 4; i++) { + switch (i) { + case 1: dn = 9; break; + case 2: dn = 13; break; + case 3: dn = 14; break; + default: dn = -1; break; + } + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + dn, 0)); + if (dev) { + bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_ck804[i]; j < bus_isa; j++) + bus_type[j] = 1; + } else { + printk_debug + ("ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804[0], sbdn + dn); + bus_isa = bus_ck804[i - 1] + 1; + } + } + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_ck804 = apicid_base + 0; +} Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/irq_tables.c 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Documentation at: http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ + +/* This is probably not right, feel free to fix this if you don't want + * to use the mptable. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern unsigned char bus_isa; +extern unsigned char bus_ck804[6]; +extern void get_bus_conf(void); + +/** + * Add one line to IRQ table. + */ +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, + uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +void pci_assign_irqs(unsigned, unsigned, const unsigned char *); + +/** + * Create the IRQ routing table. + * Values are derived from getpir generated code. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + + uint8_t sum = 0; + int i; + unsigned sbdn; + + /* get_bus_conf() will find out all bus num and apic that share with + * mptable.c and mptable.c + */ + get_bus_conf(); + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (uint8_t *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_ck804[0]; + pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; + + pirq->exclusive_irqs = 0x828; + + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + +//Slot1 PCIE 16x + write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, + 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); + pirq_info++; + slot_num++; + +//Slot2 PCIE 1x + write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); + pirq_info++; + slot_num++; + +//Slot3 PCIE 1x + write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); + pirq_info++; + slot_num++; + +//Slot4 PCIE 4x + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, + 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, + 7, 0); + pirq_info++; + slot_num++; + +//Slot5 - 7 PCI + for (i = 0; i < 3; i++) { + write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, + ((i + 0) % 4) + 1, 0xdeb8, + ((i + 1) % 4) + 1, 0xdeb8, + ((i + 2) % 4) + 1, 0xdeb8, + ((i + 3) % 4) + 1, 0xdeb8, i, 0); + pirq_info++; + slot_num++; + } + +//pci bridge + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); + pirq_info++; + slot_num++; + +//smbus + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + +//usb + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + +//audio + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; +//sata + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; +//sata + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; +//nic + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + +#if 0 + unsigned char irq[4]; + irq[0] = 0; + irq[1] = 0; + irq[2] = 0; + irq[3] = 0; + + /* Bus, device, slots IRQs for {A,B,C,D}. */ + + irq[0] = 10; /* SMBus */ /* test me */ + pci_assign_irqs(bus_ck804[0], 1, irq); + + irq[0] = 10; /* USB */ + irq[1] = 10; + pci_assign_irqs(bus_ck804[0], 2, irq); + + irq[0] = 10; /* AC97 */ + irq[1] = 0; + pci_assign_irqs(bus_ck804[0], 4, irq); + + irq[0] = 11; /* SATA */ + pci_assign_irqs(bus_ck804[0], 7, irq); + + irq[0] = 5; /* SATA */ + pci_assign_irqs(bus_ck804[0], 8, irq); + + irq[0] = 10; /* Ethernet */ + pci_assign_irqs(bus_ck804[0], 10, irq); + + + /* physical slots */ + + irq[0] = 5; /* PCI E1 - x1 */ + pci_assign_irqs(bus_ck804[2], 0, irq); + + irq[0] = 11; /* PCI E2 - x16 */ + pci_assign_irqs(bus_ck804[3], 0, irq); + + /* AGP-on-PCI "AGR" ignored */ + + irq[0] = 10; /* PCI1 */ + irq[1] = 11; + irq[2] = 5; + irq[3] = 0; + pci_assign_irqs(bus_ck804[1], 7, irq); + + irq[0] = 11; /* PCI2 */ + irq[1] = 10; + irq[2] = 5; + irq[3] = 0; + pci_assign_irqs(bus_ck804[1], 8, irq); + + irq[0] = 5; /* PCI3 */ + irq[1] = 10; + irq[2] = 11; + irq[3] = 0; + pci_assign_irqs(bus_ck804[1], 9, irq); +#endif + + return (unsigned long)pirq_info; +} Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +#if CONFIG_CHIP_NAME == 1 +struct chip_operations mainboard_msi_ms7135_ops = { + CHIP_NAME("MSI MS7135 Mainboard") +}; +#endif Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/mptable.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/mptable.c 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,221 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern unsigned char bus_isa; +extern unsigned char bus_ck804[6]; +extern unsigned apicid_ck804; + +extern unsigned bus_type[256]; + +extern void get_bus_conf(void); + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "MSI "; + static const char productid[12] = "MS7135 "; + struct mp_config_table *mc; + unsigned sbdn; + + int bus_num; + int i; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + +/* Bus: Bus ID Type*/ + /* define numbers for pci and isa bus */ + for (bus_num = 0; bus_num < 256; bus_num++) { + if (bus_type[bus_num]) + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + +/* I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword; + + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, + res->base); + } + + /* Initialize interrupt mapping */ + + /* copied from stock bios */ + /*0x01800500,0x1800d509,0x00520d08*/ + + /* if this register is what i think it is ... */ + dword = 0x08d0d218; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x8d001509; + pci_write_config32(dev, 0x80, dword); + + dword = 0x00010271; + pci_write_config32(dev, 0x84, dword); + + } + } + + /* Now, assemble the table. */ + + smp_write_intsrc(mc, mp_ExtINT, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0, apicid_ck804, 0x0); + +#define ISA_INT(intr, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, \ + bus_isa, (intr), apicid_ck804, (pin)) + + ISA_INT(1, 1); + ISA_INT(0, 2); + ISA_INT(3, 3); + ISA_INT(4, 4); + + ISA_INT(6, 6); + ISA_INT(7, 7); + ISA_INT(8, 8); + ISA_INT(9, 9); + + ISA_INT(0xc, 0xc); + ISA_INT(0xd, 0xd); + ISA_INT(0xe, 0xe); + ISA_INT(0xf, 0xf); + +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ + bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin)) + +#if 0 + // Onboard ck804 smbus + PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */ + +#endif + // Onboard ck804 USB + PCI_INT(0, sbdn+2, 0, 23); + PCI_INT(0, sbdn+2, 1, 23); + + // Onboard ck804 AC-97 + PCI_INT(0, sbdn+4, 0, 23); + + // Onboard ck804 SATA 0 + PCI_INT(0, sbdn+7, 0, 20); + + // Onboard ck804 SATA 1 + PCI_INT(0, sbdn+8, 0, 21); + + // Onboard ck804 NIC + PCI_INT(0, sbdn+10, 0, 22); + + + /* legacy PCI */ + PCI_INT(1, 7, 0, 17); + PCI_INT(1, 7, 1, 18); + PCI_INT(1, 7, 2, 19); + PCI_INT(1, 7, 3, 16); + + PCI_INT(1, 8, 0, 18); + PCI_INT(1, 8, 1, 19); + PCI_INT(1, 8, 2, 16); + PCI_INT(1, 8, 3, 17); + + PCI_INT(1, 9, 0, 19); + PCI_INT(1, 9, 1, 16); + PCI_INT(1, 9, 2, 17); + PCI_INT(1, 9, 3, 18); + + + /* PCI-E x1 port */ + PCI_INT(2, 0, 0, 19); + /* XXX guesses */ + PCI_INT(2, 0, 1, 16); + PCI_INT(2, 9, 2, 17); + PCI_INT(2, 9, 3, 18); + + /* PCI-E x16 port */ /* XXX fix me ? */ + PCI_INT(3, 0, 0, 18); + /* XXX guesses */ + PCI_INT(3, 0, 1, 19); + PCI_INT(3, 0, 2, 16); + PCI_INT(3, 0, 3, 17); + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_lintsrc(mc, mp_ExtINT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, + bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, + bus_ck804[0], 0x0, MP_APIC_ALL, 0x1); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = + smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/coreboot-v2/targets/msi/ms7135/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7135/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/msi/ms7135/Config.lb 2008-02-20 15:59:30 UTC (rev 3111) @@ -0,0 +1,61 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> +## (Thanks to LSRA University of Mannheim for their support) +## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target ms7135 +mainboard msi/ms7135 + +option DEFAULT_CONSOLE_LOGLEVEL=8 +option MAXIMUM_CONSOLE_LOGLEVEL=8 + +option HAVE_PIRQ_TABLE=1 +option CONFIG_CONSOLE_VGA=1 +option CONFIG_PCI_ROM_RUN=1 + + +romimage "normal" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION="_Normal" + payload /tmp/payload.elf +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION="_Fallback" + payload /tmp/payload.elf +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="_Failover" +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

1 0

AMD VSA binary corrupt?
by Stefan Reinauer 20 Feb '08

20 Feb '08

Hi, I'm trying to download the latest AMD Geode LX VSA from http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.… but it seems, the file is corrupted: $ gunzip amd_vsa_lx_1.01.bin.gz gzip: amd_vsa_lx_1.01.bin.gz: not in gzip format $ Any hint what to do? Best regards, Stefan. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

4 3

[PATCH] v3: fix up missing conversion from r558
by Carl-Daniel Hailfinger 20 Feb '08

20 Feb '08

r558 had this: > Author: rminnich > util/x86emu/vm86.c > Change uses of dev_find_device to dev_find_pci_device Unfortunately, x86emu/pcbios/pcibios.c was missed in the conversion. Fix it to get builds with x86emu compiling again. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-dbe61/util/x86emu/pcbios/pcibios.c =================================================================== --- LinuxBIOSv3-dbe61/util/x86emu/pcbios/pcibios.c (revision 610) +++ LinuxBIOSv3-dbe61/util/x86emu/pcbios/pcibios.c (working copy) @@ -61,7 +61,7 @@ break; case FIND_PCI_DEVICE: /* FixME: support SI != 0 */ - dev = dev_find_device(X86_DX, X86_CX, dev); + dev = dev_find_pci_device(X86_DX, X86_CX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; X86_BL = dev->path.u.pci.devfn; -- http://www.hailfinger.org/

2 2

r612 - coreboot-v3/util/x86emu/pcbios
by svn＠coreboot.org 20 Feb '08

20 Feb '08

Author: hailfinger Date: 2008-02-20 14:33:36 +0100 (Wed, 20 Feb 2008) New Revision: 612 Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c Log: The commit in r558 had this: > > Author: rminnich > > util/x86emu/vm86.c > > Change uses of dev_find_device to dev_find_pci_device Unfortunately, x86emu/pcbios/pcibios.c was missed in the conversion. Fix it to get builds with x86emu compiling again. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c =================================================================== --- coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-02-19 00:34:32 UTC (rev 611) +++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-02-20 13:33:36 UTC (rev 612) @@ -61,7 +61,7 @@ break; case FIND_PCI_DEVICE: /* FixME: support SI != 0 */ - dev = dev_find_device(X86_DX, X86_CX, dev); + dev = dev_find_pci_device(X86_DX, X86_CX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; X86_BL = dev->path.u.pci.devfn;

1 0

r3110 build service
by coreboot information 20 Feb '08

20 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3110 to the coreboot source repository and caused the following changes: Change Log: flashrom: Add board_enable for Artec Group DBE61 and DBE62 Also add a comment about NULL subsystem IDs leaving the board entry out of auto-detection logic. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3110&device=serengeti_chee… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3110 - trunk/util/flashrom
by svn＠coreboot.org 20 Feb '08

20 Feb '08

Author: stepan Date: 2008-02-20 12:11:18 +0100 (Wed, 20 Feb 2008) New Revision: 3110 Modified: trunk/util/flashrom/board_enable.c Log: flashrom: Add board_enable for Artec Group DBE61 and DBE62 Also add a comment about NULL subsystem IDs leaving the board entry out of auto-detection logic. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-02-19 20:30:25 UTC (rev 3109) +++ trunk/util/flashrom/board_enable.c 2008-02-20 11:11:18 UTC (rev 3110) @@ -28,6 +28,7 @@ #include <pci/pci.h> #include <stdint.h> #include <string.h> +#include <fcntl.h> #include "flash.h" /* @@ -368,12 +369,77 @@ } /** + * Suited for Artec Group DBE61 and DBE62. + */ +static int board_artecgroup_dbe6x(const char *name) +{ +#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015 +#define DBE6x_PRI_BOOT_LOC_SHIFT (2) +#define DBE6x_BOOT_OP_LATCHED_SHIFT (8) +#define DBE6x_SEC_BOOT_LOC_SHIFT (10) +#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT) +#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT) +#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT) +#define DBE6x_BOOT_LOC_FLASH (2) +#define DBE6x_BOOT_LOC_FWHUB (3) + + unsigned long msr[2]; + int msr_fd; + unsigned long boot_loc; + + msr_fd = open("/dev/cpu/0/msr", O_RDWR); + if (msr_fd == -1) { + perror("open /dev/cpu/0/msr"); + return -1; + } + + if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) { + perror("lseek"); + close(msr_fd); + return -1; + } + + if (read(msr_fd, (void*) msr, 8) != 8) { + perror("read"); + close(msr_fd); + return -1; + } + + if ((msr[0] & (DBE6x_BOOT_OP_LATCHED)) == + (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT)) + boot_loc = DBE6x_BOOT_LOC_FWHUB; + else + boot_loc = DBE6x_BOOT_LOC_FLASH; + + msr[0] &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC); + msr[0] |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) | + (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT)); + + if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) { + perror("lseek"); + close(msr_fd); + return -1; + } + + if (write(msr_fd, (void*) msr, 8) != 8) { + perror("write"); + close(msr_fd); + return -1; + } + + close(msr_fd); + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles * subsystem/card IDs in a sane manner. * * Keep the second set NULLed if it should be ignored. + * + * Keep the subsystem IDs NULLed if they don't identify the board fully. */ struct board_pciid_enable { /* Any device, but make it sensible, like the ISA bridge. */ @@ -427,6 +493,10 @@ "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3}, {0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd}, + {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000, + "artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x}, + {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000, + "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

1 0

DCACHE_RAM
by Mikhail Savchenko 20 Feb '08

20 Feb '08

How can I get right DCACHE_RAM_BASE and DCACHE_RAM_SIZE parameters for my platform?

1 0

Coreboot on the Asus P4PE
by Nick Stallman 20 Feb '08

20 Feb '08

Hi I just checked around a bit and saw that at least part of my motherboard is supported by Coreboot but its not on any of the lists. Its a Asus P4PE. A old Pentium 4 motherboard with a Intel 82845PE MCH northbridge and a Intel 82801DA ICH 4 southbridge. Attached is the output of various commands. How much work is required to get Coreboot going on it and whats the likely hood of borking it? I've got two of these motherboards so killing one is ok but I do prefer them working. :) Thanks Nick

2 1

r122 - buildrom-devel/packages/vsa
by svn＠coreboot.org 19 Feb '08

19 Feb '08

Author: jcrouse Date: 2008-02-19 22:52:36 +0100 (Tue, 19 Feb 2008) New Revision: 122 Removed: buildrom-devel/packages/vsa/olpc_vsa.64k.bin Log: Hmm - somehow we had this big 64k blob sitting around and nobody noticed. :) Trivial deletion of unused code. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com>

1 0

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coreboot February 2008