coreboot October 2008

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608 discussions

Tinycurses depends on active video console.
by Mats Erik Andersson 01 Oct '08

01 Oct '08

Hello all, may I point out that the flags "-Wall -Werror" prevents tinycurses to compile in case only a serial console has been configured, but no video output. The culprit is an unused but defined variable "c". The naive solution is to condition the creation of "c" by the flag CONFIG_VIDEO_CONSOLE. Signed-off-by: Mats Erik Andersson <mats.andersson(a)gisladisker.se> Index: libpayload/curses/tinycurses.c =================================================================== --- libpayload/curses/tinycurses.c (revision 3623) +++ libpayload/curses/tinycurses.c (arbetskopia) @@ -736,8 +736,10 @@ for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) { attr_t attr = win->_line[y].text[x].attr; +#ifdef CONFIG_VIDEO_CONSOLE unsigned int c = ((int)color_pairs[PAIR_NUMBER(attr)]) << 8; +#endif #ifdef CONFIG_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) {

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r3626 - trunk/util/superiotool
by svn＠coreboot.org 01 Oct '08

01 Oct '08

Author: uwe Date: 2008-10-01 22:16:58 +0200 (Wed, 01 Oct 2008) New Revision: 3626 Modified: trunk/util/superiotool/fintek.c trunk/util/superiotool/ite.c trunk/util/superiotool/smsc.c Log: Add some more Super I/O IDs/names (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/fintek.c =================================================================== --- trunk/util/superiotool/fintek.c 2008-10-01 13:10:39 UTC (rev 3625) +++ trunk/util/superiotool/fintek.c 2008-10-01 20:16:58 UTC (rev 3626) @@ -67,6 +67,8 @@ {0x30,0xf0,0xf1,EOT}, {0x00,0x00,0x00,EOT}}, {EOT}}}, + {0x0581, "F8000", { /* Fintek/ASUS F8000 */ + {EOT}}}, {EOT} }; Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-10-01 13:10:39 UTC (rev 3625) +++ trunk/util/superiotool/ite.c 2008-10-01 20:16:58 UTC (rev 3626) @@ -318,6 +318,8 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8720, "IT8720F", { /* From sensors-detect */ + {EOT}}}, {0x8726, "IT8726F", { /* Datasheet wrongly says that the ID is 0x8716. */ {EOT}}}, Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2008-10-01 13:10:39 UTC (rev 3625) +++ trunk/util/superiotool/smsc.c 2008-10-01 20:16:58 UTC (rev 3626) @@ -426,6 +426,8 @@ {EOT}}}, {0x62, "LPC47S45x", { {EOT}}}, + {0x67, "EMC2700LPC", { /* From sensors-detect */ + {EOT}}}, {0x6b, "LPC47M292", { /* From sensors-detect */ {EOT}}}, {0x6e, "LPC47B387", { /* TODO: Not yet in sensors-detect */ @@ -507,10 +509,18 @@ {EOT}}}, {0x81, "SCH5307", { {EOT}}}, + {0x83, "SCH5514D", { /* From sensors-detect */ + {EOT}}}, {0x85, "SCH5317", { /* From sensors-detect */ + /* The SCH5317 can have either 0x85 or 0x8c as device ID. */ {EOT}}}, + {0x86, "SCH5127", { /* From sensors-detect */ + {EOT}}}, {0x89, "SCH5027", { /* From sensors-detect (no public datasheet) */ {EOT}}}, + {0x8c, "SCH5317", { /* From sensors-detect */ + /* The SCH5317 can have either 0x85 or 0x8c as device ID. */ + {EOT}}}, {0x90, "SCH4307", { /* From sensors-detect */ {EOT}}},

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Re: [coreboot] coreboot gpxe
by Mats Erik Andersson 01 Oct '08

01 Oct '08

Chris Kilgour <techie(a)whiterocker.com> wrote > >> http://www.whiterocker.com/gpxe/ > >> > >> > > FYI - libpayload-lplconsole.patch was put together against libpayload r > 3345. I'm pretty sure the patch doesn't apply cleanly to the latest > libpayload. > > Chris. > I can provide an almost complete aliment in that direction. The patch provided below is constructed against todays trunk, and it solves everything except the build step build/lib/lplconsole.o(.text+0x9c3): I funktionen "cb_parse_header": : undefined reference to `strncmp' arising at the very last "ls -N -T ....." command. I had no really good idea as to the best inclusion path to "strncmp()", and therefore I had to leave the patchwork at that point. Most of you are more clever than me in this respect. Please forgive me for intruding, Mats Erik Andersson ---- Index: libpayload/curses/tinycurses.c =================================================================== --- libpayload/curses/tinycurses.c (revision 3623) +++ libpayload/curses/tinycurses.c (arbetskopia) @@ -736,8 +736,10 @@ for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) { attr_t attr = win->_line[y].text[x].attr; +#ifdef CONFIG_VIDEO_CONSOLE unsigned int c = ((int)color_pairs[PAIR_NUMBER(attr)]) << 8; +#endif #ifdef CONFIG_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) { Index: libpayload/Makefile =================================================================== --- libpayload/Makefile (revision 3623) +++ libpayload/Makefile (arbetskopia) @@ -95,12 +95,45 @@ STACKPROTECT += $(call cc-option, -fno-stack-protector,) # TODO: Re-add -Os as soon as we find out why it caused problems. -CFLAGS := -Wall -Werror $(STACKPROTECT) -nostdinc $(INCLUDES) -ffreestanding +CFLAGS := -Wall -Werror $(STACKPROTECT) -ggdb -nostdinc $(INCLUDES) -ffreestanding all: lib -lib: prepare $(obj)/lib/libpayload.a copystuff +lib: prepare $(obj)/lib/libpayload.a copystuff $(obj)/lib/lplconsole.o +LPL_CONSOLE_OBJS = $(obj)/libc/console.o $(obj)/drivers/pci.o \ + $(obj)/i386/timer.o $(obj)/i386/sysinfo.o $(obj)/i386/coreboot.o \ + $(obj)/libc/ipchecksum.o $(obj)/i386/virtual.o + +ifeq ($(CONFIG_SERIAL_CONSOLE),y) +LPL_CONSOLE_OBJS += $(obj)/drivers/serial.o +endif + +ifeq ($(CONFIG_PC_KEYBOARD),y) +LPL_CONSOLE_OBJS += $(obj)/drivers/keyboard.o +endif + +ifeq ($(CONFIG_VIDEO_CONSOLE),y) +LPL_CONSOLE_OBJS += $(obj)/drivers/video/font8x16.o \ + $(obj)/drivers/video/video.o +endif + +ifeq ($(CONFIG_VGA_VIDEO_CONSOLE),y) +LPL_CONSOLE_OBJS += $(obj)/drivers/video/vga.o +endif + +ifeq ($(CONFIG_GEODE_VIDEO_CONSOLE),y) +LPL_CONSOLE_OBJS += $(obj)/drivers/video/geode.o +endif + +$(obj)/lib/lplconsole.o: $(LPL_CONSOLE_OBJS) + $(LD) -r -o $@.tmp $(LPL_CONSOLE_OBJS) + objcopy --redefine-sym putchar=lpl_putchar --redefine-sym getchar=lpl_getchar \ + --redefine-sym havekey=lpl_havekey --redefine-sym console_init=lpl_console_init \ + --redefine-sym udelay=lpl_udelay --redefine-sym mdelay=lpl_mdelay \ + --redefine-sym ndelay=lpl_ndelay \ + $@.tmp $@ + # Copy libpayload.a and head.o into $(src)/lib where lpgcc et al expect them. copystuff: $(obj)/$(ARCHDIR-y)/head.S.o $(obj)/lib/libpayload.a $(Q)cp $(obj)/$(ARCHDIR-y)/head.S.o $(src)/lib/$(ARCHDIR-y)/head.o

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qemu emulation quirks: legacy memory attributes
by Andriy Gapon 01 Oct '08

01 Oct '08

Guys, I have an impression that qemu is used quite extensively for coreboot code testing. But I've encountered some problems with its emulation of essential hardware that I didn't have with bochs. This is with non-coreboot code. What do you think about the following: http://thread.gmane.org/gmane.comp.emulators.qemu/30106 ["register 20h" there should be changed to "register 59h"] P.S. bochs is really good, BTW, but qemu's speed is fascinating. -- Andriy Gapon

2 1

r879 - in coreboot-v3: . arch/x86 device lib mainboard mainboard/amd mainboard/amp mainboard/gigabyte mainboard/pcengines
by svn＠coreboot.org 01 Oct '08

01 Oct '08

Author: uwe Date: 2008-10-01 20:29:22 +0200 (Wed, 01 Oct 2008) New Revision: 879 Modified: coreboot-v3/Kconfig coreboot-v3/arch/x86/Kconfig coreboot-v3/device/Kconfig coreboot-v3/lib/Kconfig coreboot-v3/lib/console.c coreboot-v3/mainboard/Kconfig coreboot-v3/mainboard/amd/Kconfig coreboot-v3/mainboard/amp/Kconfig coreboot-v3/mainboard/gigabyte/Kconfig coreboot-v3/mainboard/pcengines/Kconfig Log: Minor fixes and improvements for v3, mostly for Kconfig files (trivial). - Coding style and whitespace fixes. - Remove obsolete comments, fix incorrect ones. - Use the full/canonical name of mainboards/vendors everywhere. - Update the list of USB Debug capable chipsets from http://www.coreboot.org/EHCI_Debug_Port. - s/LB/CB/ for the CONSOLE_PREFIX kconfig option. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -64,7 +64,7 @@ bool "Enable whole-program optimizations (DANGEROUS)" depends EXPERT && EXPERIMENTAL help - Enable gcc -fwhole-program -combine for select code. + Enable 'gcc -fwhole-program -combine' for select code. Needs lots of annotation in stage1 and stage2. Works for initram only. This increases compile time (no parallel compilation possible @@ -111,8 +111,6 @@ config SUPERIO_ITE_IT8716F boolean -# Source all northbridge/southbridge/superio Kconfig files: - menu "Payload" config PAYLOAD_ELF_LOADER @@ -122,8 +120,8 @@ This option allows an unparsed ELF paylaod to be added and loaded. choice - prompt "Payload type" - default PAYLOAD_NONE + prompt "Payload type" + default PAYLOAD_NONE config PAYLOAD_ELF bool "An ELF executable payload file" Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/arch/x86/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -60,62 +60,62 @@ boolean depends CPU_AMD_K8 help - Whether to configure a High Precision Event Timer. Note that HPETs are - known to be bug-prone. + Whether to configure a High Precision Event Timer (HPET). Note that + HPETs are known to be bug-prone. config K8_REV_F_SUPPORT hex default 0 if CPU_AMD_K8 help - Whether to include rev F support + Whether to include rev F support. config K8_SCAN_PCI_BUS hex default 0 if CPU_AMD_K8 help - Whether to scan the PCI bus in stage1 + Whether to scan the PCI bus in stage1. config K8_ALLOCATE_IO_RANGE hex default 0 if CPU_AMD_K8 help - Whether to allocate IO space in stage1 - + Whether to allocate I/O space in stage1. + config K8_ALLOCATE_MMIO_RANGE hex default 0 if CPU_AMD_K8 help - Whether to allocate MMIO space in stage1. - Comment from code: - Do we need allocate MMIO? Currently we direct - last 64M to southbridge link (sblink) only, - We can not lose access to last 4M range to ROM. - + Whether to allocate MMIO space in stage1. + + Comment from code: Do we need allocate MMIO? Currently we direct + last 64M to southbridge link (sblink) only. We can not lose access + to last 4M range to ROM. + config LOGICAL_CPUS hex depends CPU_AMD_K8 default 1 help - How many logical CPUs there are. Fix me. + How many logical CPUs there are. FIXME. config MAX_PHYSICAL_CPUS hex depends CPU_AMD_K8 default 1 help - Max number of physical CPUs (sockets) + Maximum number of physical CPUs (sockets). config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED hex default 0 if CPU_AMD_K8 help - Config with 4 CPUs even if more are installed + Config with 4 CPUs even if more are installed. config CROSS_BAR_47_56 hex default 0 if CPU_AMD_K8 help - Configure for the type of crossbar on the mainboard. + Configure for the type of crossbar on the mainboard. config OPTION_TABLE boolean @@ -128,14 +128,14 @@ boolean help This option is used to determine whether the mainboard has - a PIRQ table, which is the old way to set up interrupt routing. + a PIRQ table, which is the old way to set up interrupt routing. It is usually set in mainboard/*/Kconfig. config ACPI_TABLE boolean help This option is used to determine whether the mainboard has - an ACPI table. + an ACPI table. It is usually set in mainboard/*/Kconfig. config SMP @@ -143,9 +143,8 @@ depends CPU_I586 || CPU_AMD_K8 default 0 help - This option is used to enable certain functions to make - coreboot work correctly on symmetric multi processor - systems. + This option is used to enable certain functions to make coreboot + work correctly on symmetric multi processor systems. It is usually set in mainboard/*/Kconfig. config IOAPIC @@ -153,7 +152,7 @@ depends ARCH_X86 && CPU_AMD_K8 default 0 help - If you want to configure an IOAPIC, set this. + If you want to configure an IOAPIC, set this. config CARBASE hex @@ -177,36 +176,37 @@ default 0x1000 if CPU_AMD_GEODELX default 0x2000 if CPU_AMD_K8 help - This option sets the top of the memory area, in KiB, + This option sets the top of the memory area, in KiB, used for coreboot. config K8_HT_FREQ_1G_SUPPORT hex default 1 if CPU_AMD_K8 help - 1 Ghz. support. Opteron E0 or later can support - 1G HT, but still depends on the mainboard + 1 GHz support. Opteron E0 or later can support 1G HT, + but still depends on the mainboard. config HT_FREQ_800MHZ hex default 1 if CPU_AMD_K8 help - Can we run HT at 800 Mhz + Can we run HT at 800 MHz. config USBDEBUG_DIRECT boolean depends SOUTHBRIDGE_NVIDIA_MCP55 default 0 help - Determines if we enable USB Direct debugging. If you don't have a dongle, - this is probably of no value to you. + Determines if we enable USB Direct debugging. If you don't have + a dongle, this is probably of no value to you. config APIC_ID_OFFSET hex "APIC ID offset" default 0x10 depends IOAPIC help - This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting. + This is entirely mainboard dependent. 0x10 is a *typical* setting + but not always a good setting. menu "Debugging" @@ -214,6 +214,6 @@ bool "Test CAR area" default n help - Test the CAR area after it has been set up. + Test the CAR area after it has been set up. endmenu Modified: coreboot-v3/device/Kconfig =================================================================== --- coreboot-v3/device/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/device/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -36,7 +36,6 @@ execute PCI option ROMs natively (32bit x86 system required), in an emulator (x86emu), or ignore option ROM execution. - config PCI_OPTION_ROM_RUN_X86EMU bool "x86emu" select PCI_OPTION_ROM_RUN @@ -47,7 +46,6 @@ x86emu is slow, big and safe. All 16bit x86 code is executed in an encapsulated environment where it can not break out. - config PCI_OPTION_ROM_RUN_VM86 bool "vm86" select PCI_OPTION_ROM_RUN @@ -64,7 +62,6 @@ bool "Disabled" help Do not execute PCI option ROMs at all. - If you choose this option, VGA plugin cards will not be initialized. endchoice @@ -74,7 +71,7 @@ bool "Initialize all VGA cards" depends PCI_OPTION_ROM_RUN help - If you enable this option, all VGA cards will be initialized + If you enable this option, all VGA cards will be initialized. If you disable this option, only the first VGA card will be initialized. @@ -82,7 +79,7 @@ bool "Initialize onboard VGA first" depends PCI_OPTION_ROM_RUN help - Initialize onboard VGA chips before any plugin VGA cards + Initialize onboard VGA chips before any plugin VGA cards are initialized. endmenu @@ -99,17 +96,17 @@ bool "64 bit prefetchable memory addresses" depends CPU_AMD_K8 help - Enable support for 64-bit prefetchable memory addresses in PCI. + Enable support for 64-bit prefetchable memory addresses in PCI. config HW_MEM_HOLE_SIZEK hex "HW memory hole size in KB" depends CPU_AMD_K8 default 0x1000 help - Some chipsets support setting up a "hole" at the top of memory. It is essentially - a hole torn in the physical address space so that you can fit non-memory resources - (e.g. flash) at the top of the 4G address space. Given that this only happens on machines - with lots of memory, the default 4 MB is a very reasonable value. - + Some chipsets support setting up a "hole" at the top of memory. + It is essentially a hole torn in the physical address space so that + you can fit non-memory resources (e.g. flash) at the top of the 4G + address space. Given that this only happens on machines with lots + of memory, the default 4 MB is a very reasonable value. endmenu Modified: coreboot-v3/lib/Kconfig =================================================================== --- coreboot-v3/lib/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/lib/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -200,15 +200,21 @@ Debug Port capability. Controllers which are known to work: * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card) - * 10de:0088 NVIDIA MCP2A - * 10de:005b NVIDIA CK804 - * 10de:036d NVIDIA MCP55 + * 8086:24cd Intel ICH4/ICH4-M * 8086:24dd Intel ICH5 * 8086:265c Intel ICH6 * 8086:268c Intel 631xESB/632xESB/3100 * 8086:27cc Intel ICH7 * 8086:2836 Intel ICH8 * 8086:283a Intel ICH8 + * 8086:293a Intel ICH9 + * 10de:0088 NVIDIA MCP2A + * 10de:005b NVIDIA CK804 + * 10de:026e NVIDIA MCP51 + * 10de:036d NVIDIA MCP55 + * 10de:03f2 NVIDIA MCP61 + * 1002:4386 ATI/AMD SB600 + * 1106:3104 VIA VX800 See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list. @@ -216,12 +222,12 @@ depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB) config CONSOLE_PREFIX - bool "Prefix all console output with '(LB)'" + bool "Prefix all console output with '(CB)'" depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB) default n help When you enable this option, coreboot will prefix each line of - console output with '(LB)'. + console output with '(CB)'. config CONSOLE_BUFFER boolean "Console memory buffer support" Modified: coreboot-v3/lib/console.c =================================================================== --- coreboot-v3/lib/console.c 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/lib/console.c 2008-10-01 18:29:22 UTC (rev 879) @@ -116,7 +116,7 @@ #ifdef CONFIG_CONSOLE_PREFIX uart8250_tx_byte(TTYSx_BASE, '\n'); uart8250_tx_byte(TTYSx_BASE, '('); - uart8250_tx_byte(TTYSx_BASE, 'L'); + uart8250_tx_byte(TTYSx_BASE, 'C'); uart8250_tx_byte(TTYSx_BASE, 'B'); uart8250_tx_byte(TTYSx_BASE, ')'); uart8250_tx_byte(TTYSx_BASE, ' '); Modified: coreboot-v3/mainboard/Kconfig =================================================================== --- coreboot-v3/mainboard/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/mainboard/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -40,8 +40,7 @@ config VENDOR_AMP bool "AMP" help - Select this option for various systems from - Advanced Micro Devices, Inc. + Select this option for various systems from AMP. config VENDOR_ARTECGROUP bool "Artec Group" @@ -49,9 +48,9 @@ Select this option for various systems from the Artec Group. config VENDOR_GIGABYTE - bool "Gigabyte" + bool "GIGABYTE" help - Select this option for various systems from Gigabyte + Select this option for various systems from GIGABYTE. config VENDOR_EMULATION bool "Emulated systems" Modified: coreboot-v3/mainboard/amd/Kconfig =================================================================== --- coreboot-v3/mainboard/amd/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/mainboard/amd/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -56,7 +56,7 @@ select SUPERIO_WINBOND_W83627HF select IOAPIC help - AMD Serengeti + AMD Serengeti development board. endchoice Modified: coreboot-v3/mainboard/amp/Kconfig =================================================================== --- coreboot-v3/mainboard/amp/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/mainboard/amp/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -33,7 +33,7 @@ select SUPERIO_ITE_IT8716F select PIRQ_TABLE help - AMP TinyGX + AMP TinyGX board. endchoice Modified: coreboot-v3/mainboard/gigabyte/Kconfig =================================================================== --- coreboot-v3/mainboard/gigabyte/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/mainboard/gigabyte/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -24,7 +24,7 @@ depends on VENDOR_GIGABYTE config BOARD_GIGABYTE_M57SLI - bool "M57SLI" + bool "GA-M57SLI-S4" select ARCH_X86 select OPTION_TABLE select CPU_AMD_K8 @@ -33,7 +33,7 @@ select SUPERIO_ITE_IT8716F select IOAPIC help - Gigabyte M57SLI + GIGABYTE GA-M57SLI-S4. endchoice Modified: coreboot-v3/mainboard/pcengines/Kconfig =================================================================== --- coreboot-v3/mainboard/pcengines/Kconfig 2008-10-01 17:54:56 UTC (rev 878) +++ coreboot-v3/mainboard/pcengines/Kconfig 2008-10-01 18:29:22 UTC (rev 879) @@ -24,7 +24,7 @@ depends on VENDOR_PCENGINES config BOARD_PCENGINES_ALIX1C - bool "ALIX1.C" + bool "ALIX.1C" select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE @@ -33,7 +33,7 @@ select SUPERIO_WINBOND_W83627HF select PIRQ_TABLE help - PC Engines ALIX1.C. + PC Engines ALIX.1C. config BOARD_PCENGINES_ALIX2C3 bool "ALIX.2C3"

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r878 - in coreboot-v3/mainboard/amp: . tinygx
by svn＠coreboot.org 01 Oct '08

01 Oct '08

Author: uwe Date: 2008-10-01 19:54:56 +0200 (Wed, 01 Oct 2008) New Revision: 878 Modified: coreboot-v3/mainboard/amp/Kconfig coreboot-v3/mainboard/amp/tinygx/dts coreboot-v3/mainboard/amp/tinygx/initram.c coreboot-v3/mainboard/amp/tinygx/irq_tables.h coreboot-v3/mainboard/amp/tinygx/stage1.c Log: Coding style and documentation fixes for AMP TinyGX (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/mainboard/amp/Kconfig =================================================================== --- coreboot-v3/mainboard/amp/Kconfig 2008-10-01 07:23:05 UTC (rev 877) +++ coreboot-v3/mainboard/amp/Kconfig 2008-10-01 17:54:56 UTC (rev 878) @@ -33,7 +33,7 @@ select SUPERIO_ITE_IT8716F select PIRQ_TABLE help - SMP TinyGX + AMP TinyGX endchoice Modified: coreboot-v3/mainboard/amp/tinygx/dts =================================================================== --- coreboot-v3/mainboard/amp/tinygx/dts 2008-10-01 07:23:05 UTC (rev 877) +++ coreboot-v3/mainboard/amp/tinygx/dts 2008-10-01 17:54:56 UTC (rev 878) @@ -37,7 +37,7 @@ pci@f,0 { /config/("southbridge/amd/cs5536/dts"); /* Interrupt enables for LPC bus. - * Each bit is an IRQ 0-15. */ + * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ lpc_serirq_polarity = "0x0000EF25"; Modified: coreboot-v3/mainboard/amp/tinygx/initram.c =================================================================== --- coreboot-v3/mainboard/amp/tinygx/initram.c 2008-10-01 07:23:05 UTC (rev 877) +++ coreboot-v3/mainboard/amp/tinygx/initram.c 2008-10-01 17:54:56 UTC (rev 878) @@ -37,7 +37,7 @@ extern int smbus_read_byte(u16 device, u8 address); #define MANUALCONF 0 /* Do automatic strapped PLL config */ -#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */ #define PLLMSRLO 0x02000030 #define DIMM0 ((u8) 0xA0) #define DIMM1 ((u8) 0xA2) @@ -59,31 +59,28 @@ u8 spdbyte; printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - spdbyte = smbus_read_byte(device, address); - printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte); return spdbyte; } /** - * Placeholder in case we ever need it. Since this file is a - * template for other motherboards, we want this here and we want the - * call in the right place. - */ - + * Placeholder in case we ever need it. Since this file is a template for + * other boards, we want this here and we want the call in the right place. + */ static void mb_gpio_init(void) { /* Early mainboard specific GPIO setup */ } /** - * main for initram for the AMD DB800 development platform. - * It might seem that you could somehow do these functions in, e.g., the cpu - * code, but the order of operations and what those operations are is VERY - * strongly mainboard dependent. It's best to leave it in the mainboard code. - */ + * main() for initram. + * + * It might seem that you could somehow do these functions in, e.g., the CPU + * code, but the order of operations and what those operations are is VERY + * strongly mainboard dependent. It's best to leave it in the mainboard code. + */ int main(void) { printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n"); @@ -110,8 +107,8 @@ sdram_enable(DIMM0, DIMM1); printk(BIOS_DEBUG, "done sdram enable\n"); - /* Check low memory */ - /*ram_check(0x00000000, 640*1024); */ + /* Check low memory. */ + /* ram_check(0x00000000, 640 * 1024); */ printk(BIOS_DEBUG, "stage1 returns\n"); return 0; Modified: coreboot-v3/mainboard/amp/tinygx/irq_tables.h =================================================================== --- coreboot-v3/mainboard/amp/tinygx/irq_tables.h 2008-10-01 07:23:05 UTC (rev 877) +++ coreboot-v3/mainboard/amp/tinygx/irq_tables.h 2008-10-01 17:54:56 UTC (rev 878) @@ -41,14 +41,10 @@ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ /* - * AMD DB800 interrupt wiring. + * AMP TinyGX interrupt wiring. * - * Devices are: - * - * FIXME - * + * Devices are: FIXME */ - const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, @@ -62,7 +58,7 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ Modified: coreboot-v3/mainboard/amp/tinygx/stage1.c =================================================================== --- coreboot-v3/mainboard/amp/tinygx/stage1.c 2008-10-01 07:23:05 UTC (rev 877) +++ coreboot-v3/mainboard/amp/tinygx/stage1.c 2008-10-01 17:54:56 UTC (rev 878) @@ -36,18 +36,18 @@ void hardware_stage1(void) { void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); geodelx_msr_init(); - cs5536_stage1(); - /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536. + /* + * Note: Must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. */ cs5536_disable_internal_uart(); + it8716f_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); - } void mainboard_pre_payload(void)

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current k8 diff
by ron minnich 01 Oct '08

01 Oct '08

This actually builds an m57sli but this time there is real dram init inside. Please, I know that formatting is not always great, that is for another day. You should see what I am starting from :-) romcc, as wonderful as it is, got us into some really bad habits! ron

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FILO patch: color command: Report correct error
by Alex Mauer 01 Oct '08

01 Oct '08

Attached please find a patch which does: *Make the FILO 'color' command set a more helpful errnum rather than using the one from the integer parser. Signed-off-by: Alex Mauer <hawke(a)hawkensest.net>

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FILO patch: color command: make color byte like VGA.
by Alex Mauer 01 Oct '08

01 Oct '08

Attached please find a patch for FILO which: * Swaps the order of the nybbles in the color setting byte to make it the same as the traditional VGA BIOS color byte. Signed-off-by: Alex Mauer <hawke(a)hawkesnest.net>

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typo (was: Re: r3552 - in trunk/payloads/libpayload: i386 include)
by Paul Menzel 01 Oct '08

01 Oct '08

Am Freitag, den 29.08.2008, 01:12 +0200 schrieb svn(a)coreboot.org: > Modified: trunk/payloads/libpayload/include/libpayload.h > =================================================================== > --- trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:12:02 UTC (rev 3551) > +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:12:22 UTC (rev 3552) > @@ -244,6 +244,7 @@ > long long int llabs(long long int j); > u8 bin2hex(u8 b); > u8 hex2bin(u8 h); > +void fatal(const char* msg) __attribute__ ((noreturn)); > /** @} */ > > /** > @@ -398,6 +399,8 @@ > > /** > * @defgroup arch Architecture Specific Functions > + * This modules contains global architecure specific functions. s/architecure/architecture/ See patch. Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>

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coreboot October 2008