coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

stop_ap is missing for QEMU, breaks v3 compile
by Myles Watson 02 Oct '08

02 Oct '08

Make v3 for QEMU build again by adding stop_ap which does nothing. I'm not sure this is the right place for it, but it compiles. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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Status of OpenVSA?
by Stephen Crocker 02 Oct '08

02 Oct '08

I have been experimenting with the OpenVSA code and have found that it becomes stuck on POST code 17. By adding extra codes, I have narrowed this down to the SAVE_STATE macro, which reads the PCI address port (cf8). Furthermore, in order to build it, I had to remove the -Werror flag from the Makefile because of several "cast from pointer to integer of different size" errors. What is the status of the OpenVSA code at the moment? Are these known problems or could it be a problem with my build environment? Has anyone used it successfully?

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r3633 build service
by coreboot information 02 Oct '08

02 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3633 to the coreboot source repository and caused the following changes: Change Log: Whitespace cleanup (trivial). Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3633&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3633&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3633&device=epia-cn&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3632 build service
by coreboot information 02 Oct '08

02 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3632 to the coreboot source repository and caused the following changes: Change Log: Whitespace cleanup (trivial). Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3632&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3632&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3632&device=epia-cn&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] r3631 - trunk/coreboot-v2/src/southbridge/nvidia/ck804
by Carl-Daniel Hailfinger 02 Oct '08

02 Oct '08

Hi Uwe, thanks for cleaning up the codeing style. However, it seems that indent also did some readability damage. Could you perhaps fix up these places? Review follows. Regards, Carl-Daniel On 02.10.2008 20:19, svn(a)coreboot.org wrote: > Author: uwe > Date: 2008-10-02 20:19:17 +0200 (Thu, 02 Oct 2008) > New Revision: 3631 > > Log: > CK804 coding-style fixed based on an 'indent' run (trivial). > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h 2008-10-02 18:19:17 UTC (rev 3631) > @@ -1,8 +1,7 @@ > #ifndef CK804_CHIP_H > #define CK804_CHIP_H > > -struct southbridge_nvidia_ck804_config > -{ > +struct southbridge_nvidia_ck804_config { > unsigned int usb1_hc_reset : 1; > unsigned int ide0_enable : 1; > unsigned int ide1_enable : 1; > @@ -16,4 +15,4 @@ > struct chip_operations; > extern struct chip_operations southbridge_nvidia_ck804_ops; > > -#endif /* CK804_CHIP_H */ > +#endif > Was the change above intentional? > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -4,9 +4,7 @@ > */ > > #include <console/console.h> > - > #include <arch/io.h> > - > #include <device/device.h> > #include <device/pci.h> > #include <device/pci_ids.h> > @@ -15,178 +13,167 @@ > > static uint32_t final_reg; > > -static device_t find_lpc_dev( device_t dev, unsigned devfn) > +static device_t find_lpc_dev(device_t dev, unsigned devfn) > { > - > device_t lpc_dev; > > - lpc_dev = dev_find_slot(dev->bus->secondary, devfn); > + lpc_dev = dev_find_slot(dev->bus->secondary, devfn); > + if (!lpc_dev) > + return lpc_dev; > > - if ( !lpc_dev ) return lpc_dev; > + if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) > + || ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) > + && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) > + && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE))) > + { > + uint32_t id; > + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); > + if ((id != (PCI_VENDOR_ID_NVIDIA | > + (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) > + && (id != (PCI_VENDOR_ID_NVIDIA | > + (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) > + && (id != (PCI_VENDOR_ID_NVIDIA | > + (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))) > + { > + lpc_dev = 0; > + } > + } > > - if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || ( > - (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) && > - (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) && > - (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) { > - uint32_t id; > - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); > - if ( (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) && > - (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) && > - (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))) > - ) { > - lpc_dev = 0; > - } > - } > - > return lpc_dev; > } > > void ck804_enable(device_t dev) > { > device_t lpc_dev; > - unsigned index = 0; > - unsigned index2 = 0; > + unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; > Confusing, see also below. > uint32_t reg_old, reg; > uint8_t byte; > - unsigned deviceid; > - unsigned vendorid; > > - struct southbridge_nvidia_ck804_config *conf; > - conf = dev->chip_info; > + struct southbridge_nvidia_ck804_config *conf; > + conf = dev->chip_info; > > - unsigned devfn; > - > - if(dev->device==0x0000) { > + if (dev->device == 0x0000) { > vendorid = pci_read_config32(dev, PCI_VENDOR_ID); > - deviceid = (vendorid>>16) & 0xffff; > -// vendorid &= 0xffff; > + deviceid = (vendorid >> 16) & 0xffff; > + /* vendorid &= 0xffff; */ > } else { > -// vendorid = dev->vendor; > + /* vendorid = dev->vendor; */ > deviceid = dev->device; > } > > devfn = (dev->path.u.pci.devfn) & ~7; > - switch(deviceid) { > - case PCI_DEVICE_ID_NVIDIA_CK804_SM: > - index = 16; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_USB: > - devfn -= (1<<3); > - index = 8; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_USB2: > - devfn -= (1<<3); > - index = 20; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_NIC: > - devfn -= (9<<3); > - index = 10; > - dev->rom_address = conf->nic_rom_address; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: > - devfn -= (9<<3); > - index = 10; > - dev->rom_address = conf->nic_rom_address; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_ACI: > - devfn -= (3<<3); > - index = 12; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_MCI: > - devfn -= (3<<3); > - index = 13; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_IDE: > - devfn -= (5<<3); > - index = 14; > - dev->rom_address = conf->raid_rom_address; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: > - devfn -= (6<<3); > - index = 22; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: > - devfn -= (7<<3); > - index = 18; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_PCI: > - devfn -= (8<<3); > - index = 15; > - break; > - case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: > - devfn -= (0xa<<3); > - index2 = 19; > - break; > - default: > - index = 0; > + switch (deviceid) { > + case PCI_DEVICE_ID_NVIDIA_CK804_SM: > + index = 16; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_USB: > + devfn -= (1 << 3); > + index = 8; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_USB2: > + devfn -= (1 << 3); > + index = 20; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_NIC: > + devfn -= (9 << 3); > + index = 10; > + dev->rom_address = conf->nic_rom_address; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: > + devfn -= (9 << 3); > + index = 10; > + dev->rom_address = conf->nic_rom_address; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_ACI: > + devfn -= (3 << 3); > + index = 12; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_MCI: > + devfn -= (3 << 3); > + index = 13; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_IDE: > + devfn -= (5 << 3); > + index = 14; > + dev->rom_address = conf->raid_rom_address; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: > + devfn -= (6 << 3); > + index = 22; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: > + devfn -= (7 << 3); > + index = 18; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_PCI: > + devfn -= (8 << 3); > + index = 15; > + break; > + case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: > + devfn -= (0xa << 3); > + index2 = 19; > + break; > + default: > + index = 0; > } > > - if(index2!=0) { > + if (index2 != 0) { > int i; > - for(i=0;i<4;i++) { > - lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); > - if(!lpc_dev) continue; > + for (i = 0; i < 4; i++) { > + lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); > + if (!lpc_dev) > + continue; > index2 -= i; > break; > } > > - if ( lpc_dev ) { > - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); > - > - if (!dev->enabled) { > - reg |= (1<<index2); > - } > - > - if (reg != reg_old) { > - pci_write_config32(lpc_dev, 0xe4, reg); > - } > + if (lpc_dev) { > + reg_old = reg = pci_read_config32(lpc_dev, 0xe4); > + if (!dev->enabled) > + reg |= (1 << index2); > + if (reg != reg_old) > + pci_write_config32(lpc_dev, 0xe4, reg); > } > > index2 = 0; > return; > } > > - > lpc_dev = find_lpc_dev(dev, devfn); > + if (!lpc_dev) > + return; > > - if ( !lpc_dev ) return; > - > - if ( index == 0) { > - > + if (index == 0) { > final_reg = pci_read_config32(lpc_dev, 0xe8); > - final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15)); > - pci_write_config32(lpc_dev, 0xe8, final_reg); > + final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10) > + | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22) > + | (1 << 18) | (1 << 15)); > + pci_write_config32(lpc_dev, 0xe8, final_reg); > > - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); > - reg |= (1<<20); > - if (reg != reg_old) { > - pci_write_config32(lpc_dev, 0xe4, reg); > - } > + reg_old = reg = pci_read_config32(lpc_dev, 0xe4); > + reg |= (1 << 20); > + if (reg != reg_old) > + pci_write_config32(lpc_dev, 0xe4, reg); > > - byte = pci_read_config8(lpc_dev, 0x74); > - byte |= ((1<<1)); > - pci_write_config8(dev, 0x74, byte); > + byte = pci_read_config8(lpc_dev, 0x74); > + byte |= ((1 << 1)); > + pci_write_config8(dev, 0x74, byte); > > - byte = pci_read_config8(lpc_dev, 0xdd); > - byte |= ((1<<0)|(1<<3)); > - pci_write_config8(dev, 0xdd, byte); > + byte = pci_read_config8(lpc_dev, 0xdd); > + byte |= ((1 << 0) | (1 << 3)); > + pci_write_config8(dev, 0xdd, byte); > > return; > + } > > - } > + if (!dev->enabled) > + final_reg |= (1 << index); > > - if (!dev->enabled) { > - final_reg |= (1 << index); > - } > - > - if(index == 10 ) { > + if (index == 10) { > reg_old = pci_read_config32(lpc_dev, 0xe8); > - if (final_reg != reg_old) { > - pci_write_config32(lpc_dev, 0xe8, final_reg); > - } > - > + if (final_reg != reg_old) > + pci_write_config32(lpc_dev, 0xe8, final_reg); > } > - > } > > struct chip_operations southbridge_nvidia_ck804_ops = { > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h 2008-10-02 18:19:17 UTC (rev 3631) > @@ -5,4 +5,4 @@ > > void ck804_enable(device_t dev); > > -#endif /* CK804_H */ > +#endif > Comment removal. > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > #include <console/console.h> > #include <device/device.h> > #include <device/pci.h> > @@ -11,19 +12,19 @@ > > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > - pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + pci_write_config32(dev, 0x40, > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > > static struct pci_operations lops_pci = { > - .set_subsystem = lpci_set_subsystem, > + .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations ac97audio_ops = { > +static struct device_operations ac97audio_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > This actually kills readable indentation. > .init = 0, > .scan_bus = 0, > .ops_pci = &lops_pci, > @@ -35,12 +36,11 @@ > .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, > }; > > - > -static struct device_operations ac97modem_ops = { > +static struct device_operations ac97modem_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Same here. > .init = 0, > .scan_bus = 0, > .ops_pci = &lops_pci, > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > static int set_ht_link_ck804(uint8_t ht_c_num) > { > unsigned vendorid = 0x10de; > @@ -9,10 +10,10 @@ > return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); > } > > -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) > +static void setup_ss_table(unsigned index, unsigned where, unsigned control, > + const unsigned int *register_values, int max) > { > int i; > - > unsigned val; > > val = inl(control); > @@ -21,7 +22,7 @@ > > outl(0, index); > > - for(i = 0; i < max; i++) { > + for (i = 0; i < max; i++) { > unsigned long reg; > reg = register_values[i]; > outl(reg, where); > @@ -29,67 +30,61 @@ > val = inl(control); > val |= 1; > outl(val, control); > - > } > > #define ANACTRL_IO_BASE 0x7000 > #define ANACTRL_REG_POS 0x68 > > - > #define SYSCTRL_IO_BASE 0x6000 > #define SYSCTRL_REG_POS 0x64 > > /* > - 16 1 1 2 :0 > - 8 8 2 2 :1 > - 8 8 4 :2 > - 8 4 4 4 :3 > - 16 4 :4 > + * 16 1 1 2 :0 > + * 8 8 2 2 :1 > + * 8 8 4 :2 > + * 8 4 4 4 :3 > + * 16 4 :4 > */ > > #ifndef CK804_PCI_E_X > - #define CK804_PCI_E_X 4 > +#define CK804_PCI_E_X 4 > #endif > > #if CK804_NUM > 1 > - #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000) > - #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000) > - > - #ifndef CK804B_BUSN > - #define CK804B_BUSN 0x80 > - #endif > - > - #ifndef CK804B_PCI_E_X > - #define CK804B_PCI_E_X 4 > - #endif > +#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) > +#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000) > +#ifndef CK804B_BUSN > +#define CK804B_BUSN 0x80 > #endif > +#ifndef CK804B_PCI_E_X > +#define CK804B_PCI_E_X 4 > +#endif > +#endif > > #ifndef CK804_USE_NIC > - #define CK804_USE_NIC 0 > +#define CK804_USE_NIC 0 > #endif > > #ifndef CK804_USE_ACI > - #define CK804_USE_ACI 0 > +#define CK804_USE_ACI 0 > #endif > > #define CK804_CHIP_REV 3 > > #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE > - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE > +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE > #else > - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE > +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE > #endif > > #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 > - #define CK804B_DEVN_BASE 1 > +#define CK804B_DEVN_BASE 1 > #else > - #define CK804B_DEVN_BASE CK804_DEVN_BASE > +#define CK804B_DEVN_BASE CK804_DEVN_BASE > #endif > > - > static void ck804_early_set_port(void) > { > - > static const unsigned int ctrl_devport_conf[] = { > PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, > #if CK804_NUM > 1 > @@ -103,12 +98,10 @@ > }; > > setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); > - > } > > static void ck804_early_clear_port(void) > { > - > static const unsigned int ctrl_devport_conf_clear[] = { > PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, > #if CK804_NUM > 1 > @@ -122,84 +115,70 @@ > }; > > setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); > - > } > > static void ck804_early_setup(void) > { > - > static const unsigned int ctrl_conf[] = { > > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, > > - > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, > - > - > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, > #endif > > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, > > - > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, > - > - > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, > #endif > > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, > - RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, > - > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, > - RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, > #endif > > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, > - > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, > #endif > > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, > - > - > - > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, > #endif > > - > RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, > RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, > RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, > @@ -208,139 +187,125 @@ > RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, > > RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), > > #if CK804_NUM > 1 > - > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, > - > #endif > > - > RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, > #if CK804_NUM > 1 > RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, > #endif > > - // Activate master port on primary SATA controller > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000, > + /* Activate master port on primary SATA controller. */ > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, > - > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, > #endif > > - > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), > #if CK804_NUM > 1 > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), > #endif > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, > #if CK804_NUM > 1 > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, > #endif > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), > #if CK804_NUM > 1 > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), > #endif > > - > - > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), > #if CK804_USE_NIC == 1 > - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), > + RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), > #endif > > #if CK804_USE_ACI == 1 > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), > #endif > > #if CK804_NUM > 1 > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), > #endif > > - > #if CK804_NUM > 1 > - #if CK804_USE_NIC == 1 > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, > - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), > - #endif > +#if CK804_USE_NIC == 1 > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, > + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), > #endif > +#endif > > - > - > #ifdef CK804_MB_SETUP > CK804_MB_SETUP > #endif > - > }; > > - > - > setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); > > - setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); > - setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); > - setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); > + setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); > + setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); > + setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); > > #if CK804_NUM > 1 > - setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64); > - setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64); > - setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64); > + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); > + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); > + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); > #endif > > #if 0 > dump_io_resources(ANACTRL_IO_BASE); > dump_io_resources(SYSCTRL_IO_BASE); > #endif > - > } > > static int ck804_early_setup_x(void) > @@ -369,4 +334,3 @@ > outb(0x06, 0x0cf9); > #endif > } > - > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -11,365 +11,339 @@ > return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); > } > > -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) > +static void setup_ss_table(unsigned index, unsigned where, unsigned control, > + const unsigned int *register_values, int max) > { > int i; > - > unsigned val; > + > val = inl(control); > val &= 0xfffffffe; > outl(val, control); > > outl(0, index); > > - for(i = 0; i < max; i++) { > + for (i = 0; i < max; i++) { > unsigned long reg; > - > reg = register_values[i]; > outl(reg, where); > } > + > val = inl(control); > val |= 1; > outl(val, control); > - > } > > #define ANACTRL_IO_BASE 0x3000 > #define ANACTRL_REG_POS 0x68 > > - > #define SYSCTRL_IO_BASE 0x2000 > #define SYSCTRL_REG_POS 0x64 > > /* > - 16 1 1 2 :0 > - 8 8 2 2 :1 > - 8 8 4 :2 > - 8 4 4 4 :3 > - 16 4 :4 > + * 16 1 1 2 :0 > + * 8 8 2 2 :1 > + * 8 8 4 :2 > + * 8 4 4 4 :3 > + * 16 4 :4 > */ > > #ifndef CK804_PCI_E_X > - #define CK804_PCI_E_X 4 > +#define CK804_PCI_E_X 4 > #endif > > - /* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */ > - #define CK804B_ANACTRL_IO_BASE 0x3000 > - #define CK804B_SYSCTRL_IO_BASE 0x2000 > +/* > + * We will use the offset in setup_resource_map_x_offset and > + * setup_resource_map_offset. > + */ > +#define CK804B_ANACTRL_IO_BASE 0x3000 > +#define CK804B_SYSCTRL_IO_BASE 0x2000 > > - #ifdef CK804B_BUSN > - #undef CK804B_BUSN > - #endif > - #define CK804B_BUSN 0x0 > +#ifdef CK804B_BUSN > +#undef CK804B_BUSN > +#endif > +#define CK804B_BUSN 0x0 > > - #ifndef CK804B_PCI_E_X > - #define CK804B_PCI_E_X 4 > - #endif > +#ifndef CK804B_PCI_E_X > +#define CK804B_PCI_E_X 4 > +#endif > > #ifndef CK804_USE_NIC > - #define CK804_USE_NIC 0 > +#define CK804_USE_NIC 0 > #endif > > #ifndef CK804_USE_ACI > - #define CK804_USE_ACI 0 > +#define CK804_USE_ACI 0 > #endif > > #define CK804_CHIP_REV 3 > > #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE > - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE > +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE > #else > - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE > +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE > #endif > > #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 > - #define CK804B_DEVN_BASE 1 > +#define CK804B_DEVN_BASE 1 > #else > - #define CK804B_DEVN_BASE CK804_DEVN_BASE > +#define CK804B_DEVN_BASE CK804_DEVN_BASE > #endif > > -static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) > +static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, > + unsigned *io_base) > { > - > static const unsigned int ctrl_devport_conf[] = { > - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, > - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, > + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, > + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, > }; > > static const unsigned int ctrl_devport_conf_b[] = { > - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, > - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, > + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, > + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, > }; > > int j; > - for(j = 0; j < ck804_num; j++ ) { > - if(busn[j]==0) { //sb chain > + for (j = 0; j < ck804_num; j++) { > + if (busn[j] == 0) { //sb chain > setup_resource_map_offset(ctrl_devport_conf, > ARRAY_SIZE(ctrl_devport_conf), > - PCI_DEV(busn[j], 0, 0) , io_base[j]); > + PCI_DEV(busn[j], 0, 0), io_base[j]); > continue; > } > setup_resource_map_offset(ctrl_devport_conf_b, > - ARRAY_SIZE(ctrl_devport_conf_b), > - PCI_DEV(busn[j], 0, 0) , io_base[j]); > + ARRAY_SIZE(ctrl_devport_conf_b), > + PCI_DEV(busn[j], 0, 0), io_base[j]); > } > } > > -static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) > +static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, > + unsigned *io_base) > { > - > static const unsigned int ctrl_devport_conf_clear[] = { > - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, > - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, > + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, > + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, > }; > > static const unsigned int ctrl_devport_conf_clear_b[] = { > - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, > - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, > + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, > + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, > }; > > int j; > - for(j = 0; j < ck804_num; j++ ) { > - if(busn[j]==0) { //sb chain > + for (j = 0; j < ck804_num; j++) { > + if (busn[j] == 0) { //sb chain > setup_resource_map_offset(ctrl_devport_conf_clear, > ARRAY_SIZE(ctrl_devport_conf_clear), > - PCI_DEV(busn[j], 0, 0) , io_base[j]); > + PCI_DEV(busn[j], 0, 0), io_base[j]); > continue; > } > setup_resource_map_offset(ctrl_devport_conf_clear_b, > - ARRAY_SIZE(ctrl_devport_conf_clear_b), > - PCI_DEV(busn[j], 0, 0) , io_base[j]); > + ARRAY_SIZE(ctrl_devport_conf_clear_b), > + PCI_DEV(busn[j], 0, 0), io_base[j]); > } > - > - > } > > - > -static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base) > +static void ck804_early_setup(unsigned ck804_num, unsigned *busn, > + unsigned *io_base) > { > - > static const unsigned int ctrl_conf_master[] = { > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, > > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, > > - > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, > - RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, > - > - > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, > - > - > #ifdef CK804_MB_SETUP > - CK804_MB_SETUP > + CK804_MB_SETUP > #endif > - > - > #if CK804_NUM > 1 > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, > - > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, > #endif > > #if CK804_NUM == 1 > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, > - > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, > #endif > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), > > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, > > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), > > +// PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, > > -//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, > + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), > > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, > - > - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), > - > - > //SYSCTRL > - > - > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), > #if CK804_USE_NIC == 1 > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), > - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), > + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), > #endif > > #if CK804_USE_ACI == 1 > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), > #endif > > #if CK804_NUM > 1 > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), > #endif > - > - > }; > > - > - > - > static const unsigned int ctrl_conf_slave[] = { > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, > > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, > > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, > > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, > > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, > > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, > > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, > - RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, > > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, > > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), > > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, > +//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, > > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, > > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, > + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), > > - > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), > - > -//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, > - > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, > - > - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), > - > - #if CK804_USE_NIC == 1 > - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), > - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), > - #endif > - > +#if CK804_USE_NIC == 1 > + RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), > + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), > +#endif > }; > > int j; > - > - for(j=0; j<ck804_num; j++) { > - if(busn[j] == 0) { > - setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), > - PCI_DEV(busn[0],0,0), io_base[0]); > + for (j = 0; j < ck804_num; j++) { > + if (busn[j] == 0) { > + setup_resource_map_x_offset(ctrl_conf_master, > + ARRAY_SIZE(ctrl_conf_master), > + PCI_DEV(busn[0], 0, 0), io_base[0]); > continue; > } > > - > - setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave), > - PCI_DEV(busn[j],0,0), io_base[j]); > + setup_resource_map_x_offset(ctrl_conf_slave, > + ARRAY_SIZE(ctrl_conf_slave), > + PCI_DEV(busn[j], 0, 0), io_base[j]); > } > > - for(j=0; j< ck804_num; j++) { > - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 > - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 > - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 > - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, > - io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); > - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, > - io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); > -//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, > -// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); > + for (j = 0; j < ck804_num; j++) { > + /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ > + /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ > + /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ > + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, > + io_base[j] + ANACTRL_IO_BASE + 0x44, > + io_base[j] + ANACTRL_IO_BASE + 0x48, > + pcie_ss_tbl, 64); > + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, > + io_base[j] + ANACTRL_IO_BASE + 0xb4, > + io_base[j] + ANACTRL_IO_BASE + 0xb8, > + sata_ss_tbl, 64); > +//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, > +// io_base[j] + ANACTRL_IO_BASE + 0xc4, > +// io_base[j] + ANACTRL_IO_BASE + 0xc8, > +// cpu_ss_tbl, 64); > } > - > - > } > > static int ck804_early_setup_x(void) > { > - unsigned busn[4]; > - unsigned io_base[4]; > - int ck804_num = 0; > - int i; > + unsigned busn[4], io_base[4]; > + int i, ck804_num = 0; > I know it is correct to do write code that way, but I wonder each time if the code actually means i=0, ck804num=0. > > - for(i=0;i<4;i++) { > + for (i = 0; i < 4; i++) { > uint32_t id; > device_t dev; > - if(i == 0) { // SB chain > - dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0); > - } > - else { > - dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0); > - } > + if (i == 0) // SB chain > + dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); > + else > + dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); > id = pci_read_config32(dev, PCI_VENDOR_ID); > - if(id == 0x005e10de) { > + if (id == 0x005e10de) { > busn[ck804_num] = i * 0x40; > io_base[ck804_num] = i * 0x4000; > ck804_num++; > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -13,61 +13,61 @@ > static void ide_init(struct device *dev) > { > struct southbridge_nvidia_ck804_config *conf; > - /* Enable ide devices so the linux ide driver will work */ > uint32_t dword; > uint16_t word; > uint8_t byte; > + > conf = dev->chip_info; > > word = pci_read_config16(dev, 0x50); > - /* Ensure prefetch is disabled */ > + /* Ensure prefetch is disabled. */ > word &= ~((1 << 15) | (1 << 13)); > if (conf->ide1_enable) { > - /* Enable secondary ide interface */ > - word |= (1<<0); > + /* Enable secondary IDE interface. */ > + word |= (1 << 0); > printk_debug("IDE1 \t"); > } > if (conf->ide0_enable) { > - /* Enable primary ide interface */ > - word |= (1<<1); > + /* Enable primary IDE interface. */ > + word |= (1 << 1); > printk_debug("IDE0\n"); > } > > - word |= (1<<12); > - word |= (1<<14); > + word |= (1 << 12); > + word |= (1 << 14); > > pci_write_config16(dev, 0x50, word); > > - > - byte = 0x20 ; // Latency: 64-->32 > + byte = 0x20; /* Latency: 64 --> 32 */ > pci_write_config8(dev, 0xd, byte); > > dword = pci_read_config32(dev, 0xf8); > dword |= 12; > pci_write_config32(dev, 0xf8, dword); > + > #if CONFIG_PCI_ROM_RUN == 1 > pci_dev_init(dev); > #endif > - > } > > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > + > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations ide_ops = { > +static struct device_operations ide_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > - .init = ide_init, > - .scan_bus = 0, > -// .enable = ck804_enable, > - .ops_pci = &lops_pci, > + .init = ide_init, > + .scan_bus = 0, > + // .enable = ck804_enable, > Indentation was better before. > + .ops_pci = &lops_pci, > }; > > static const struct pci_driver ide_driver __pci_driver = { > @@ -75,4 +75,3 @@ > .vendor = PCI_VENDOR_ID_NVIDIA, > .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, > }; > - > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -4,6 +4,7 @@ > * by yhlu(a)tyan.com > * 2006.1 yhlu add dest apicid for IRQ0 > */ > + > #include <console/console.h> > #include <device/device.h> > #include <device/pci.h> > @@ -44,30 +45,30 @@ > #define INT (1 << 8) > /* IO-APIC virtual wire mode configuration */ > /* mask, trigger, polarity, destination, delivery, vector */ > - { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, > - { 1, DISABLED, NONE}, > - { 2, DISABLED, NONE}, > - { 3, DISABLED, NONE}, > - { 4, DISABLED, NONE}, > - { 5, DISABLED, NONE}, > - { 6, DISABLED, NONE}, > - { 7, DISABLED, NONE}, > - { 8, DISABLED, NONE}, > - { 9, DISABLED, NONE}, > - { 10, DISABLED, NONE}, > - { 11, DISABLED, NONE}, > - { 12, DISABLED, NONE}, > - { 13, DISABLED, NONE}, > - { 14, DISABLED, NONE}, > - { 15, DISABLED, NONE}, > - { 16, DISABLED, NONE}, > - { 17, DISABLED, NONE}, > - { 18, DISABLED, NONE}, > - { 19, DISABLED, NONE}, > - { 20, DISABLED, NONE}, > - { 21, DISABLED, NONE}, > - { 22, DISABLED, NONE}, > - { 23, DISABLED, NONE}, > + {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, > + {1, DISABLED, NONE}, > + {2, DISABLED, NONE}, > + {3, DISABLED, NONE}, > + {4, DISABLED, NONE}, > + {5, DISABLED, NONE}, > + {6, DISABLED, NONE}, > + {7, DISABLED, NONE}, > + {8, DISABLED, NONE}, > + {9, DISABLED, NONE}, > + {10, DISABLED, NONE}, > + {11, DISABLED, NONE}, > + {12, DISABLED, NONE}, > + {13, DISABLED, NONE}, > + {14, DISABLED, NONE}, > + {15, DISABLED, NONE}, > + {16, DISABLED, NONE}, > + {17, DISABLED, NONE}, > + {18, DISABLED, NONE}, > + {19, DISABLED, NONE}, > + {20, DISABLED, NONE}, > + {21, DISABLED, NONE}, > + {22, DISABLED, NONE}, > + {23, DISABLED, NONE}, > /* Be careful and don't write past the end... */ > }; > > @@ -75,23 +76,22 @@ > { > int i; > unsigned long value_low, value_high; > -// unsigned long ioapic_base = 0xfec00000; > + /* unsigned long ioapic_base = 0xfec00000; */ > I don't get that change. Why did indent use another comment delimiter here? > volatile unsigned long *l; > struct ioapicreg *a = ioapicregvalues; > > - ioapicregvalues[0].value_high = lapicid()<<(56-32); > + ioapicregvalues[0].value_high = lapicid() << (56 - 32); > > - l = (unsigned long *) ioapic_base; > + l = (unsigned long *)ioapic_base; > > - for (i = 0; i < ARRAY_SIZE(ioapicregvalues); > - i++, a++) { > + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { > l[0] = (a->reg * 2) + 0x10; > l[4] = a->value_low; > value_low = l[4]; > - l[0] = (a->reg *2) + 0x11; > + l[0] = (a->reg * 2) + 0x11; > l[4] = a->value_high; > value_high = l[4]; > - if ((i==0) && (value_low == 0xffffffff)) { > + if ((i == 0) && (value_low == 0xffffffff)) { > printk_warning("IO APIC not responding.\n"); > return; > } > @@ -117,20 +117,19 @@ > uint8_t byte; > uint32_t dword; > > - /* IO APIC initialization */ > + /* I/O APIC initialization */ > byte = pci_read_config8(dev, 0x74); > - byte |= (1<<0); // enable APIC > + byte |= (1 << 0); /* Enable APIC. */ > pci_write_config8(dev, 0x74, byte); > - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 > + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ > > setup_ioapic(dword); > > #if 1 > dword = pci_read_config32(dev, 0xe4); > - dword |= (1<<23); > + dword |= (1 << 23); > pci_write_config32(dev, 0xe4, dword); > #endif > - > } > > static void lpc_slave_init(device_t dev) > @@ -138,132 +137,123 @@ > lpc_common_init(dev); > } > > -static void rom_dummy_write(device_t dev){ > +static void rom_dummy_write(device_t dev) > +{ > uint8_t old, new; > uint8_t *p; > > old = pci_read_config8(dev, 0x88); > new = old | 0xc0; > - if (new != old) { > + if (new != old) > pci_write_config8(dev, 0x88, new); > - } > - // enable write > + /* Enable write. */ > old = pci_read_config8(dev, 0x6d); > new = old | 0x01; > - if (new != old) { > + if (new != old) > pci_write_config8(dev, 0x6d, new); > - } > > - /* dummy write */ > - p = (uint8_t *)0xffffffe0; > + /* Dummy write. */ > + p = (uint8_t *) 0xffffffe0; > old = 0; > *p = old; > old = *p; > > - // disable write > + /* Disable write. */ > old = pci_read_config8(dev, 0x6d); > new = old & 0xfe; > - if (new != old) { > + if (new != old) > pci_write_config8(dev, 0x6d, new); > - > - } > - > } > + > #if 0 > static void enable_hpet(struct device *dev) > { > unsigned long hpet_address; > > - pci_write_config32(dev,0x44, 0xfed00001); > - hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; > - printk_debug("enabling HPET @0x%x\n", hpet_address); > + pci_write_config32(dev, 0x44, 0xfed00001); > + hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; > + printk_debug("Enabling HPET @0x%x\n", hpet_address); > } > #endif > > static void lpc_init(device_t dev) > { > - uint8_t byte; > - uint8_t byte_old; > - int on; > - int nmi_option; > + uint8_t byte, byte_old; > + int on, nmi_option; > > lpc_common_init(dev); > > #if CK804_CHIP_REV==1 > - if(dev->bus->secondary!=1) return; > + if (dev->bus->secondary != 1) > + return; > #endif > > #if 0 > - /* posted memory write enable */ > + /* Posted memory write enable */ > byte = pci_read_config8(dev, 0x46); > - pci_write_config8(dev, 0x46, byte | (1<<0)); > - > + pci_write_config8(dev, 0x46, byte | (1 << 0)); > #endif > - /* power after power fail */ > > + /* power after power fail */ > on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; > get_option(&on, "power_on_after_fail"); > byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); > byte &= ~0x40; > - if (!on) { > + if (!on) > byte |= 0x40; > - } > pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); > - printk_info("set power %s after power fail\n", on?"on":"off"); > + printk_info("set power %s after power fail\n", on ? "on" : "off"); > > - /* Throttle the CPU speed down for testing */ > + /* Throttle the CPU speed down for testing. */ > on = SLOW_CPU_OFF; > get_option(&on, "slow_cpu"); > - if(on) { > + if (on) { > uint16_t pm10_bar; > uint32_t dword; > - pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); > - outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); > + pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); > + outl(((on << 1) + 0x10), (pm10_bar + 0x10)); > dword = inl(pm10_bar + 0x10); > - on = 8-on; > + on = 8 - on; > printk_debug("Throttling CPU %2d.%1.1d percent.\n", > - (on*12)+(on>>1),(on&1)*5); > + (on * 12) + (on >> 1), (on & 1) * 5); > } > - > #if 0 > // default is enabled > - /* Enable Port 92 fast reset */ > + /* Enable Port 92 fast reset. */ > byte = pci_read_config8(dev, 0xe8); > byte |= ~(1 << 3); > pci_write_config8(dev, 0xe8, byte); > #endif > > - /* Enable Error reporting */ > - /* Set up sync flood detected */ > + /* Enable Error reporting. */ > + /* Set up sync flood detected. */ > byte = pci_read_config8(dev, 0x47); > byte |= (1 << 1); > pci_write_config8(dev, 0x47, byte); > > - /* Set up NMI on errors */ > - byte = inb(0x70); // RTC70 > + /* Set up NMI on errors. */ > + byte = inb(0x70); /* RTC70 */ > byte_old = byte; > nmi_option = NMI_OFF; > get_option(&nmi_option, "nmi"); > if (nmi_option) { > - byte &= ~(1 << 7); /* set NMI */ > + byte &= ~(1 << 7); /* Set NMI. */ > } else { > - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW > + byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ > } > - if( byte != byte_old) { > + if (byte != byte_old) > outb(0x70, byte); > - } > > - /* Initialize the real time clock */ > + /* Initialize the real time clock (RTC). */ > rtc_init(0); > > - /* Initialize isa dma */ > + /* Initialize ISA DMA. */ > isa_dma_init(); > > - /* Initialize the High Precision Event Timers */ > -// enable_hpet(dev); > + /* Initialize the High Precision Event Timers (HPET). */ > + /* enable_hpet(dev); */ > > rom_dummy_write(dev); > - > } > > static void ck804_lpc_read_resources(device_t dev) > @@ -271,43 +261,43 @@ > struct resource *res; > unsigned long index; > > - /* Get the normal pci resources of this device */ > - pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP > + /* Get the normal PCI resources of this device. */ > + /* We got one for APIC, or one more for TRAP. */ > + pci_dev_read_resources(dev); > > - /* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */ > - for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. > + /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ > + for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ > pci_get_resource(dev, index); > - } > compact_resources(dev); > > - /* Add an extra subtractive resource for both memory and I/O */ > + /* Add an extra subtractive resource for both memory and I/O. */ > res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); > - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > + res->flags = > + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > > res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); > - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > - > + res->flags = > + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > } > > /** > - * @brief Enable resources for children devices > + * Enable resources for children devices. > * > - * @param dev the device whos children's resources are to be enabled > - * > - * This function is call by the global enable_resources() indirectly via the > + * This function is called by the global enable_resources() indirectly via the > * device_operation::enable_resources() method of devices. > * > * Indirect mutual recursion: > * enable_childrens_resources() -> enable_resources() > * enable_resources() -> device_operation::enable_resources() > * device_operation::enable_resources() -> enable_children_resources() > + * > + * @param dev The device whose children's resources are to be enabled. > */ > static void ck804_lpc_enable_childrens_resources(device_t dev) > { > unsigned link; > uint32_t reg, reg_var[4]; > - int i; > - int var_num = 0; > + int i, var_num = 0; > > reg = pci_read_config32(dev, 0xa0); > > @@ -315,44 +305,49 @@ > device_t child; > for (child = dev->link[link].children; child; child = child->sibling) { > enable_resources(child); > - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { > - for(i=0;i<child->resources;i++) { > + if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { > + for (i = 0; i < child->resources; i++) { > struct resource *res; > - unsigned long base, end; // don't need long long > + unsigned long base, end; // don't need long long > res = &child->resource[i]; > - if(!(res->flags & IORESOURCE_IO)) continue; > + if (!(res->flags & IORESOURCE_IO)) > + continue; > base = res->base; > end = resource_end(res); > - printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); > - switch(base) { > - case 0x3f8: // COM1 > - reg |= (1<<0); break; > - case 0x2f8: // COM2 > - reg |= (1<<1); break; > - case 0x378: // Parallal 1 > - reg |= (1<<24); break; > - case 0x3f0: // FD0 > - reg |= (1<<20); break; > - case 0x220: // Aduio 0 > - reg |= (1<<8); break; > - case 0x300: // Midi 0 > - reg |= (1<<12); break; > + printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end); > + switch (base) { > + case 0x3f8: // COM1 > + reg |= (1 << 0); > + break; > + case 0x2f8: // COM2 > + reg |= (1 << 1); > + break; > + case 0x378: // Parallel 1 > + reg |= (1 << 24); > + break; > + case 0x3f0: // FD0 > + reg |= (1 << 20); > + break; > + case 0x220: // Audio 0 > + reg |= (1 << 8); > + break; > + case 0x300: // Midi 0 > + reg |= (1 << 12); > + break; > } > - if( base == 0x290 || base >= 0x400) { > - if(var_num>=4) continue; // only 4 var ; compact them ? > - reg |= (1<<(28+var_num)); > - reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); > + if (base == 0x290 || base >= 0x400) { > + if (var_num >= 4) > + continue; // only 4 var ; compact them ? > + reg |= (1 << (28 + var_num)); > + reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); > } > } > } > } > } > pci_write_config32(dev, 0xa0, reg); > - for(i=0;i<var_num;i++) { > - pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); > - } > - > - > + for (i = 0; i < var_num; i++) > + pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); > } > > static void ck804_lpc_enable_resources(device_t dev) > @@ -364,22 +359,23 @@ > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations lpc_ops = { > +static struct device_operations lpc_ops = { > .read_resources = ck804_lpc_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = ck804_lpc_enable_resources, > .init = lpc_init, > .scan_bus = scan_static_bus, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Indentation. > .ops_pci = &lops_pci, > }; > + > static const struct pci_driver lpc_driver __pci_driver = { > .ops = &lpc_ops, > .vendor = PCI_VENDOR_ID_NVIDIA, > @@ -399,12 +395,12 @@ > .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, > }; > #else > -static struct device_operations lpc_slave_ops = { > +static struct device_operations lpc_slave_ops = { > .read_resources = ck804_lpc_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > .init = lpc_slave_init, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Same here. > .ops_pci = &lops_pci, > }; > > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > #include <console/console.h> > #include <device/device.h> > #include <device/smbus.h> > @@ -11,21 +12,16 @@ > #include <arch/io.h> > #include "ck804.h" > > - > static void nic_init(struct device *dev) > { > - uint32_t dword, old; > - uint32_t mac_h, mac_l; > + uint32_t dword, old, mac_h, mac_l; > int eeprom_valid = 0; > struct southbridge_nvidia_ck804_config *conf; > - > static uint32_t nic_index = 0; > - > uint8_t *base; > struct resource *res; > > res = find_resource(dev, 0x10); > - > base = res->base; > > #define NvRegPhyInterface 0xC0 > @@ -36,37 +32,37 @@ > old = dword = pci_read_config32(dev, 0x30); > dword &= ~(0xf); > dword |= 0xf; > - if(old != dword) { > - pci_write_config32(dev, 0x30 , dword); > - } > + if (old != dword) > + pci_write_config32(dev, 0x30, dword); > > conf = dev->chip_info; > > - if(conf->mac_eeprom_smbus != 0) { > -// read MAC address from EEPROM at first > + if (conf->mac_eeprom_smbus != 0) { > + /* Read MAC address from EEPROM at first. */ > struct device *dev_eeprom; > - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); > + dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, > + conf->mac_eeprom_addr); > > - if(dev_eeprom) { > - // if that is valid we will use that > + if (dev_eeprom) { > + /* If that is valid we will use that. */ > unsigned char dat[6]; > - int status; > - int i; > - for(i=0;i<6;i++) { > + int i, status; > + for (i = 0; i < 6; i++) { > status = smbus_read_byte(dev_eeprom, i); > - if(status < 0) break; > + if (status < 0) > + break; > dat[i] = status & 0xff; > } > - if(status >= 0) { > + if (status >= 0) { > mac_l = 0; > - for(i=3;i>=0;i--) { > + for (i = 3; i >= 0; i--) { > mac_l <<= 8; > mac_l += dat[i]; > } > - if(mac_l != 0xffffffff) { > + if (mac_l != 0xffffffff) { > mac_l += nic_index; > mac_h = 0; > - for(i=5;i>=4;i--) { > + for (i = 5; i >= 4; i--) { > mac_h <<= 8; > mac_h += dat[i]; > } > @@ -75,21 +71,22 @@ > } > } > } > -// if that is invalid we will read that from romstrap > - if(!eeprom_valid) { > + > + /* If that is invalid we will read that from romstrap. */ > + if (!eeprom_valid) { > unsigned long mac_pos; > - mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds > + mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ > mac_l = readl(mac_pos) + nic_index; > mac_h = readl(mac_pos + 4); > } > #if 1 > -// set that into NIC MMIO > + /* Set that into NIC MMIO. */ > #define NvRegMacAddrA 0xA8 > #define NvRegMacAddrB 0xAC > writel(mac_l, base + NvRegMacAddrA); > writel(mac_h, base + NvRegMacAddrB); > #else > -// set that into NIC > + /* Set that into NIC. */ > pci_write_config32(dev, 0xa8, mac_l); > pci_write_config32(dev, 0xac, mac_h); > #endif > @@ -97,35 +94,36 @@ > nic_index++; > > #if CONFIG_PCI_ROM_RUN == 1 > - pci_dev_init(dev);// it will init option rom > + pci_dev_init(dev); /* It will init Option ROM. */ > #endif > - > } > > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations nic_ops = { > +static struct device_operations nic_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > .init = nic_init, > .scan_bus = 0, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Indentation. > .ops_pci = &lops_pci, > }; > + > static const struct pci_driver nic_driver __pci_driver = { > .ops = &nic_ops, > .vendor = PCI_VENDOR_ID_NVIDIA, > .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, > }; > + > static const struct pci_driver nic_bridge_driver __pci_driver = { > .ops = &nic_ops, > .vendor = PCI_VENDOR_ID_NVIDIA, > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -12,70 +12,72 @@ > > static void pci_init(struct device *dev) > { > - > uint32_t dword; > #if CONFIG_PCI_64BIT_PREF_MEM == 1 > device_t pci_domain_dev; > struct resource *mem1, *mem2; > #endif > > - /* System error enable */ > dword = pci_read_config32(dev, 0x04); > - dword |= (1<<8); /* System error enable */ > - dword |= (1<<30); /* Clear possible errors */ > + dword |= (1 << 8); /* System error enable */ > + dword |= (1 << 30); /* Clear possible errors */ > pci_write_config32(dev, 0x04, dword); > > #if 0 > word = pci_read_config16(dev, 0x48); > - word |= (1<<0); /* MRL2MRM */ > - word |= (1<<2); /* MR2MRM */ > + word |= (1 << 0); /* MRL2MRM */ > + word |= (1 << 2); /* MR2MRM */ > pci_write_config16(dev, 0x48, word); > #endif > > #if 1 > dword = pci_read_config32(dev, 0x4c); > - dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ > + dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ > pci_write_config32(dev, 0x4c, dword); > #endif > > #if CONFIG_PCI_64BIT_PREF_MEM == 1 > pci_domain_dev = dev->bus->dev; > - while(pci_domain_dev) { > - if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; > + while (pci_domain_dev) { > + if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) > + break; > pci_domain_dev = pci_domain_dev->bus->dev; > } > > - if(!pci_domain_dev) return; // impossiable > - mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit > - mem2 = find_resource(pci_domain_dev, 2); // mem > - if(mem1->base > mem2->base) { > - dword = mem2->base & (0xffff0000UL); > + if (!pci_domain_dev) > + return; /* Impossible */ > + > + mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit > + mem2 = find_resource(pci_domain_dev, 2); // mem > + if (mem1->base > mem2->base) { > + dword = mem2->base & (0xffff0000UL); > printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); > } else { > - dword = mem1->base & (0xffff0000UL); > - printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); > + dword = mem1->base & (0xffff0000UL); > + printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", > + mem1->base); > } > #else > dword = dev_root.resource[1].base & (0xffff0000UL); > - printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); > + printk_debug("dev_root mem base = 0x%010Lx\n", > + dev_root.resource[1].base); > #endif > > printk_debug("[0x50] <-- 0x%08x\n", dword); > - pci_write_config32(dev, 0x50, dword); //TOM > - > + pci_write_config32(dev, 0x50, dword); /* TOM */ > } > > static struct pci_operations lops_pci = { > .set_subsystem = 0, > }; > > -static struct device_operations pci_ops = { > +static struct device_operations pci_ops = { > .read_resources = pci_bus_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_bus_enable_resources, > .init = pci_init, > .scan_bus = pci_scan_bridge, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Indentation. > .ops_pci = &lops_pci, > }; > > @@ -84,4 +86,3 @@ > .vendor = PCI_VENDOR_ID_NVIDIA, > .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, > }; > - > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -12,29 +12,26 @@ > > static void pcie_init(struct device *dev) > { > - > - /* Enable pci error detecting */ > uint32_t dword; > > - /* System error enable */ > + /* Enable PCI error detecting. */ > dword = pci_read_config32(dev, 0x04); > - dword |= (1<<8); /* System error enable */ > - dword |= (1<<30); /* Clear possible errors */ > + dword |= (1 << 8); /* System error enable */ > + dword |= (1 << 30); /* Clear possible errors */ > pci_write_config32(dev, 0x04, dword); > - > } > > static struct pci_operations lops_pci = { > .set_subsystem = 0, > }; > > -static struct device_operations pcie_ops = { > +static struct device_operations pcie_ops = { > .read_resources = pci_bus_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_bus_enable_resources, > .init = pcie_init, > .scan_bus = pci_scan_bridge, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Indentation. > .ops_pci = &lops_pci, > }; > > @@ -43,4 +40,3 @@ > .vendor = PCI_VENDOR_ID_NVIDIA, > .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, > }; > - > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -15,7 +15,7 @@ > static void pci_write_config32(device_t dev, unsigned where, unsigned value) > { > unsigned addr; > - addr = (dev>>4) | where; > + addr = (dev >> 4) | where; > outl(0x80000000 | (addr & ~3), 0xCF8); > outl(value, 0xCFC); > } > @@ -23,7 +23,7 @@ > static unsigned pci_read_config32(device_t dev, unsigned where) > { > unsigned addr; > - addr = (dev>>4) | where; > + addr = (dev >> 4) | where; > outl(0x80000000 | (addr & ~3), 0xCF8); > return inl(0xCFC); > } > @@ -33,8 +33,7 @@ > void hard_reset(void) > { > set_bios_reset(); > - /* Try rebooting through port 0xcf9 */ > - outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); > - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); > + /* Try rebooting through port 0xcf9. */ > + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); > + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); > } > - > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > #include <console/console.h> > #include <device/device.h> > #include <delay.h> > @@ -10,7 +11,6 @@ > #include <device/pci_ops.h> > #include "ck804.h" > > - > static void sata_com_reset(struct device *dev, unsigned reset) > // reset = 1 : reset > // reset = 0 : clear > @@ -23,12 +23,12 @@ > > printk_debug("base = %08x\r\n", base); > > - if(reset) { > - *(base + 4) = 0xffffffff; > - *(base + 0x44) = 0xffffffff; > + if (reset) { > + *(base + 4) = 0xffffffff; > + *(base + 0x44) = 0xffffffff; > } > > - dword = *(base +8); > + dword = *(base + 8); > dword &= ~(0xf); > dword |= reset; > > @@ -42,87 +42,89 @@ > *(base + 0x48) = dword; > #endif > > - if(reset) return; > + if (reset) > + return; > > - dword = *(base+ 0); > - printk_debug("*(base+0)=%08x\r\n",dword); > - if(dword == 0x113) { > - loop = 200000;// 2 > + dword = *(base + 0); > + printk_debug("*(base+0)=%08x\r\n", dword); > + if (dword == 0x113) { > + loop = 200000; // 2 > do { > - dword = *(base + 4); > - if((dword & 0x10000)!=0) break; > + dword = *(base + 4); > + if ((dword & 0x10000) != 0) > + break; > udelay(10); > - } while (--loop>0); > - printk_debug("loop=%d, *(base+4)=%08x\r\n",loop, dword); > + } while (--loop > 0); > + printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword); > } > > - dword = *(base+ 0x40); > - printk_debug("*(base+0x40)=%08x\r\n",dword); > - if(dword == 0x113) { > - loop = 200000;//2 > - do { > - dword = *(base + 0x44); > - if((dword & 0x10000)!=0) break; > + dword = *(base + 0x40); > + printk_debug("*(base+0x40)=%08x\r\n", dword); > + if (dword == 0x113) { > + loop = 200000; //2 > + do { > + dword = *(base + 0x44); > + if ((dword & 0x10000) != 0) > + break; > udelay(10); > - } while (--loop>0); > - printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop, dword); > + } while (--loop > 0); > + printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword); > } > } > > static void sata_init(struct device *dev) > { > - > uint32_t dword; > + struct southbridge_nvidia_ck804_config *conf; > > - struct southbridge_nvidia_ck804_config *conf; > conf = dev->chip_info; > > dword = pci_read_config32(dev, 0x50); > - /* Ensure prefetch is disabled */ > + /* Ensure prefetch is disabled. */ > dword &= ~((1 << 15) | (1 << 13)); > if (conf->sata1_enable) { > - /* Enable secondary SATA interface */ > - dword |= (1<<0); > - printk_debug("SATA S \t"); > + /* Enable secondary SATA interface. */ > + dword |= (1 << 0); > + printk_debug("SATA S \t"); > } > if (conf->sata0_enable) { > - /* Enable primary SATA interface */ > - dword |= (1<<1); > - printk_debug("SATA P \n"); > + /* Enable primary SATA interface. */ > + dword |= (1 << 1); > + printk_debug("SATA P \n"); > } > #if 0 > -// write back > - dword |= (1<<12); > - dword |= (1<<14); > + /* Write back */ > + dword |= (1 << 12); > + dword |= (1 << 14); > #endif > > #if 0 > -// ADMA > - dword |= (1<<16); > - dword |= (1<<17); > + /* ADMA */ > + dword |= (1 << 16); > + dword |= (1 << 17); > #endif > > #if 1 > -//DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. > - dword &= ~(0x1f<<24); > - dword |= (0x15<<24); > + /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ > + dword &= ~(0x1f << 24); > + dword |= (0x15 << 24); > #endif > pci_write_config32(dev, 0x50, dword); > > #if 0 > -//SLUMBER_DURING_D3. > + /* SLUMBER_DURING_D3 */ > dword = pci_read_config32(dev, 0x7c); > - dword &= ~(1<<4); > + dword &= ~(1 << 4); > pci_write_config32(dev, 0x7c, dword); > > dword = pci_read_config32(dev, 0xd0); > - dword &= ~(0xff<<24); > - dword |= (0x68<<24); > + dword &= ~(0xff << 24); > + dword |= (0x68 << 24); > pci_write_config32(dev, 0xd0, dword); > > dword = pci_read_config32(dev, 0xe0); > - dword &= ~(0xff<<24); > - dword |= (0x68<<24); > + dword &= ~(0xff << 24); > + dword |= (0x68 << 24); > pci_write_config32(dev, 0xe0, dword); > #endif > > @@ -132,11 +134,11 @@ > > #if 0 > dword = pci_read_config32(dev, 0xac); > - dword &= ~((1<<13)|(1<<14)); > - dword |= (1<<13)|(0<<14); > + dword &= ~((1 << 13) | (1 << 14)); > + dword |= (1 << 13) | (0 << 14); > pci_write_config32(dev, 0xac, dword); > > - sata_com_reset(dev, 1); // for discover some s-atapi device > + sata_com_reset(dev, 1); /* For discover some s-atapi device. */ > #endif > > } > @@ -144,17 +146,18 @@ > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > + > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations sata_ops = { > +static struct device_operations sata_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > .init = sata_init, > .scan_bus = 0, > .ops_pci = &lops_pci, > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > #include <console/console.h> > #include <device/device.h> > #include <device/pci.h> > @@ -68,6 +69,7 @@ > > return do_smbus_write_byte(res->base, device, address, val); > } > + > static struct smbus_bus_operations lops_smbus_bus = { > .recv_byte = lsmbus_recv_byte, > .send_byte = lsmbus_send_byte, > @@ -78,25 +80,26 @@ > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > + > static struct device_operations smbus_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > .init = 0, > .scan_bus = scan_static_bus, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Indentation. > .ops_pci = &lops_pci, > .ops_smbus_bus = &lops_smbus_bus, > }; > + > static const struct pci_driver smbus_driver __pci_driver = { > .ops = &smbus_ops, > .vendor = PCI_VENDOR_ID_NVIDIA, > .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, > }; > - > > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > #include <console/console.h> > #include <device/device.h> > #include <device/pci.h> > @@ -9,34 +10,41 @@ > #include <device/pci_ops.h> > #include "ck804.h" > > -static void usb1_init(struct device *dev) { > - struct southbridge_nvidia_ck804_config const * conf=dev->chip_info; > +static void usb1_init(struct device *dev) > +{ > + struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; > if (conf->usb1_hc_reset) { > - //Somehow the warm reset does not really resets the USB controller. > - //Later, during boot, when the Bus Master bit is set, the USB > - //controller trashes the memory, causing weird misbehavior. > - //Was detected on Sun Ultra40, where mptable was damaged. > - uint32_t bar0=pci_read_config32(dev,0x10); > - uint32_t* regs=(uint32_t*)(bar0&~0xfff); > - regs[2]|=1; //OHCI USB HCCommandStatus Register, HostControllerReset bit > + /* > + * Somehow the warm reset does not really reset the USB > + * controller. Later, during boot, when the Bus Master bit is > + * set, the USB controller trashes the memory, causing weird > + * misbehavior. Was detected on Sun Ultra40, where mptable > + * was damaged. > + */ > + uint32_t bar0 = pci_read_config32(dev, 0x10); > + uint32_t *regs = (uint32_t *) (bar0 & ~0xfff); > + > + /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ > + regs[2] |= 1; > } > } > > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > + > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations usb_ops = { > +static struct device_operations usb_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > .init = usb1_init, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Undo the indentation change, please. > .scan_bus = 0, > .ops_pci = &lops_pci, > }; > @@ -46,4 +54,3 @@ > .vendor = PCI_VENDOR_ID_NVIDIA, > .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, > }; > - > > Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c 2008-10-02 15:42:14 UTC (rev 3630) > +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c 2008-10-02 18:19:17 UTC (rev 3631) > @@ -2,6 +2,7 @@ > * Copyright 2004 Tyan Computer > * by yhlu(a)tyan.com > */ > + > #include <console/console.h> > #include <device/device.h> > #include <device/pci.h> > @@ -11,7 +12,6 @@ > > static void usb2_init(struct device *dev) > { > - > uint32_t dword; > dword = pci_read_config32(dev, 0xf8); > dword |= 40; > @@ -21,18 +21,19 @@ > static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) > { > pci_write_config32(dev, 0x40, > - ((device & 0xffff) << 16) | (vendor & 0xffff)); > + ((device & 0xffff) << 16) | (vendor & 0xffff)); > } > + > static struct pci_operations lops_pci = { > .set_subsystem = lpci_set_subsystem, > }; > > -static struct device_operations usb2_ops = { > +static struct device_operations usb2_ops = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > .enable_resources = pci_dev_enable_resources, > .init = usb2_init, > -// .enable = ck804_enable, > + // .enable = ck804_enable, > Undo the indentation change, please. > .scan_bus = 0, > .ops_pci = &lops_pci, > }; > > > -- http://www.hailfinger.org/

1 0

r3633 - in trunk/coreboot-v2/src/superio: smsc/lpc47b397 winbond/w83627hf
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: myles Date: 2008-10-02 21:21:30 +0200 (Thu, 02 Oct 2008) New Revision: 3633 Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c Log: Whitespace cleanup (trivial). Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h 2008-10-02 19:21:30 UTC (rev 3633) @@ -1,7 +1,7 @@ -#define LPC47B397_FDC 0 /* Floppy */ -#define LPC47B397_PP 3 /* Parallel Port */ -#define LPC47B397_SP1 4 /* Com1 */ -#define LPC47B397_SP2 5 /* Com2 */ -#define LPC47B397_KBC 7 /* Keyboard & Mouse */ -#define LPC47B397_HWM 8 /* HW Monitor */ -#define LPC47B397_RT 10 /* Runtime reg*/ +#define LPC47B397_FDC 0 /* Floppy */ +#define LPC47B397_PP 3 /* Parallel Port */ +#define LPC47B397_SP1 4 /* Com1 */ +#define LPC47B397_SP2 5 /* Com2 */ +#define LPC47B397_KBC 7 /* Keyboard & Mouse */ +#define LPC47B397_HWM 8 /* HW Monitor */ +#define LPC47B397_RT 10 /* Runtime reg*/ Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c 2008-10-02 19:21:30 UTC (rev 3633) @@ -2,9 +2,10 @@ { outb(value,iobase+offset); } + static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) { - return inb(iobase+offset); + return inb(iobase+offset); } //for GP60-GP64, GP66-GP85 @@ -13,13 +14,13 @@ static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned value) { - outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); + outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); outb(value, iobase+LPC47B397_GPIO_CNTL_DATA); } + static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index) { outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); - return inb(iobase+LPC47B397_GPIO_CNTL_DATA); + return inb(iobase+LPC47B397_GPIO_CNTL_DATA); } - Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c 2008-10-02 19:21:30 UTC (rev 3633) @@ -3,12 +3,14 @@ static inline void pnp_enter_conf_state(device_t dev) { unsigned port = dev>>8; - outb(0x55, port); + outb(0x55, port); } + static void pnp_exit_conf_state(device_t dev) { unsigned port = dev>>8; - outb(0xaa, port); + outb(0xaa, port); } + static void lpc47b397_enable_serial(device_t dev, unsigned iobase) { pnp_enter_conf_state(dev); Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2008-10-02 19:21:30 UTC (rev 3633) @@ -1,7 +1,7 @@ /* Copyright 2000 AG Electronics Ltd. */ /* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan - */ +/* Copyright 2004 Tyan + */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */ @@ -20,32 +20,32 @@ static void pnp_enter_conf_state(device_t dev) { - outb(0x55, dev->path.u.pnp.port); + outb(0x55, dev->path.u.pnp.port); } static void pnp_exit_conf_state(device_t dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.u.pnp.port); } static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) { - outb(reg, port_base); - outb(value, port_base + 1); + outb(reg, port_base); + outb(value, port_base + 1); } static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) { - outb(reg, port_base); - return inb(port_base + 1); + outb(reg, port_base); + return inb(port_base + 1); } static void enable_hwm_smbus(device_t dev) { /* enable SensorBus register access */ - uint8_t reg, value; - reg = 0xf0; - value = pnp_read_config(dev, reg); - value |= 0x01; - pnp_write_config(dev, reg, value); -} + uint8_t reg, value; + reg = 0xf0; + value = pnp_read_config(dev, reg); + value |= 0x01; + pnp_write_config(dev, reg, value); +} static void lpc47b397_init(device_t dev) @@ -57,7 +57,7 @@ } conf = dev->chip_info; switch(dev->path.u.pnp.device) { - case LPC47B397_SP1: + case LPC47B397_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -71,51 +71,51 @@ init_pc_keyboard(res0->base, res1->base, &conf->keyboard); break; } - + } void lpc47b397_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_resources(dev); #if 0 - dump_pnp_device(dev); + dump_pnp_device(dev); #endif - - pnp_exit_conf_state(dev); - -} - + + pnp_exit_conf_state(dev); + +} + void lpc47b397_pnp_enable_resources(device_t dev) -{ +{ - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); - pnp_enable_resources(dev); + pnp_enable_resources(dev); - switch(dev->path.u.pnp.device) { - case LPC47B397_HWM: - printk_debug("lpc47b397 SensorBus Register Access enabled\r\n"); + switch(dev->path.u.pnp.device) { + case LPC47B397_HWM: + printk_debug("lpc47b397 SensorBus Register Access enabled\r\n"); pnp_set_logical_device(dev); - enable_hwm_smbus(dev); - break; - } + enable_hwm_smbus(dev); + break; + } -#if 0 - dump_pnp_device(dev); +#if 0 + dump_pnp_device(dev); #endif - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } void lpc47b397_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -126,8 +126,8 @@ pnp_set_enable(dev, 0); } - pnp_exit_conf_state(dev); - + pnp_exit_conf_state(dev); + } static struct device_operations ops = { @@ -149,60 +149,60 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) { - unsigned device; - struct resource *res; + unsigned device; + struct resource *res; int result; - device = dev->path.u.i2c.device; + device = dev->path.u.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); + res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? - + result = pnp_read_index(res->base+SB_INDEX, address); // we only read it one byte one time - - return result; + + return result; } static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) -{ - unsigned device; - struct resource *res; - - device = dev->path.u.i2c.device; +{ + unsigned device; + struct resource *res; + + device = dev->path.u.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? + pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? - pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time - - return 0; + pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time + + return 0; } static struct smbus_bus_operations lops_smbus_bus = { -// .recv_byte = lsmbus_recv_byte, -// .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, +// .recv_byte = lsmbus_recv_byte, +// .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static struct device_operations ops_hwm = { - .read_resources = pnp_read_resources, - .set_resources = lpc47b397_pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, - .enable = lpc47b397_pnp_enable, - .init = lpc47b397_init, + .read_resources = pnp_read_resources, + .set_resources = lpc47b397_pnp_set_resources, + .enable_resources = lpc47b397_pnp_enable_resources, + .enable = lpc47b397_pnp_enable, + .init = lpc47b397_init, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, }, - { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, }, }; static void enable_dev(struct device *dev) Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2008-10-02 19:21:30 UTC (rev 3633) @@ -1,6 +1,6 @@ /* Copyright 2000 AG Electronics Ltd. */ /* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan +/* Copyright 2004 Tyan By LYH change from PC87360 */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */ @@ -18,27 +18,27 @@ #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.u.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.u.pnp.port); } static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) { - outb(reg, port_base); - outb(value, port_base + 1); + outb(reg, port_base); + outb(value, port_base + 1); } static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) { - outb(reg, port_base); - return inb(port_base + 1); -} + outb(reg, port_base); + return inb(port_base + 1); +} static void enable_hwm_smbus(device_t dev) { /* set the pin 91,92 as I2C bus */ @@ -56,14 +56,14 @@ get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); - pnp_write_index(dev->path.u.pnp.port,7,0x0a); + pnp_write_index(dev->path.u.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); value &= ~(3<<5); if(power_on) { value |= (1<<5); } pnp_write_config(dev, 0xE4, value); - pnp_exit_ext_func_mode(dev); + pnp_exit_ext_func_mode(dev); } static void init_hwm(unsigned long base) @@ -72,16 +72,16 @@ int i; unsigned hwm_reg_values[] = { -/* reg mask data */ - 0x40, 0xff, 0x81, /* start HWM */ - 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ - 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ - 0x4e, 0x80, 0x00, - 0x43, 0x00, 0xff, - 0x44, 0x00, 0x3f, - 0x4c, 0xbf, 0x18, - 0x4d, 0xff, 0x80 /* turn off beep */ - +/* reg mask data */ + 0x40, 0xff, 0x81, /* start HWM */ + 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ + 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ + 0x4e, 0x80, 0x00, + 0x43, 0x00, 0xff, + 0x44, 0x00, 0x3f, + 0x4c, 0xbf, 0x18, + 0x4d, 0xff, 0x80 /* turn off beep */ + }; for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) { @@ -105,7 +105,7 @@ } conf = dev->chip_info; switch(dev->path.u.pnp.device) { - case W83627HF_SP1: + case W83627HF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -118,50 +118,50 @@ res1 = find_resource(dev, PNP_IDX_IO1); init_pc_keyboard(res0->base, res1->base, &conf->keyboard); break; - case W83627HF_HWM: - res0 = find_resource(dev, PNP_IDX_IO0); + case W83627HF_HWM: + res0 = find_resource(dev, PNP_IDX_IO0); #define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); - break; - case W83627HF_ACPI: - init_acpi(dev); - break; + init_hwm(res0->base + HWM_INDEX_PORT); + break; + case W83627HF_ACPI: + init_acpi(dev); + break; } } void w83627hf_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); - -} - + pnp_exit_ext_func_mode(dev); + +} + void w83627hf_pnp_enable_resources(device_t dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_enable_resources(dev); - switch(dev->path.u.pnp.device) { +{ + pnp_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + switch(dev->path.u.pnp.device) { case W83627HF_HWM: printk_debug("w83627hf hwm smbus enabled\n"); enable_hwm_smbus(dev); break; } - pnp_exit_ext_func_mode(dev); + pnp_exit_ext_func_mode(dev); } void w83627hf_pnp_enable(device_t dev) { - if (!dev->enabled) { - pnp_enter_ext_func_mode(dev); + if (!dev->enabled) { + pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); - pnp_exit_ext_func_mode(dev); - } + pnp_exit_ext_func_mode(dev); + } } static struct device_operations ops = { @@ -173,18 +173,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, - { &ops, W83627HF_GPIO2, }, - { &ops, W83627HF_GPIO3, }, - { &ops, W83627HF_ACPI, }, - { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, + { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + // No 4 { 0,}, + { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &ops, W83627HF_GPIO2, }, + { &ops, W83627HF_GPIO3, }, + { &ops, W83627HF_ACPI, }, + { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, }; static void enable_dev(struct device *dev) Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h 2008-10-02 19:21:30 UTC (rev 3633) @@ -18,10 +18,10 @@ #define W83627HF_GPEVR 0xf2 #define W83627HF_GPCFG2 0xf3 #define W83627HF_EXTCFG 0xf4 -#define W83627HF_IOEXT1A 0xf5 -#define W83627HF_IOEXT1B 0xf6 -#define W83627HF_IOEXT2A 0xf7 -#define W83627HF_IOEXT2B 0xf8 +#define W83627HF_IOEXT1A 0xf5 +#define W83627HF_IOEXT1B 0xf6 +#define W83627HF_IOEXT2A 0xf7 +#define W83627HF_IOEXT2B 0xf8 #define W83627HF_GPDO_0 0x00 #define W83627HF_GPDI_0 0x01 @@ -40,26 +40,26 @@ #define W83627HF_GPDO_5 0x0e #define W83627HF_GPDI_5 0x0f #define W83627HF_GPDO_6 0x10 -#define W83627HF_GPDO_7A 0x11 -#define W83627HF_GPDO_7B 0x12 -#define W83627HF_GPDO_7C 0x13 -#define W83627HF_GPDO_7D 0x14 -#define W83627HF_GPDI_7A 0x15 -#define W83627HF_GPDI_7B 0x16 -#define W83627HF_GPDI_7C 0x17 -#define W83627HF_GPDI_7D 0x18 +#define W83627HF_GPDO_7A 0x11 +#define W83627HF_GPDO_7B 0x12 +#define W83627HF_GPDO_7C 0x13 +#define W83627HF_GPDO_7D 0x14 +#define W83627HF_GPDI_7A 0x15 +#define W83627HF_GPDI_7B 0x16 +#define W83627HF_GPDI_7C 0x17 +#define W83627HF_GPDI_7D 0x18 #define W83627HF_XIOCNF 0xf0 -#define W83627HF_XIOBA1H 0xf1 -#define W83627HF_XIOBA1L 0xf2 +#define W83627HF_XIOBA1H 0xf1 +#define W83627HF_XIOBA1L 0xf2 #define W83627HF_XIOSIZE1 0xf3 -#define W83627HF_XIOBA2H 0xf4 -#define W83627HF_XIOBA2L 0xf5 +#define W83627HF_XIOBA2H 0xf4 +#define W83627HF_XIOBA2L 0xf5 #define W83627HF_XIOSIZE2 0xf6 #define W83627HF_XMEMCNF1 0xf7 #define W83627HF_XMEMCNF2 0xf8 -#define W83627HF_XMEMBAH 0xf9 -#define W83627HF_XMEMBAL 0xfa +#define W83627HF_XMEMBAH 0xf9 +#define W83627HF_XMEMBAL 0xfa #define W83627HF_XMEMSIZE 0xfb #define W83627HF_XIRQMAP1 0xfc #define W83627HF_XIRQMAP2 0xfd Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c 2008-10-02 19:20:22 UTC (rev 3632) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c 2008-10-02 19:21:30 UTC (rev 3633) @@ -1,17 +1,19 @@ #include <arch/romcc_io.h> #include "w83627hf.h" -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(device_t dev) { unsigned port = dev>>8; - outb(0x87, port); - outb(0x87, port); + outb(0x87, port); + outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) + +static void pnp_exit_ext_func_mode(device_t dev) { unsigned port = dev>>8; - outb(0xaa, port); + outb(0xaa, port); } + static void w83627hf_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev);

1 0

r3632 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: myles Date: 2008-10-02 21:20:22 +0200 (Thu, 02 Oct 2008) New Revision: 3632 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl Log: Whitespace cleanup (trivial). Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2008-10-02 19:20:22 UTC (rev 3632) @@ -19,13 +19,13 @@ if HAVE_ACPI_TABLES object amdk8_acpi.o - makerule ssdt.c - depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" - action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" - action "mv ssdt.hex ssdt.c" - end - object ./ssdt.o + makerule ssdt.c + depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" + action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" + action "mv ssdt.hex ssdt.c" + end + object ./ssdt.o end Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -49,133 +49,131 @@ unsigned long acpi_create_madt_lapics(unsigned long current) { - device_t cpu; - int cpu_index = 0; + device_t cpu; + int cpu_index = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { - continue; - } - if (!cpu->enabled) { - continue; - } - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id); - cpu_index++; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id); + cpu_index++; - } + } - return current; + return current; } unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) { - device_t cpu; - int cpu_index = 0; + device_t cpu; + int cpu_index = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { - continue; - } - if (!cpu->enabled) { - continue; - } - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); - cpu_index++; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); + cpu_index++; - } + } - return current; + return current; } + unsigned long acpi_create_srat_lapics(unsigned long current) { - device_t cpu; - int cpu_index = 0; + device_t cpu; + int cpu_index = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { - continue; - } - if (!cpu->enabled) { - continue; - } - printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); - cpu_index++; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); + cpu_index++; - } + } - return current; + return current; } - - static unsigned long resk(uint64_t value) { - unsigned long resultk; - if (value < (1ULL << 42)) { - resultk = value >> 10; - } - else { - resultk = 0xffffffff; - } - return resultk; + unsigned long resultk; + if (value < (1ULL << 42)) { + resultk = value >> 10; + } + else { + resultk = 0xffffffff; + } + return resultk; } - struct acpi_srat_mem_state { - unsigned long current; + unsigned long current; }; void set_srat_mem(void *gp, struct device *dev, struct resource *res) { - struct acpi_srat_mem_state *state = gp; - unsigned long basek, sizek; - basek = resk(res->base); - sizek = resk(res->size); + struct acpi_srat_mem_state *state = gp; + unsigned long basek, sizek; + basek = resk(res->base); + sizek = resk(res->size); - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", - dev_path(dev), res->index, basek, sizek); - /* - 0-640K must be on node 0 - next range is from 1M--- - So will cut off before 1M in the mem range - */ - if((basek+sizek)<1024) return; + printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", + dev_path(dev), res->index, basek, sizek); + /* + 0-640K must be on node 0 + next range is from 1M--- + So will cut off before 1M in the mem range + */ + if((basek+sizek)<1024) return; - if(basek<1024) { - sizek -= 1024 - basek; - basek = 1024; - } + if(basek<1024) { + sizek -= 1024 - basek; + basek = 1024; + } - state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV + state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV } unsigned long acpi_fill_srat(unsigned long current) { - struct acpi_srat_mem_state srat_mem_state; + struct acpi_srat_mem_state srat_mem_state; - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); - /* create all subteble for memory range */ + /* create all subteble for memory range */ - /* 0-640K must be on node 0 */ - current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable -#if 1 - srat_mem_state.current = current; - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - set_srat_mem, &srat_mem_state); + /* 0-640K must be on node 0 */ + current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable - current = srat_mem_state.current; -#endif - return current; + srat_mem_state.current = current; + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + set_srat_mem, &srat_mem_state); + + current = srat_mem_state.current; + + return current; } @@ -184,7 +182,7 @@ /* need to find out the node num at first */ /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - + /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ static uint8_t hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, 1, 0, 2, 1, 3, 2, 4, 3, @@ -192,7 +190,7 @@ 2, 1, 1, 0, 2, 1, 3, 2, 2, 3, 1, 2, 0, 1, 1, 2, 3, 2, 2, 1, 1, 0, 2, 1, - 3, 4, 2, 3, 1, 2, 0, 1, + 3, 4, 2, 3, 1, 2, 0, 1, 4, 4, 3, 2, 2, 1, 1, 0 }; // uint8_t outer_node[8]; @@ -208,10 +206,10 @@ #if 0 for(i=0;i<sysconf.hc_possible_num;i++) { if((sysconf.pci1234[i]&1) !=1 ) continue; - outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node + outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node } #endif - + for(i=0;i<nodes;i++) { for(j=0;j<nodes; j++) { if(i==j) { p[i*nodes+j] = 10; } @@ -234,7 +232,7 @@ } } p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10; -#else +#else p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10; #endif @@ -243,9 +241,9 @@ } } - current += 8+nodes*nodes; + current += 8+nodes*nodes; - return current; + return current; } @@ -255,10 +253,10 @@ // moved from mb acpi_tables.c static void int_to_stream(uint32_t val, uint8_t *dest) { - int i; - for(i=0;i<4;i++) { - *(dest+i) = (val >> (8*i)) & 0xff; - } + int i; + for(i=0;i<4;i++) { + *(dest+i) = (val >> (8*i)) & 0xff; + } } @@ -266,60 +264,60 @@ void update_ssdt(void *ssdt) { - uint8_t *BUSN; - uint8_t *MMIO; - uint8_t *PCIO; - uint8_t *SBLK; - uint8_t *TOM1; - uint8_t *SBDN; - uint8_t *HCLK; - uint8_t *HCDN; + uint8_t *BUSN; + uint8_t *MMIO; + uint8_t *PCIO; + uint8_t *SBLK; + uint8_t *TOM1; + uint8_t *SBDN; + uint8_t *HCLK; + uint8_t *HCDN; uint8_t *CBST; - int i; - device_t dev; - uint32_t dword; - msr_t msr; + int i; + device_t dev; + uint32_t dword; + msr_t msr; - BUSN = ssdt+0x3a; //+5 will be next BUSN - MMIO = ssdt+0x57; //+5 will be next MMIO - PCIO = ssdt+0xaf; //+5 will be next PCIO - SBLK = ssdt+0xdc; // one byte - TOM1 = ssdt+0xe3; // - SBDN = ssdt+0xed;// - HCLK = ssdt+0xfa; //+5 will be next HCLK - HCDN = ssdt+0x12a; //+5 will be next HCDN + BUSN = ssdt+0x3a; //+5 will be next BUSN + MMIO = ssdt+0x57; //+5 will be next MMIO + PCIO = ssdt+0xaf; //+5 will be next PCIO + SBLK = ssdt+0xdc; // one byte + TOM1 = ssdt+0xe3; // + SBDN = ssdt+0xed; // + HCLK = ssdt+0xfa; //+5 will be next HCLK + HCDN = ssdt+0x12a; //+5 will be next HCDN CBST = ssdt+0x157; // - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - for(i=0;i<4;i++) { - dword = pci_read_config32(dev, 0xe0+i*4); - int_to_stream(dword, BUSN+i*5); - } - for(i=0;i<0x10;i++) { - dword = pci_read_config32(dev, 0x80+i*4); - int_to_stream(dword, MMIO+i*5); - } - for(i=0;i<0x08;i++) { - dword = pci_read_config32(dev, 0xc0+i*4); - int_to_stream(dword, PCIO+i*5); - } + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + for(i=0;i<4;i++) { + dword = pci_read_config32(dev, 0xe0+i*4); + int_to_stream(dword, BUSN+i*5); + } + for(i=0;i<0x10;i++) { + dword = pci_read_config32(dev, 0x80+i*4); + int_to_stream(dword, MMIO+i*5); + } + for(i=0;i<0x08;i++) { + dword = pci_read_config32(dev, 0xc0+i*4); + int_to_stream(dword, PCIO+i*5); + } - *SBLK = (uint8_t)(sysconf.sblk); + *SBLK = (uint8_t)(sysconf.sblk); - msr = rdmsr(TOP_MEM); - int_to_stream(msr.lo, TOM1); + msr = rdmsr(TOP_MEM); + int_to_stream(msr.lo, TOM1); - for(i=0;i<sysconf.hc_possible_num;i++) { - int_to_stream(sysconf.pci1234[i], HCLK + i*5); - int_to_stream(sysconf.hcdn[i], HCDN + i*5); - } - for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 - int_to_stream(0x00000000, HCLK + i*5); - int_to_stream(0x20202020, HCDN + i*5); - } + for(i=0;i<sysconf.hc_possible_num;i++) { + int_to_stream(sysconf.pci1234[i], HCLK + i*5); + int_to_stream(sysconf.hcdn[i], HCDN + i*5); + } + for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + int_to_stream(0x00000000, HCLK + i*5); + int_to_stream(0x20202020, HCDN + i*5); + } - int_to_stream(sysconf.sbdn, SBDN); + int_to_stream(sysconf.sbdn, SBDN); if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 *CBST = (uint8_t) (0x0f); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h 2008-10-02 19:20:22 UTC (rev 3632) @@ -461,48 +461,48 @@ //struct definitions struct dimm_size { - uint8_t per_rank; // it is rows + col + bank_lines + data lines */ - uint8_t rows; - uint8_t col; - uint8_t bank; //1, 2, 3 mean 2, 4, 8 - uint8_t rank; + uint8_t per_rank; // it is rows + col + bank_lines + data lines */ + uint8_t rows; + uint8_t col; + uint8_t bank; //1, 2, 3 mean 2, 4, 8 + uint8_t rank; } __attribute__((packed)); struct mem_info { // pernode - uint32_t dimm_mask; - struct dimm_size sz[DIMM_SOCKETS]; - uint32_t x4_mask; - uint32_t x16_mask; + uint32_t dimm_mask; + struct dimm_size sz[DIMM_SOCKETS]; + uint32_t x4_mask; + uint32_t x16_mask; uint32_t single_rank_mask; - uint32_t page_1k_mask; -// uint32_t ecc_mask; -// uint32_t registered_mask; - uint8_t is_opteron; - uint8_t is_registered; - uint8_t is_ecc; - uint8_t is_Width128; + uint32_t page_1k_mask; +// uint32_t ecc_mask; +// uint32_t registered_mask; + uint8_t is_opteron; + uint8_t is_registered; + uint8_t is_ecc; + uint8_t is_Width128; uint8_t is_64MuxMode; - uint8_t memclk_set; // we need to use this to retrieve the mem param + uint8_t memclk_set; // we need to use this to retrieve the mem param uint8_t rsv[2]; } __attribute__((packed)); struct link_pair_st { - device_t udev; - uint32_t upos; - uint32_t uoffs; - device_t dev; - uint32_t pos; - uint32_t offs; + device_t udev; + uint32_t upos; + uint32_t uoffs; + device_t dev; + uint32_t pos; + uint32_t offs; } __attribute__((packed)); struct sys_info { - uint8_t ctrl_present[NODE_NUMS]; - struct mem_info meminfo[NODE_NUMS]; + uint8_t ctrl_present[NODE_NUMS]; + struct mem_info meminfo[NODE_NUMS]; struct mem_controller ctrl[NODE_NUMS]; uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail - uint32_t tom_k; - uint32_t tom2_k; + uint32_t tom_k; + uint32_t tom2_k; uint32_t mem_base[NODE_NUMS]; uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx @@ -511,9 +511,9 @@ uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9 uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8 uint32_t nodes; - struct link_pair_st link_pair[16];// enough? only in_conherent - uint32_t link_pair_num; - uint32_t ht_c_num; + struct link_pair_st link_pair[16];// enough? only in_conherent + uint32_t link_pair_num; + uint32_t ht_c_num; uint32_t sbdn; uint32_t sblk; uint32_t sbbusn; @@ -526,38 +526,38 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) { - int i; - uint32_t mask = 0; + int i; + uint32_t mask = 0; unsigned needs_reset = 0; if(sysinfo->nodes == 1) return; // in case only one cpu installed - for(i=1; i<sysinfo->nodes; i++) { - /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->mem_trained[i]==0x00) continue; + for(i=1; i<sysinfo->nodes; i++) { + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->mem_trained[i]==0x00) continue; - mask |= (1<<i); + mask |= (1<<i); - } + } - i = 1; - while(1) { + i = 1; + while(1) { if(mask & (1<<i)) { if((sysinfo->mem_trained[i])!=0x80) { mask &= ~(1<<i); } } - if(!mask) break; + if(!mask) break; #if 0 /* cpu_relax */ __asm__ __volatile__("rep;nop": : :"memory"); #endif - i++; - i%=sysinfo->nodes; + i++; + i%=sysinfo->nodes; } for(i=0; i<sysinfo->nodes; i++) { @@ -566,7 +566,7 @@ #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif - switch(sysinfo->mem_trained[i]) { + switch(sysinfo->mem_trained[i]) { case 0: //don't need train case 1: //trained break; Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -4,53 +4,53 @@ /* bit [10,8] are dev func, bit[1,0] are dev index */ static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) { - uint32_t dword; + uint32_t dword; - pci_write_config32(dev, index_reg, index); + pci_write_config32(dev, index_reg, index); - dword = pci_read_config32(dev, index_reg+0x4); + dword = pci_read_config32(dev, index_reg+0x4); - return dword; + return dword; } static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) { - pci_write_config32(dev, index_reg, index); + pci_write_config32(dev, index_reg, index); - pci_write_config32(dev, index_reg + 0x4, data); + pci_write_config32(dev, index_reg + 0x4, data); } static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index) { - uint32_t dword; + uint32_t dword; - index &= ~(1<<30); - pci_write_config32(dev, index_reg, index); + index &= ~(1<<30); + pci_write_config32(dev, index_reg, index); - do { - dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); + do { + dword = pci_read_config32(dev, index_reg); + } while (!(dword & (1<<31))); - dword = pci_read_config32(dev, index_reg+0x4); + dword = pci_read_config32(dev, index_reg+0x4); - return dword; + return dword; } static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) { - uint32_t dword; + uint32_t dword; - pci_write_config32(dev, index_reg + 0x4, data); + pci_write_config32(dev, index_reg + 0x4, data); - index |= (1<<30); - pci_write_config32(dev, index_reg, index); - do { - dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); + index |= (1<<30); + pci_write_config32(dev, index_reg, index); + do { + dword = pci_read_config32(dev, index_reg); + } while (!(dword & (1<<31))); } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -1,5 +1,5 @@ -/* coherent hypertransport initialization for AMD64 - * +/* coherent hypertransport initialization for AMD64 + * * written by Stefan Reinauer <stepan(a)openbios.org> * (c) 2003-2004 by SuSE Linux AG * @@ -16,51 +16,51 @@ * nodes : 1 2 4 6 8 * org. : 1x1 2x1 2x2 2x3 2x4 Ladder: - CPU7-------------CPU6 - | | + CPU7-------------CPU6 | | - | | - | | - | | - | | - CPU5-------------CPU4 - | | - | | - | | - | | - | | - | | - CPU3-------------CPU2 - | | - | | | | | | - | | - | | - CPU1-------------CPU0 + | | + | | + | | + CPU5-------------CPU4 + | | + | | + | | + | | + | | + | | + CPU3-------------CPU2 + | | + | | + | | + | | + | | + | | + CPU1-------------CPU0 CROSS_BAR_47_56: - CPU7-------------CPU6 - | \____ ___/ | + CPU7-------------CPU6 + | \____ ___/ | | \ / | - | \/ | - | /\ | - | / \ | - | ____/ \___ | - CPU5 CPU4 - | | - | | - | | - | | - | | - | | - CPU3-------------CPU2 - | | - | | + | \/ | + | /\ | + | / \ | + | ____/ \___ | + CPU5 CPU4 | | | | - | | - | | - CPU1-------------CPU0 + | | + | | + | | + | | + CPU3-------------CPU2 + | | + | | + | | + | | + | | + | | + CPU1-------------CPU0 */ #include <device/pci_def.h> @@ -105,15 +105,15 @@ #endif #ifndef ENABLE_APIC_EXT_ID - #define ENABLE_APIC_EXT_ID 0 + #define ENABLE_APIC_EXT_ID 0 #endif -static inline void print_linkn (const char *strval, uint8_t byteval) +static inline void print_linkn (const char *strval, uint8_t byteval) { #if 1 #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%02x\r\n", strval, byteval); + printk_debug("%s%02x\r\n", strval, byteval); #else print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n"); #endif @@ -126,7 +126,7 @@ * they don't make sense if only one cpu is available */ - /* Hypetransport Transaction Control Register + /* Hypetransport Transaction Control Register * F0:0x68 * [ 0: 0] Disable read byte probe * 0 = Probes issues @@ -151,7 +151,7 @@ val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | - HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | + HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); @@ -159,16 +159,16 @@ } -static void enable_apic_ext_id(u8 node) +static void enable_apic_ext_id(u8 node) { #if ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?" u32 val; - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); + val = pci_read_config32(NODE_HT(node), 0x68); + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); + pci_write_config32(NODE_HT(node), 0x68, val); #endif } @@ -228,7 +228,7 @@ if (ldt&0x08) return 0x40; if (ldt&0x04) return 0x20; if (ldt&0x02) return 0x00; - + /* we should never get here */ print_spew("Unknown Link\n"); return 0; @@ -253,7 +253,7 @@ val=pci_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ - val |= node; /* new node */ + val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); print_spew(" done.\r\n"); @@ -263,12 +263,12 @@ { /* See if we have a valid connection to dest */ u32 val; - + /* Verify that the coherent hypertransport link is * established and actually working by reading the * remode node's vendor/device id */ - val = pci_read_config32(NODE_HT(dest),0); + val = pci_read_config32(NODE_HT(dest),0); if(val != 0x11001022) return 0; @@ -287,7 +287,7 @@ #if K8_HT_FREQ_1G_SUPPORT == 1 #if K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) - #endif + #endif { return freq_cap; } @@ -299,7 +299,7 @@ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { freq_cap &= ~(1 << HT_FREQ_1000Mhz); } - + return freq_cap; } @@ -353,10 +353,10 @@ ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - + /* See if I am changing node1's width */ old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1); - old_width &= 0x77; + old_width &= 0x77; needs_reset |= old_width != width; /* Set node1's widths */ @@ -378,27 +378,27 @@ static uint8_t get_linkn_first(uint8_t byte) { - if(byte & 0x02) { byte = 0; } - else if(byte & 0x04) { byte = 1; } - else if(byte & 0x08) { byte = 2; } - return byte; + if(byte & 0x02) { byte = 0; } + else if(byte & 0x04) { byte = 1; } + else if(byte & 0x08) { byte = 2; } + return byte; } static uint8_t get_linkn_last(uint8_t byte) { - if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } - if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } - if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } - return byte>>4; + if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } + if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } + if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } + return byte>>4; } static uint8_t get_linkn_last_count(uint8_t byte) { - byte &= 0x0f; - if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } - if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } - if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } - return byte>>4; + byte &= 0x0f; + if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } + if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } + if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } + return byte>>4; } static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/ @@ -406,13 +406,13 @@ uint8_t linkn; uint32_t val; val = 1; - for(linkn = 0; linkn<3; linkn++) { - uint8_t regpos; + for(linkn = 0; linkn<3; linkn++) { + uint8_t regpos; uint32_t reg; regpos = 0x98 + 0x20 * linkn; reg = pci_read_config32(NODE_HT(source), regpos); if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/ - val |= 1<<(linkn+1); + val |= 1<<(linkn+1); } val <<= 16; val |= 0x0101; @@ -426,17 +426,17 @@ val = 1<<(linkn+1); val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/ - if(((source &1)!=(dest &1)) + if(((source &1)!=(dest &1)) #if CROSS_BAR_47_56 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here - //(6,5) (7,4) should be here + //(6,5) (7,4) should be here #endif ){ val |= (1<<16); } else { /*for CROSS_BAR_47_56 47, 56, should be here too - and for 47, 56, 57, 75, 46, 64 we need to substract another link to - 6, 7, 6, 6, 7, 7 + and for 47, 56, 57, 75, 46, 64 we need to substract another link to + 6, 7, 6, 6, 7, 7 */ val_s = get_row(temp, source); val |= ((val_s>>16) - (1<<(linkn+1)))<<16; @@ -454,26 +454,26 @@ } static void opt_broadcast_rt_group(const u8 *conn, int num) { - int i; + int i; - for(i=0; i<num; i+=3) { - opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); - } + for(i=0; i<num; i+=3) { + opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); + } } static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) { - uint32_t val; - val = get_row(source, dest); - val += link_connection(source, kickout)<<16; - fill_row(source, dest, val); -} - + uint32_t val; + val = get_row(source, dest); + val += link_connection(source, kickout)<<16; + fill_row(source, dest, val); +} + static void opt_broadcast_rt_plus_group(const u8 *conn, int num) { - int i; - - for(i=0; i<num; i+=3) { - opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); - } -} + int i; + + for(i=0; i<num; i+=3) { + opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); + } +} #endif static void setup_row_direct(u8 source, u8 dest, u8 linkn){ @@ -497,8 +497,8 @@ static void setup_remote_node(u8 node) { - static const uint8_t pci_reg[] = { - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, + static const uint8_t pci_reg[] = { + 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, @@ -535,7 +535,7 @@ /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */ uint32_t val_s; uint32_t val; -#if !CROSS_BAR_47_56 +#if !CROSS_BAR_47_56 u8 gateway; u8 diff; if(source<dest) { @@ -546,11 +546,11 @@ #endif val_s = get_row(temp, source); val = get_row(temp, gateway); - + val &= 0xffff; val_s >>= 16; val_s &= 0xfe; - + #if !CROSS_BAR_47_56 diff = ((source&1)!=(dest &1)); #endif @@ -568,32 +568,32 @@ if(source<dest) { val_s-=link_connection(temp, source-2); /* -down*/ } else { -#if CROSS_BAR_47_56 - #if 0 +#if CROSS_BAR_47_56 + #if 0 if(source==7) { val_s-=link_connection(temp, 6); // for 7,2 via 5 } else if (source==6){ val_s-=link_connection(temp, 7); // for 6,3 via 4 - } else + } else #endif if (source < gateway) { // for 5, 4 via 7 val_s-=link_connection(temp, source-2); } else -#endif +#endif val_s-=link_connection(temp, source+2); /* -up*/ } } #endif val &= 0xff; val |= (val_s<<8); - } + } if(diff) { /* cross rung?*/ val |= (1<<16); } else { val_s = get_row(temp, source); - val |= ((val_s>>16) - link_connection(temp, gateway))<<16; + val |= ((val_s>>16) - link_connection(temp, gateway))<<16; } fill_row(temp, dest, val); @@ -602,15 +602,15 @@ #if !CROSS_BAR_47_56 static void setup_row_indirect(u8 source, u8 dest) -{ +{ setup_row_indirect_x(source, source, dest); } -#else +#else static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff) { setup_row_indirect_x(source, source, dest, gateway, diff); } -#endif +#endif static void setup_row_indirect_group(const u8 *conn, int num) { @@ -674,9 +674,9 @@ needs_reset = optimize_connection( NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])), NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) ); - } + } return needs_reset; -} +} #endif #if CONFIG_MAX_PHYSICAL_CPUS > 1 @@ -688,7 +688,7 @@ nodes = 2; setup_row_local(0, 0); /* it will update the broadcast RT*/ - + val = get_row(0,0); byte = (val>>16) & 0xfe; if(byte<0x2) { /* no coherent connection so get out.*/ @@ -705,7 +705,7 @@ print_linkn("(0,1) link=", byte); setup_row_direct(0,1, byte); setup_temp_row(0, 1); - + verify_connection(7); /* We found 2 nodes so far */ @@ -715,7 +715,7 @@ setup_row_local(7,1); setup_remote_row_direct(1, 0, byte); -#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) val = get_row(7,1); byte = (val>>16) & 0xfe; byte = get_linkn_last_count(byte); @@ -730,18 +730,18 @@ print_linkn("\t-->(0,1) link=", byte); setup_row_direct(0,1, byte); setup_temp_row(0, 1); - + verify_connection(7); - + /* We found 2 nodes so far */ val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on node7 to node0*/ - print_linkn("\t-->(1,0) link=", byte); + print_linkn("\t-->(1,0) link=", byte); setup_row_local(7,1); setup_remote_row_direct(1, 0, byte); } #endif - + setup_remote_node(1); /* Setup the regs on the remote node */ rename_temp_node(1); /* Rename Node 7 to Node 1 */ enable_routing(1); /* Enable routing on Node 1 */ @@ -775,7 +775,7 @@ } byte &= 3; /* bit [3,2] is count-1*/ - print_linkn("(0,2) link=", byte); + print_linkn("(0,2) link=", byte); setup_row_direct(0, 2, byte); /*(0,2) direct link done*/ /* We found 3 nodes so far. Now setup a temporary @@ -786,7 +786,7 @@ val = get_row(1,1); byte = ((val>>16) & 0xfe) - link_connection(1,0); byte = get_linkn_first(byte); - print_linkn("(1,3) link=", byte); + print_linkn("(1,3) link=", byte); setup_row_direct(1,3,byte); /* (1, 3) direct link done*/ /* We found 4 nodes so far. Now setup all nodes for 4p */ @@ -795,7 +795,7 @@ static const u8 conn4_1[] = { 0,3, 1,2, - }; + }; #else static const u8 conn4_1[] = { 0,3,2,1, @@ -809,7 +809,7 @@ verify_connection(7); val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 0*/ - print_linkn("(2,0) link=", byte); + print_linkn("(2,0) link=", byte); setup_row_local(7,2); setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */ @@ -824,7 +824,7 @@ val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 1*/ - print_linkn("(3,1) link=", byte); + print_linkn("(3,1) link=", byte); setup_row_local(7,3); setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */ @@ -835,7 +835,7 @@ byte = ((val>>16) & 0xfe) - link_connection(2,0); byte = get_linkn_last_count(byte); print_linkn("(2,3) link=", byte & 3); - + setup_row_direct(2,3, byte & 0x3); setup_temp_row(0,2); setup_temp_row(2,3); @@ -849,68 +849,68 @@ val = get_row(2,2); byte = ((val>>16) & 0xfe) - link_connection(2,0); byte = get_linkn_first(byte); - print_linkn("\t-->(2,3) link=", byte); + print_linkn("\t-->(2,3) link=", byte); setup_row_direct(2,3,byte); setup_temp_row(2,3); verify_connection(7); /* to 3*/ } - } + } #endif val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 2*/ - print_linkn("(3,2) link=", byte); + print_linkn("(3,2) link=", byte); setup_remote_row_direct(3,2, byte); #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) /* set link from 3 to 5 before enable it*/ - val = get_row(7,3); - byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); - byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ - byte &= 3; /*bit [3,2] is count-2*/ - print_linkn("(3,5) link=", byte); - setup_remote_row_direct(3, 5, byte); + val = get_row(7,3); + byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); + byte = get_linkn_last_count(byte); + if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ + byte &= 3; /*bit [3,2] is count-2*/ + print_linkn("(3,5) link=", byte); + setup_remote_row_direct(3, 5, byte); } - - val = get_row(2,2); - byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); - byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ - byte &= 3; /* bit [3,2] is count-2*/ - print_linkn("(2,4) link=", byte); - setup_row_direct(2, 4, byte); - } + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); + byte = get_linkn_last_count(byte); + + if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ + byte &= 3; /* bit [3,2] is count-2*/ + print_linkn("(2,4) link=", byte); + setup_row_direct(2, 4, byte); + } #endif //Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3 #if !CROSS_BAR_47_56 - static const u8 conn4_3[] = { - 3,0, - }; + static const u8 conn4_3[] = { + 3,0, + }; #else - static const u8 conn4_3[] = { - 3,0,1,1, - }; + static const u8 conn4_3[] = { + 3,0,1,1, + }; #endif - setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); /* ready to enable RT for Node 3 */ rename_temp_node(3); enable_routing(3); /* enable routing on node 3 (temp.) */ // beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2 -#if !CROSS_BAR_47_56 - static const u8 conn4_2[] = { - 2,1, - }; -#else - static const u8 conn4_2[] = { - 2,1,0,1, - }; -#endif - setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); +#if !CROSS_BAR_47_56 + static const u8 conn4_2[] = { + 2,1, + }; +#else + static const u8 conn4_2[] = { + 2,1,0,1, + }; +#endif + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); #if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -936,27 +936,27 @@ nodes=6; /* Setup and check temporary connection from Node 0 to Node 4 through 2*/ - val = get_row(2,2); - byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); - byte = get_linkn_last_count(byte); + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); + byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ - nodes = 4; - return nodes; - } + if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ + nodes = 4; + return nodes; + } /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/ - /* set link from 3 to 5 before enable it*/ - val = get_row(3,3); - byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); - byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ - nodes = 4; - return nodes; - } - + /* set link from 3 to 5 before enable it*/ + val = get_row(3,3); + byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); + byte = get_linkn_last_count(byte); + if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ + nodes = 4; + return nodes; + } + /* We found 6 nodes so far. Now setup all nodes for 6p */ -#warning "FIXME we need to find out the correct gateway for 6p" +#warning "FIXME we need to find out the correct gateway for 6p" static const u8 conn6_1[] = { #if !CROSS_BAR_47_56 0, 4, @@ -973,22 +973,22 @@ 2, 5, 3, 0, 3, 4, 2, 0, #endif - }; + }; setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); - + for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /*get default link on 7 to 2*/ - print_linkn("(4,2) link=", byte); - + print_linkn("(4,2) link=", byte); + setup_row_local(7,4); setup_remote_row_direct(4, 2, byte); setup_remote_node(4); /* Setup the regs on the remote node */ - + /* Set indirect connection to 0, to 3 */ //we only need to set 4,0 here static const u8 conn6_2[] = { @@ -997,10 +997,10 @@ #else 4, 0, 2, 0, #endif - }; - + }; + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); - + rename_temp_node(4); enable_routing(4); @@ -1012,18 +1012,18 @@ val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 3*/ - print_linkn("(5,3) link=", byte); + print_linkn("(5,3) link=", byte); setup_row_local(7,5); setup_remote_row_direct(5, 3, byte); setup_remote_node(5); /* Setup the regs on the remote node */ - + #if !CROSS_BAR_47_56 /* We need to init link between 4, and 5 direct link */ val = get_row(4,4); byte = ((val>>16) & 0xfe) - link_connection(4,2); byte = get_linkn_last_count(byte); print_linkn("(4,5) link=", byte & 3); - + setup_row_direct(4,5, byte & 0x3); setup_temp_row(0,2); setup_temp_row(2,4); @@ -1032,7 +1032,7 @@ #if CONFIG_MAX_PHYSICAL_CPUS > 6 /* We need to find out which link is to node5 */ - + if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ val = get_row(7,5); if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ @@ -1044,37 +1044,37 @@ setup_temp_row(4,5); verify_connection(7); /* to 5*/ } - } + } #endif val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ - print_linkn("(5,4) link=", byte); + print_linkn("(5,4) link=", byte); setup_remote_row_direct(5,4, byte); - + //init 5, 7 here - val = get_row(7,5); - byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); - byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ - byte &= 3; /*bit [3,2] is count-2*/ - print_linkn("(5,7) link=", byte); - setup_remote_row_direct(5, 7, byte); + val = get_row(7,5); + byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); + byte = get_linkn_last_count(byte); + if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ + byte &= 3; /*bit [3,2] is count-2*/ + print_linkn("(5,7) link=", byte); + setup_remote_row_direct(5, 7, byte); } - + //init 4,6 here - val = get_row(4,4); - byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); - byte = get_linkn_last_count(byte); + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); + byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ - byte &= 3; /* bit [3,2] is count-2*/ - print_linkn("(4,6) link=", byte); - setup_row_direct(4, 6, byte); - } - -#endif - + if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ + byte &= 3; /* bit [3,2] is count-2*/ + print_linkn("(4,6) link=", byte); + setup_row_direct(4, 6, byte); + } + +#endif + //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */ static const u8 conn6_3[] = { @@ -1083,8 +1083,8 @@ #else 5, 0, 3, 0, #endif - }; - + }; + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3)); /* ready to enable RT for 5 */ @@ -1095,27 +1095,27 @@ #if !CROSS_BAR_47_56 4, 1, 4, 3, - + 5, 2, 5, 1, - + #else 4, 1, 2, 0, 4, 3, 2, 0, 4, 5, 2, 0, - + 5, 2, 3, 0, 5, 1, 3, 0, 5, 4, 3, 0, - + #endif - }; - + }; + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); #if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) - * It will be done by clear_dead_links + * It will be done by clear_dead_links */ for(byte=0; byte<4; byte++) { clear_temp_row(byte); @@ -1140,18 +1140,18 @@ /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */ val = get_row(4,4); -#if CROSS_BAR_47_56 +#if CROSS_BAR_47_56 byte = ((val>>16) & 0xfe) - link_connection(4,2); #else byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); - byte = get_linkn_last_count(byte); /* Max link to 6*/ - if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ - nodes = 6; - return nodes; - } + byte = get_linkn_last_count(byte); /* Max link to 6*/ + if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ + nodes = 6; + return nodes; + } #endif -#if CROSS_BAR_47_56 +#if CROSS_BAR_47_56 byte = get_linkn_last_count(byte); /* Max link to 6*/ if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/ nodes = 6; @@ -1169,13 +1169,13 @@ #if !CROSS_BAR_47_56 /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/ - val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); - byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ - nodes = 6; - return nodes; - } + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); + byte = get_linkn_last_count(byte); + if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ + nodes = 6; + return nodes; + } #endif /* We found 8 nodes so far. Now setup all nodes for 8p */ @@ -1212,12 +1212,12 @@ val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ print_linkn("(6,4) link=", byte); - + setup_row_local(7,6); setup_remote_row_direct(6, 4, byte); setup_remote_node(6); /* Setup the regs on the remote node */ /* Set indirect connection to 0, to 3 */ -#warning "FIXME we need to find out the correct gateway for 8p" +#warning "FIXME we need to find out the correct gateway for 8p" static const u8 conn8_2[] = { #if !CROSS_BAR_47_56 6, 0, @@ -1230,55 +1230,55 @@ #if CROSS_BAR_47_56 //init 5, 6 here - /* here init 5, 6 */ - /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/ - val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,3); + /* here init 5, 6 */ + /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3); #if TRY_HIGH_FIRST == 1 byte = get_linkn_first(byte); #else - byte = get_linkn_last(byte); + byte = get_linkn_last(byte); #endif - print_linkn("(5,6) link=", byte); - setup_row_direct(5, 6, byte); + print_linkn("(5,6) link=", byte); + setup_row_direct(5, 6, byte); - setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { - setup_temp_row(byte+1,byte+3); - } + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } setup_temp_row(5,6); - verify_connection(7); + verify_connection(7); val = get_row(7,6); // to chect it if it is node6 before renaming if( (val>>16) == 1) { // it is real node 7 so swap it - /* We need to recompute link to 6 */ - val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,3); + /* We need to recompute link to 6 */ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3); #if TRY_HIGH_FIRST == 1 - byte = get_linkn_first(byte); + byte = get_linkn_first(byte); #else - byte = get_linkn_last(byte); + byte = get_linkn_last(byte); #endif - print_linkn("\t-->(5,6) link=", byte); - setup_row_direct(5, 6, byte); + print_linkn("\t-->(5,6) link=", byte); + setup_row_direct(5, 6, byte); #if 0 - setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { - setup_temp_row(byte+1,byte+3); - } + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } #endif setup_temp_row(5,6); - verify_connection(7); + verify_connection(7); } - val = pci_read_config32(NODE_HT(7), 0x6c); - byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ - print_linkn("(6,5) link=", byte); - setup_remote_row_direct(6, 5, byte); - /*Till now 56, 65 done */ + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ + print_linkn("(6,5) link=", byte); + setup_remote_row_direct(6, 5, byte); + /*Till now 56, 65 done */ #endif - + rename_temp_node(6); enable_routing(6); @@ -1292,27 +1292,27 @@ val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ - print_linkn("(7,5) link=", byte); + print_linkn("(7,5) link=", byte); setup_row_local(7,7); setup_remote_row_direct(7, 5, byte); #else - val = get_row(4,4); - byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6); - byte = get_linkn_first(byte); - print_linkn("(4,7) link=", byte); - setup_row_direct(4, 7, byte); + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6); + byte = get_linkn_first(byte); + print_linkn("(4,7) link=", byte); + setup_row_direct(4, 7, byte); - /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ + /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); } - verify_connection(7); + verify_connection(7); val = pci_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ - print_linkn("(7,4) link=", byte); + print_linkn("(7,4) link=", byte); setup_row_local(7,7); setup_remote_row_direct(7, 4, byte); /* till now 4-7, 7-4 done. */ @@ -1325,12 +1325,12 @@ val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6); byte = get_linkn_first(byte); - print_linkn("(5,7) link=", byte); + print_linkn("(5,7) link=", byte); setup_row_direct(5, 7, byte); - + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ for(byte=0; byte<4; byte+=2) { - setup_temp_row(byte+1,byte+3); + setup_temp_row(byte+1,byte+3); } verify_connection(7); @@ -1340,7 +1340,7 @@ print_linkn("(7,5) link=", byte); setup_remote_row_direct(7, 5, byte); /*Till now 57, 75 done */ - + #endif /* We need to init link between 6, and 7 direct link */ @@ -1372,12 +1372,12 @@ 2, 7, 3, 7, 4, 7, - + 6, 1, 6, 2, 6, 3, 6, 5, - + 7, 0, 7, 1, 7, 2, @@ -1385,68 +1385,68 @@ 7, 4, #else - - 4, 5, 6, 1, - 5, 4, 7, 1, - 6, 1, 5, 0, // or 4, 1 - 6, 2, 4, 0, - 6, 3, 5, 0, // or 4, 1 + 4, 5, 6, 1, + 5, 4, 7, 1, - 7, 0, 4, 0, // or 5, 1 - 7, 1, 5, 0, - 7, 2, 4, 0, // or 5, 1 - 7, 3, 5, 0, + 6, 1, 5, 0, // or 4, 1 + 6, 2, 4, 0, + 6, 3, 5, 0, // or 4, 1 + 7, 0, 4, 0, // or 5, 1 + 7, 1, 5, 0, + 7, 2, 4, 0, // or 5, 1 + 7, 3, 5, 0, + 0, 7, 2, 0, /* restore it*/ 1, 7, 3, 0, 2, 7, 4, 1, 3, 7, 5, 0, - 2, 5, 4, 1, /* reset it */ - 3, 4, 5, 1, + 2, 5, 4, 1, /* reset it */ + 3, 4, 5, 1, 4, 1, 2, 1, /* reset it */ 4, 3, 2, 1, 5, 2, 3, 1, /* reset it */ 5, 0, 3, 1, - + #endif }; setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3)); #if CROSS_BAR_47_56 - /* for 47, 56, 57, 75, 46, 64 we need to substract another link to - 6, 7, 6, 6, 7, 7 */ - static const u8 conn8_4[] = { + /* for 47, 56, 57, 75, 46, 64 we need to substract another link to + 6, 7, 6, 6, 7, 7 */ + static const u8 conn8_4[] = { //direct - 4, 7, 6, - 5, 6, 7, - 5, 7, 6, - 7, 5, 6, - 4, 6, 7, - 6, 4, 7, + 4, 7, 6, + 5, 6, 7, + 5, 7, 6, + 7, 5, 6, + 4, 6, 7, + 6, 4, 7, //in direct - 0, 6, 1, - 0, 7, 1, - - 1, 6, 0, - 1, 7, 0, + 0, 6, 1, + 0, 7, 1, - 2, 6, 3, + 1, 6, 0, + 1, 7, 0, + + 2, 6, 3, // 2, 7, 3, + - + // 3, 6, 1, + 3, 7, 2, - + 6, 0, 7, 6, 1, 7, // needed for via 5 6, 1, 4, // ??? 6, 2, 7, - 6, 3, 7, // needed for via 5 + 6, 3, 7, // needed for via 5 6, 3, 4, //??? 7, 0, 6, // needed for via 4 7, 0, 5, //??? @@ -1454,21 +1454,21 @@ 7, 2, 6, // needed for via 4 7, 2, 5, //??? 7, 3, 6, - }; + }; - opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); - static const u8 conn8_5[] = { - 2, 7, 0, + static const u8 conn8_5[] = { + 2, 7, 0, - 3, 6, 1, - }; - - opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); + 3, 6, 1, + }; + + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif - + /* ready to enable RT for Node 7 */ enable_routing(7); /* enable routing on node 7 (temp.) */ @@ -1485,20 +1485,20 @@ unsigned nodes; print_spew("Enabling SMP settings\r\n"); - + nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if(nodes == 2) + if(nodes == 2) nodes = setup_smp4(); #endif - + #if CONFIG_MAX_PHYSICAL_CPUS > 4 if(nodes == 4) nodes = setup_smp6(); #endif #if CONFIG_MAX_PHYSICAL_CPUS > 6 - if(nodes == 6) + if(nodes == 6) nodes = setup_smp8(); #endif @@ -1508,20 +1508,20 @@ print_debug_hex8(nodes); print_debug(" nodes initialized.\r\n"); #endif - + return nodes; } static unsigned verify_mp_capabilities(unsigned nodes) { unsigned node, mask; - + mask = 0x06; /* BigMPCap */ for (node=0; node<nodes; node++) { mask &= pci_read_config32(NODE_MC(node), 0xe8); } - + switch(mask) { #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ @@ -1538,7 +1538,7 @@ } break; } - + return nodes; } @@ -1560,14 +1560,14 @@ fill_row(node, row, DEFAULT); } } - + /* Update the local row */ for( node=0; node<nodes; node++) { uint32_t val = 0; for(row =0; row<nodes; row++) { val |= get_row(node, row); } - fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); + fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); } } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ @@ -1584,7 +1584,7 @@ } return totalcpus; - + } #endif @@ -1604,7 +1604,7 @@ total_cpus = nodes; } #endif - + /* set up cpu count and node count and enable Limit * Config Space Range for all available CPUs. * Also clear non coherent hypertransport bus range @@ -1631,13 +1631,13 @@ pci_write_config32(dev, 0x60, val); /* Only respond to real cpu pci configuration cycles - * and optimize the HT settings + * and optimize the HT settings */ val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); - val |= HTTC_LIMIT_CLDT_CFG | + val |= HTTC_LIMIT_CLDT_CFG | (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) | (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) | (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); @@ -1667,7 +1667,7 @@ if (is_cpu_pre_c0()) { /* Errata 66 - * Limit the number of downstream posted requests to 1 + * Limit the number of downstream posted requests to 1 */ cmd = pci_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { @@ -1694,7 +1694,7 @@ } else if (is_cpu_pre_d0()) { // d0 later don't need it uint32_t cmd_ref; - /* Errata 98 + /* Errata 98 * Set Clk Ramp Hystersis to 7 * Clock Power/Timing Low */ @@ -1728,8 +1728,8 @@ reg = 0x98 + (link * 0x20); link_type = pci_read_config32(f0_dev, reg); /* Only handle coherent links */ - if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == - (LinkConnected|InitComplete)) + if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == + (LinkConnected|InitComplete)) { cmd &= ~(0xff << (link *8)); cmd |= 0x25 << (link *8); @@ -1745,70 +1745,70 @@ static inline unsigned get_nodes(void) { - return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; + return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; } static int optimize_link_coherent_ht(void) { - int needs_reset = 0; + int needs_reset = 0; - unsigned nodes; + unsigned nodes; - nodes = get_nodes(); + nodes = get_nodes(); #if CONFIG_MAX_PHYSICAL_CPUS > 1 - if(nodes>1) { - needs_reset |= optimize_connection( - NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), - NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); - } + if(nodes>1) { + needs_reset |= optimize_connection( + NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), + NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); + } #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if(nodes>2) { - /* optimize physical connections - by LYH */ - static const u8 opt_conn4[] = { - 0,2, - 1,3, - 2,3, - }; - needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); - } + if(nodes>2) { + /* optimize physical connections - by LYH */ + static const u8 opt_conn4[] = { + 0,2, + 1,3, + 2,3, + }; + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); + } #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 - if(nodes>4) { - static const uint8_t opt_conn6[] ={ - 2, 4, - 3, 5, - #if !CROSS_BAR_47_56 - 4, 5, - #endif - }; - needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); - } + if(nodes>4) { + static const uint8_t opt_conn6[] ={ + 2, 4, + 3, 5, + #if !CROSS_BAR_47_56 + 4, 5, + #endif + }; + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); + } #endif #if CONFIG_MAX_PHYSICAL_CPUS > 6 - if(nodes>6) { - static const uint8_t opt_conn8[] ={ - 4, 6, - #if CROSS_BAR_47_56 - 4, 7, - 5, 6, - #endif - 5, 7, - 6, 7, - }; - needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); - } + if(nodes>6) { + static const uint8_t opt_conn8[] ={ + 4, 6, + #if CROSS_BAR_47_56 + 4, 7, + 5, 6, + #endif + 5, 7, + 6, 7, + }; + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); + } #endif #endif - needs_reset |= apply_cpu_errata_fixes(nodes); - needs_reset |= optimize_link_read_pointers(nodes); + needs_reset |= apply_cpu_errata_fixes(nodes); + needs_reset |= optimize_link_read_pointers(nodes); - return needs_reset; + return needs_reset; } #if RAMINIT_SYSINFO == 1 @@ -1823,9 +1823,9 @@ enable_bsp_routing(); #if CONFIG_MAX_PHYSICAL_CPUS > 1 - nodes = setup_smp(); - nodes = verify_mp_capabilities(nodes); - clear_dead_routes(nodes); + nodes = setup_smp(); + nodes = verify_mp_capabilities(nodes); + clear_dead_routes(nodes); #endif if (nodes == 1) { Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -7,10 +7,10 @@ { #if CACHE_AS_RAM_ADDRESS_DEBUG == 1 #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("------Address debug: %s%x------\r\n", str, val); - #else + printk_debug("------Address debug: %s%x------\r\n", str, val); + #else print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n"); - #endif + #endif #endif } @@ -32,8 +32,8 @@ static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -64,12 +64,12 @@ { int i; print_debug_pci_dev(dev); - + for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("\r\n%02x:",i); + printk_debug("\r\n%02x:",i); #else print_debug("\r\n"); print_debug_hex8(i); @@ -91,40 +91,40 @@ static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { - int i; - print_debug_pci_dev(dev); - print_debug(" -- index_reg="); print_debug_hex32(index_reg); + int i; + print_debug_pci_dev(dev); + print_debug(" -- index_reg="); print_debug_hex32(index_reg); - for(i = 0; i < 0x40; i++) { - uint32_t val; + for(i = 0; i < 0x40; i++) { + uint32_t val; int j; #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("\r\n%02x:",i); + printk_debug("\r\n%02x:",i); #else - print_debug("\r\n"); - print_debug_hex8(i); - print_debug_char(':'); + print_debug("\r\n"); + print_debug_hex8(i); + print_debug_char(':'); #endif - val = pci_read_config32_index_wait(dev, index_reg, i); + val = pci_read_config32_index_wait(dev, index_reg, i); for(j=0;j<4;j++) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug(" %02x", val & 0xff); + printk_debug(" %02x", val & 0xff); #else - print_debug_char(' '); print_debug_hex8(val&0xff); + print_debug_char(' '); print_debug_hex8(val&0xff); #endif val >>= 8; } - } - print_debug("\r\n"); + } + print_debug("\r\n"); } #endif static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -135,39 +135,39 @@ } dump_pci_device(dev); - if(((dev>>12) & 0x07) == 0) { - uint8_t hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } + if(((dev>>12) & 0x07) == 0) { + uint8_t hdr_type; + hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); + if((hdr_type & 0x80) != 0x80) { + dev += PCI_DEV(0,0,7); + } + } } } static void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; - for(dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); + device_t dev; + for(dev = PCI_DEV(busn, 0, 0); + dev <= PCI_DEV(busn, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); - if(((dev>>12) & 0x07) == 0) { - uint8_t hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } + if(((dev>>12) & 0x07) == 0) { + uint8_t hdr_type; + hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); + if((hdr_type & 0x80) != 0x80) { + dev += PCI_DEV(0,0,7); + } + } + } } #ifndef DEBUG_SMBUS @@ -187,8 +187,8 @@ #if CONFIG_USE_PRINTK_IN_CAR printk_debug("dimm: %02x.0: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); #endif @@ -222,10 +222,10 @@ if (device) { int j; #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("dimm: %02x.1: %02x", i, device); + printk_debug("dimm: %02x.1: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); #endif @@ -234,7 +234,7 @@ unsigned char byte; if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("\r\n%02x: ", j); + printk_debug("\r\n%02x: ", j); #else print_debug("\r\n"); print_debug_hex8(j); @@ -247,7 +247,7 @@ } byte = status & 0xff; #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%02x ", byte); + printk_debug("%02x ", byte); #else print_debug_hex8(byte); print_debug_char(' '); @@ -260,89 +260,89 @@ static void dump_smbus_registers(void) { unsigned device; - print_debug("\r\n"); - for(device = 1; device < 0x80; device++) { - int j; + print_debug("\r\n"); + for(device = 1; device < 0x80; device++) { + int j; if( smbus_read_byte(device, 0) < 0 ) continue; #if CONFIG_USE_PRINTK_IN_CAR printk_debug("smbus: %02x", device); #else - print_debug("smbus: "); - print_debug_hex8(device); + print_debug("smbus: "); + print_debug_hex8(device); #endif - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + status = smbus_read_byte(device, j); + if (status < 0) { break; - } - if ((j & 0xf) == 0) { + } + if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%02x: ",j); #else - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); #endif - } - byte = status & 0xff; + } + byte = status & 0xff; #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%02x ", byte); + printk_debug("%02x ", byte); #else - print_debug_hex8(byte); - print_debug_char(' '); + print_debug_hex8(byte); + print_debug_char(' '); #endif - } - print_debug("\r\n"); - } + } + print_debug("\r\n"); + } } #endif -static void dump_io_resources(unsigned port) +static void dump_io_resources(unsigned port) { int i; - udelay(2000); + udelay(2000); #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%04x:\r\n", port); #else - print_debug_hex16(port); - print_debug(":\r\n"); + print_debug_hex16(port); + print_debug(":\r\n"); #endif - for(i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) { + for(i=0;i<256;i++) { + uint8_t val; + if ((i & 0x0f) == 0) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%02x:", i); #else - print_debug_hex8(i); - print_debug_char(':'); + print_debug_hex8(i); + print_debug_char(':'); #endif - } - val = inb(port); + } + val = inb(port); #if CONFIG_USE_PRINTK_IN_CAR printk_debug(" %02x",val); #else - print_debug_char(' '); - print_debug_hex8(val); + print_debug_char(' '); + print_debug_hex8(val); #endif - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } port++; - } + } } static void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; print_debug("dump_mem:"); - for(i=start;i<end;i++) { + for(i=start;i<end;i++) { if((i & 0xf)==0) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%08x:", i); -#else +#else print_debug("\r\n"); print_debug_hex32(i); print_debug(":"); @@ -352,9 +352,9 @@ printk_debug(" %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); - print_debug_hex8((unsigned char)*((unsigned char *)i)); + print_debug_hex8((unsigned char)*((unsigned char *)i)); #endif - } - print_debug("\r\n"); + } + print_debug("\r\n"); } #endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -1,11 +1,11 @@ -/* +/* 2005.11 yhlu add let the real sb to use small unitid */ // only for sb ht chain static void enumerate_ht_chain(void) { -#if HT_CHAIN_UNITID_BASE != 0 -/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ +#if HT_CHAIN_UNITID_BASE != 0 +/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. * On most boards this just happens. If a cpu has multiple @@ -43,7 +43,7 @@ hdr_type &= 0x7f; if ((hdr_type == PCI_HEADER_TYPE_NORMAL) || - (hdr_type == PCI_HEADER_TYPE_BRIDGE)) + (hdr_type == PCI_HEADER_TYPE_BRIDGE)) { pos = pci_read_config8(dev, PCI_CAPABILITY_LIST); } @@ -71,7 +71,7 @@ } else { goto out; } - } + } real_last_unitid = next_unitid; real_last_pos = pos; ht_dev_num++; @@ -115,7 +115,7 @@ } } } while((ctrl & (1 << 5)) == 0); - + break; } } @@ -130,9 +130,9 @@ if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); - flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); + flags &= ~0x1f; + flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags); } #endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -35,36 +35,36 @@ #if 0 unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; + device_t dev; + unsigned reg; - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; } #endif @@ -87,8 +87,8 @@ * So we need to make sure that the south bridge link will always be on * pci1234[0]. * - * Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1, - * but you only install HT I/O 2 and HT I/O 3. The HT I/Os will end up in registers + * Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1, + * but you only install HT I/O 2 and HT I/O 3. The HT I/Os will end up in registers * 0xE4 and 0xE8. * * But we want to leave pci1234[1] to HT I/O 1 (even though it is disabled), @@ -119,7 +119,7 @@ * }; * * - * For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7): + * For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7): * You need an array pci1234[6]: * * unsigned pci1234[] = { @@ -130,10 +130,10 @@ * 0x0000f60, // HT IO 4 card always on node 6 * 0x0000f70 // HT IO 5 card always on node 7 * }; - * - * - * For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P + - * htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5), + * + * + * For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P + + * htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5), * you need an array pci1234[8]: * * unsigned pci1234[] = { @@ -146,10 +146,10 @@ * 0x0000f40, // HT IO 6 card always on node 4 * 0x0000f50 // HT IO 7 card always on node 5 * }; - * - * + * + * * For 4P + htio(n1) + htio(n2) + htio(n3), 4p + htio(n1) + 2p + htio(n4) + - * htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7), + * htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7), * you need an array pci1234[8]: * * unsigned pci1234[] = { @@ -162,53 +162,53 @@ * 0x0000f60, // HT IO 6 card always on node 6 * 0x0000f70 // HT IO 7 card always on node 7 * }; - * - * + * + * * So the maximum posible value of HC_POSSIBLE_NUM is 8. (FIXME Why?) - * + * * 1n: 3 * 2n: 2x2 - 1 - * 4n: 1x4 - 2 - * 6n: 2 - * 8n: 2 - * Total: 12 - * - * Just put all the possible HT Node/link to the list tp pci1234[] in + * 4n: 1x4 - 2 + * 6n: 2 + * 8n: 2 + * Total: 12 + * + * Just put all the possible HT Node/link to the list tp pci1234[] in * src/mainboard/<vendor>/<mainboard>get_bus_conf.c - * + * * Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if * you have too many SSDTs - * + * * What about co-processor in socket 1 on a 2 way system? Or socket 2 and * socket 3 on a 4 way system? Treat that as an HC, too! - * + * */ void get_sblk_pci1234(void) { - device_t dev; - int i,j; - uint32_t dword; + device_t dev; + int i,j; + uint32_t dword; - /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); - dword = pci_read_config32(dev, 0x64); - sysconf.sblk = (dword>>8) & 0x3; + /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ + dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); + dword = pci_read_config32(dev, 0x64); + sysconf.sblk = (dword>>8) & 0x3; - dword &=0x0300; - dword |= 1; - sysconf.pci1234[0] = dword; + dword &=0x0300; + dword |= 1; + sysconf.pci1234[0] = dword; sysconf.hcid[0] = 0; - /* About hardcoded numbering for HT_IO support + /* About hardcoded numbering for HT_IO support * * Set the node_id and link_id that could have a HT chain in the one * array, (FIXME: which one?) then check if is enabled. Then update - * final value - */ + * final value + */ - /* Here we need to set hcdn + /* Here we need to set hcdn * * 1. hypertransport.c needs to record hcdn_reg together with 0xe0, * 0xe4, 0xe8, 0xec when are set (FIXME: when WHAT is set?) @@ -216,48 +216,48 @@ * 2. So at the same time we need update hcdn with hcdn_reg here. FIXME: Why? */ - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - for(j=0;j<4;j++) { - uint32_t dwordx; - dwordx = pci_read_config32(dev, 0xe0 + j*4); - dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ - if((dwordx & 0xff1) == dword) { /* SBLINK */ - sysconf.pci1234[0] = dwordx; + for(j=0;j<4;j++) { + uint32_t dwordx; + dwordx = pci_read_config32(dev, 0xe0 + j*4); + dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ + if((dwordx & 0xff1) == dword) { /* SBLINK */ + sysconf.pci1234[0] = dwordx; sysconf.hcdn[0] = sysconf.hcdn_reg[j]; - continue; - } + continue; + } - if((dwordx & 1) == 1) { - /* We need to find out the number of HC - * for exact match + if((dwordx & 1) == 1) { + /* We need to find out the number of HC + * for exact match */ - for(i=1;i<sysconf.hc_possible_num;i++) { - if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { - sysconf.pci1234[i] = dwordx; + for(i=1;i<sysconf.hc_possible_num;i++) { + if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { + sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; - break; - } - } + break; + } + } - /* For 0xff0 match or same node */ - for(i=1;i<sysconf.hc_possible_num;i++) { - if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { - sysconf.pci1234[i] = dwordx; + /* For 0xff0 match or same node */ + for(i=1;i<sysconf.hc_possible_num;i++) { + if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { + sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; - break; - } - } - } - } + break; + } + } + } + } - for(i=1;i<sysconf.hc_possible_num;i++) { - if((sysconf.pci1234[i] & 1) != 1) { - sysconf.pci1234[i] = 0; + for(i=1;i<sysconf.hc_possible_num;i++) { + if((sysconf.pci1234[i] & 1) != 1) { + sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; - } + } sysconf.hcid[i] = 0; - } + } } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -8,7 +8,7 @@ #include <device/hypertransport_def.h> #ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 + #define K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef K8_SCAN_PCI_BUS @@ -16,20 +16,20 @@ #endif #ifndef K8_ALLOCATE_IO_RANGE - #define K8_ALLOCATE_IO_RANGE 0 + #define K8_ALLOCATE_IO_RANGE 0 #endif -// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM +// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM #ifndef K8_ALLOCATE_MMIO_RANGE - #define K8_ALLOCATE_MMIO_RANGE 0 + #define K8_ALLOCATE_MMIO_RANGE 0 #endif static inline void print_linkn_in (const char *strval, uint8_t byteval) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%02x\r\n", strval, byteval); + printk_debug("%s%02x\r\n", strval, byteval); #else - print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n"); + print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n"); #endif } @@ -67,13 +67,13 @@ } static uint8_t ht_lookup_slave_capability(device_t dev) -{ +{ return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format } static uint8_t ht_lookup_host_capability(device_t dev) { - return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format + return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format } static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) @@ -91,12 +91,12 @@ /* Check if is already collapsed */ if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) { dev = PCI_DEV(bus, 0, 0); - id = pci_read_config32(dev, PCI_VENDOR_ID); - if ( ! ( (id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000) ) ) { - return; - } - } + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (!((id == 0xffffffff) || (id == 0x00000000) || + (id == 0x0000ffff) || (id == 0xffff0000))) { + return; + } + } /* Spin through the devices and collapse any previous * hypertransport enumeration. @@ -105,13 +105,13 @@ uint32_t id; uint8_t pos; uint16_t flags; - + id = pci_read_config32(dev, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { continue; } - + pos = ht_lookup_slave_capability(dev); if (!pos) { continue; @@ -145,23 +145,24 @@ if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) { freq_cap &= ~(1 << HT_FREQ_800Mhz); return freq_cap; - } - + } + /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 - if (is_cpu_pre_e0()) { // only E0 later support 1GHz + #if K8_HT_FREQ_1G_SUPPORT == 1 + #if K8_REV_F_SUPPORT == 0 + if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } #endif - #else - freq_cap &= ~(1 << HT_FREQ_1000Mhz); + #else + freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif } return freq_cap; } + static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) { uint8_t width_cap = pci_read_config8(dev, pos); @@ -176,12 +177,13 @@ width_cap &= 0x88; } } - + return width_cap; - + } + #define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \ - (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF)) + (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF)) #define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF) #define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF) @@ -189,19 +191,19 @@ #define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF) #define PCI_HT_HOST_OFFS LINK_OFFS( \ - PCI_HT_CAP_HOST_CTRL, \ + PCI_HT_CAP_HOST_CTRL, \ PCI_HT_CAP_HOST_WIDTH, \ PCI_HT_CAP_HOST_FREQ, \ PCI_HT_CAP_HOST_FREQ_CAP) #define PCI_HT_SLAVE0_OFFS LINK_OFFS( \ - PCI_HT_CAP_SLAVE_CTRL0, \ + PCI_HT_CAP_SLAVE_CTRL0, \ PCI_HT_CAP_SLAVE_WIDTH0, \ PCI_HT_CAP_SLAVE_FREQ0, \ PCI_HT_CAP_SLAVE_FREQ_CAP0) #define PCI_HT_SLAVE1_OFFS LINK_OFFS( \ - PCI_HT_CAP_SLAVE_CTRL1, \ + PCI_HT_CAP_SLAVE_CTRL1, \ PCI_HT_CAP_SLAVE_WIDTH1, \ PCI_HT_CAP_SLAVE_FREQ1, \ PCI_HT_CAP_SLAVE_FREQ_CAP1) @@ -280,22 +282,23 @@ return needs_reset; } + #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) #if RAMINIT_SYSINFO == 1 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); -static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) +static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) #else static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid); static int scan_pci_bus( unsigned bus) #endif { - /* - here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7) - So We can scan these devices to find out if they are bridge - If it is pci bridge, We need to set busn in bridge, and go on - For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus - */ + /* + here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7) + So We can scan these devices to find out if they are bridge + If it is pci bridge, We need to set busn in bridge, and go on + For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus + */ unsigned int devfn; unsigned new_bus; unsigned max_bus; @@ -314,85 +317,85 @@ new_bus = bus; - for (devfn = 0; devfn <= 0xff; devfn++) { - uint8_t hdr_type; - uint16_t class; + for (devfn = 0; devfn <= 0xff; devfn++) { + uint8_t hdr_type; + uint16_t class; uint32_t buses; device_t dev; uint16_t cr; dev = PCI_DEV((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7)); - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - class = pci_read_config16(dev, PCI_CLASS_DEVICE); + hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); + class = pci_read_config16(dev, PCI_CLASS_DEVICE); switch(hdr_type & 0x7f) { /* header type */ - case PCI_HEADER_TYPE_BRIDGE: - if (class != PCI_CLASS_BRIDGE_PCI) goto bad; + case PCI_HEADER_TYPE_BRIDGE: + if (class != PCI_CLASS_BRIDGE_PCI) goto bad; /* set the bus range dev */ - /* Clear all status bits and turn off memory, I/O and master enables. */ - cr = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, 0x0000); - pci_write_config16(dev, PCI_STATUS, 0xffff); + /* Clear all status bits and turn off memory, I/O and master enables. */ + cr = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, 0x0000); + pci_write_config16(dev, PCI_STATUS, 0xffff); - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - buses &= 0xff000000; + buses &= 0xff000000; new_bus++; - buses |= (((unsigned int) (bus & 0xff) << 0) | - ((unsigned int) (new_bus & 0xff) << 8) | - ((unsigned int) max_bus << 16)); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - + buses |= (((unsigned int) (bus & 0xff) << 0) | + ((unsigned int) (new_bus & 0xff) << 8) | + ((unsigned int) max_bus << 16)); + pci_write_config32(dev, PCI_PRIMARY_BUS, buses); + /* here we need to figure out if dev is a ht bridge if it is ht bridge, we need to call ht_setup_chainx at first - Not verified --- yhlu + Not verified --- yhlu */ uint8_t upos; - upos = ht_lookup_host_capability(dev); // one func one ht sub - if (upos) { // sub ht chain + upos = ht_lookup_host_capability(dev); // one func one ht sub + if (upos) { // sub ht chain uint8_t busn; busn = (new_bus & 0xff); - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(busn, 0); + /* Make certain the HT bus is not enumerated */ + ht_collapse_previous_enumeration(busn, 0); /* scan the ht chain */ #if RAMINIT_SYSINFO == 1 - ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid + ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid #else new_bus |= (ht_setup_chainx(dev, upos, busn, 0)<<16); // store reset_needed to upword #endif - } - - #if RAMINIT_SYSINFO == 1 + } + + #if RAMINIT_SYSINFO == 1 new_bus = scan_pci_bus(new_bus, sysinfo); #else new_bus = scan_pci_bus(new_bus); #endif /* set real max bus num in that */ - buses = (buses & 0xff00ffff) | - ((unsigned int) (new_bus & 0xff) << 16); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); + buses = (buses & 0xff00ffff) | + ((unsigned int) (new_bus & 0xff) << 16); + pci_write_config32(dev, PCI_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); - break; - default: - bad: + break; + default: + bad: ; - } + } - /* if this is not a multi function device, - * or the device is not present don't waste - * time probing another function. - * Skip to next device. - */ - if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80)) - { - devfn += 0x07; - } - } - - return new_bus; + /* if this is not a multi function device, + * or the device is not present don't waste + * time probing another function. + * Skip to next device. + */ + if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80)) + { + devfn += 0x07; + } + } + + return new_bus; } #endif @@ -412,9 +415,9 @@ #endif #if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid; - uint8_t real_last_pos; + //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE + unsigned real_last_unitid; + uint8_t real_last_pos; int ht_dev_num = 0; uint8_t end_used = 0; #endif @@ -428,50 +431,50 @@ uint16_t flags, ctrl; uint8_t count; unsigned offs; - + /* Wait until the link initialization is complete */ do { ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs)); /* Is this the end of the hypertransport chain? */ if (ctrl & (1 << 6)) { - goto end_of_chain; + goto end_of_chain; } if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have - * a CRC error. - * Sometimes this can happen due to link - * retrain, so lets knock it down and see - * if its transient - */ + /* + * Either the link has failed, or we have + * a CRC error. + * Sometimes this can happen due to link + * retrain, so lets knock it down and see + * if its transient + */ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc - pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl); - ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs)); - if (ctrl & ((1 << 4) | (1 << 8))) { - print_err("Detected error on Hypertransport Link\n"); + pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl); + ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs)); + if (ctrl & ((1 << 4) | (1 << 8))) { + print_err("Detected error on Hypertransport Link\n"); break; - } + } } } while((ctrl & (1 << 5)) == 0); - + device_t dev = PCI_DEV(bus, 0, 0); last_unitid = next_unitid; id = pci_read_config32(dev, PCI_VENDOR_ID); /* If the chain is enumerated quit */ - if ( (id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000)) + if ((id == 0xffffffff) || (id == 0x00000000) || + (id == 0x0000ffff) || (id == 0xffff0000)) { break; } pos = ht_lookup_slave_capability(dev); if (!pos) { - print_err("udev="); print_err_hex32(udev); - print_err("\tupos="); print_err_hex32(upos); - print_err("\tuoffs="); print_err_hex32(uoffs); + print_err("udev="); print_err_hex32(udev); + print_err("\tupos="); print_err_hex32(upos); + print_err("\tuoffs="); print_err_hex32(uoffs); print_err("\tHT link capability not found\r\n"); break; } @@ -481,17 +484,17 @@ if(offset_unitid) { if(next_unitid>= (bus ? 0x20:0x18) ) { if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; } - - } - real_last_pos = pos; + + } + real_last_pos = pos; real_last_unitid = next_unitid; ht_dev_num++; - } + } #endif /* Update the Unitid of the current device */ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); @@ -499,23 +502,23 @@ flags |= next_unitid & 0x1f; pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); - /* Compute the number of unitids consumed */ - count = (flags >> 5) & 0x1f; + /* Compute the number of unitids consumed */ + count = (flags >> 5) & 0x1f; /* Note the change in device number */ dev = PCI_DEV(bus, next_unitid, 0); - next_unitid += count; + next_unitid += count; /* Find which side of the ht link we are on, * by reading which direction our last write to PCI_CAP_FLAGS * came from. */ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS; - + offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS; + #if RAMINIT_SYSINFO == 1 - /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */ + /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */ { struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num]; link_pair->udev = udev; @@ -539,32 +542,32 @@ out: end_of_chain: ; - + #if HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) { - uint16_t flags; + if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) { + uint16_t flags; int i; - flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); + flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); + flags &= ~0x1f; + flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); - #if RAMINIT_SYSINFO == 1 + #if RAMINIT_SYSINFO == 1 // Here need to change the dev in the array for(i=0;i<sysinfo->link_pair_num;i++) - { - struct link_pair_st *link_pair = &sysinfo->link_pair[i]; - if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { + { + struct link_pair_st *link_pair = &sysinfo->link_pair[i]; + if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); continue; } - if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); - } - } + if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { + link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + } + } #endif - } + } #endif #if RAMINIT_SYSINFO == 0 @@ -581,55 +584,55 @@ { unsigned offset_unitid = 0; #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; + offset_unitid = 1; #endif - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. - */ + /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. + * On most boards this just happens. If a cpu has multiple + * non Coherent links the appropriate bus registers for the + * links needs to be programed to point at bus 0. + */ - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(0, 0); + /* Make certain the HT bus is not enumerated */ + ht_collapse_previous_enumeration(0, 0); #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; + offset_unitid = 1; #endif #if RAMINIT_SYSINFO == 1 ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo); #else - return ht_setup_chainx(udev, upos, 0, offset_unitid); + return ht_setup_chainx(udev, upos, 0, offset_unitid); #endif } static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) { uint32_t dword, dword_old; uint8_t link_type; - + /* This works on an Athlon64 because unimplemented links return 0 */ dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); link_type = dword & 0xff; - - + + if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); dword &= ~( 0xff<<(linkn *8) ); dword |= val << (linkn *8); - + if (dword != dword_old) { pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword); return 1; } } - + return 0; } static int optimize_link_read_pointers_chain(uint8_t ht_c_num) { - int reset_needed; + int reset_needed; uint8_t i; reset_needed = 0; @@ -642,14 +645,14 @@ unsigned devn = 1; #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if(i==0) // to check if it is sb ht chain - #endif - devn = HT_CHAIN_UNITID_BASE; - #endif + #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if(i==0) // to check if it is sb ht chain + #endif + devn = HT_CHAIN_UNITID_BASE; + #endif reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); - + nodeid = ((reg & 0xf0)>>4); // nodeid linkn = ((reg & 0xf00)>>8); // link n busn = (reg & 0xff0000)>>16; //busn @@ -672,59 +675,59 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) { - uint32_t dword; - uint8_t link_type; + uint32_t dword; + uint8_t link_type; unsigned regpos; device_t dev; - /* This works on an Athlon64 because unimplemented links return 0 */ + /* This works on an Athlon64 because unimplemented links return 0 */ regpos = 0x98 + (linkn * 0x20); dev = PCI_DEV(0,0x18+node,0); - dword = pci_read_config32(dev, regpos); - link_type = dword & 0xff; + dword = pci_read_config32(dev, regpos); + link_type = dword & 0xff; - if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ regpos = 0x90 + (linkn * 0x20); - dword = pci_read_config32(dev, regpos ); + dword = pci_read_config32(dev, regpos ); - if (dword != val) { - pci_write_config32(dev, regpos, val); - return 1; - } + if (dword != val) { + pci_write_config32(dev, regpos, val); + return 1; + } } - return 0; + return 0; } static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { - int reset_needed; - uint8_t i; + int reset_needed; + uint8_t i; - reset_needed = 0; + reset_needed = 0; - for (i = 0; i < ht_c_num; i++) { - uint32_t reg; - uint8_t nodeid, linkn; - uint8_t busn; - unsigned devn; + for (i = 0; i < ht_c_num; i++) { + uint32_t reg; + uint8_t nodeid, linkn; + uint8_t busn; + unsigned devn; - reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); - if((reg & 3) != 3) continue; // not enabled + reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); + if((reg & 3) != 3) continue; // not enabled - nodeid = ((reg & 0xf0)>>4); // nodeid - linkn = ((reg & 0xf00)>>8); // link n - busn = (reg & 0xff0000)>>16; //busn + nodeid = ((reg & 0xf0)>>4); // nodeid + linkn = ((reg & 0xf00)>>8); // link n + busn = (reg & 0xff0000)>>16; //busn for(devn = 0; devn < 0x20; devn++) { - reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? - if ( (reg & 0xffff) == vendorid ) { - reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); + reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? + if ( (reg & 0xffff) == vendorid ) { + reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); break; - } + } } - } + } - return reset_needed; + return reset_needed; } @@ -734,13 +737,13 @@ static int ht_setup_chains(uint8_t ht_c_num) #endif { - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. + /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. * On most boards this just happens. If a cpu has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ - uint8_t upos; - device_t udev; + uint8_t upos; + device_t udev; uint8_t i; #if RAMINIT_SYSINFO == 0 @@ -760,30 +763,30 @@ unsigned bus; #endif unsigned offset_unitid = 0; - + reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); //We need setup 0x94, 0xb4, and 0xd4 according to the reg devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; - + dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ; dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); - + #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if(i==0) // to check if it is sb ht chain - #endif - offset_unitid = 1; - #endif - - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(busn, offset_unitid); + #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if(i==0) // to check if it is sb ht chain + #endif + offset_unitid = 1; + #endif + /* Make certain the HT bus is not enumerated */ + ht_collapse_previous_enumeration(busn, offset_unitid); + upos = ((reg & 0xf00)>>8) * 0x20 + 0x80; udev = PCI_DEV(0, devpos, 0); @@ -794,10 +797,10 @@ #endif #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) - /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ - bus = busn; // we need 32 bit + /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ + bus = busn; // we need 32 bit #if RAMINIT_SYSINFO == 1 - scan_pci_bus(bus, sysinfo); + scan_pci_bus(bus, sysinfo); #else reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword #endif @@ -821,30 +824,30 @@ #else static int ht_setup_chains_x(void) #endif -{ - uint8_t nodeid; - uint32_t reg; +{ + uint8_t nodeid; + uint32_t reg; uint32_t tempreg; - uint8_t next_busn; - uint8_t ht_c_num; + uint8_t next_busn; + uint8_t ht_c_num; uint8_t nodes; -#if K8_ALLOCATE_IO_RANGE == 1 +#if K8_ALLOCATE_IO_RANGE == 1 unsigned next_io_base; #endif - nodes = get_nodes(); - - /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ + nodes = get_nodes(); + + /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ print_linkn_in("SBLink=", ((reg>>8) & 3) ); #if RAMINIT_SYSINFO == 1 sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; #endif - tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); - pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg); + tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); + pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg); next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ @@ -858,95 +861,95 @@ #endif /* clean others */ - for(ht_c_num=1;ht_c_num<4; ht_c_num++) { - pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); + for(ht_c_num=1;ht_c_num<4; ht_c_num++) { + pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); #if K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0); #endif - } - - for(nodeid=0; nodeid<nodes; nodeid++) { - device_t dev; - uint8_t linkn; - dev = PCI_DEV(0, 0x18+nodeid,0); - for(linkn = 0; linkn<3; linkn++) { - unsigned regpos; - regpos = 0x98 + 0x20 * linkn; - reg = pci_read_config32(dev, regpos); - if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/ + } + + for(nodeid=0; nodeid<nodes; nodeid++) { + device_t dev; + uint8_t linkn; + dev = PCI_DEV(0, 0x18+nodeid,0); + for(linkn = 0; linkn<3; linkn++) { + unsigned regpos; + regpos = 0x98 + 0x20 * linkn; + reg = pci_read_config32(dev, regpos); + if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/ print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); - tempreg = 3 | (nodeid <<4) | (linkn<<8); - /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ - for(ht_c_num=0;ht_c_num<4; ht_c_num++) { - reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); - if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ - break; - } - } - if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/ - /*update to 0xe0...*/ + tempreg = 3 | (nodeid <<4) | (linkn<<8); + /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ + for(ht_c_num=0;ht_c_num<4; ht_c_num++) { + reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); + if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ + break; + } + } + if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/ + /*update to 0xe0...*/ if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */ print_linkn_in("\tbusn=", next_busn); - tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24); - pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); + tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24); + pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); next_busn+=0x3f+1; -#if K8_ALLOCATE_IO_RANGE == 1 +#if K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ - tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit - pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? - pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); - next_io_base += 0x3+0x1; + tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit + pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); + tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? + pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); + next_io_base += 0x3+0x1; #endif - } - } - /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/ + } + } + /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/ - for(nodeid = 1; nodeid<nodes; nodeid++) { - int i; - device_t dev; - dev = PCI_DEV(0, 0x18+nodeid,1); - for(i = 0; i< 4; i++) { - unsigned regpos; - regpos = 0xe0 + i * 4; - reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); - pci_write_config32(dev, regpos, reg); - } + for(nodeid = 1; nodeid<nodes; nodeid++) { + int i; + device_t dev; + dev = PCI_DEV(0, 0x18+nodeid,1); + for(i = 0; i< 4; i++) { + unsigned regpos; + regpos = 0xe0 + i * 4; + reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); + pci_write_config32(dev, regpos, reg); + } #if K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ - for(i = 0; i< 4; i++) { - unsigned regpos; - regpos = 0xc4 + i * 8; - reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); - pci_write_config32(dev, regpos, reg); - } - for(i = 0; i< 4; i++) { - unsigned regpos; - regpos = 0xc0 + i * 8; - reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); - pci_write_config32(dev, regpos, reg); - } + for(i = 0; i< 4; i++) { + unsigned regpos; + regpos = 0xc4 + i * 8; + reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); + pci_write_config32(dev, regpos, reg); + } + for(i = 0; i< 4; i++) { + unsigned regpos; + regpos = 0xc0 + i * 8; + reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); + pci_write_config32(dev, regpos, reg); + } #endif - } - + } + /* recount ht_c_num*/ uint8_t i=0; - for(ht_c_num=0;ht_c_num<4; ht_c_num++) { + for(ht_c_num=0;ht_c_num<4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); - if(((reg & 0xf) != 0x0)) { + if(((reg & 0xf) != 0x0)) { i++; } - } + } #if RAMINIT_SYSINFO == 1 sysinfo->ht_c_num = i; - ht_setup_chains(i, sysinfo); + ht_setup_chains(i, sysinfo); sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); #else return ht_setup_chains(i); @@ -960,10 +963,10 @@ // We need to use recorded link pair info to optimize the link int i; int reset_needed = 0; - + unsigned link_pair_num = sysinfo->link_pair_num; - for(i=0; i< link_pair_num; i++) { + for(i=0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -103,14 +103,14 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) { - + uint32_t link_type; int i; uint32_t busses, config_busses; unsigned free_reg, config_reg; unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain - unsigned max_bus; - unsigned min_bus; + unsigned max_bus; + unsigned min_bus; unsigned max_devfn; dev->link[link].cap = 0x80 + (link *0x20); @@ -127,7 +127,7 @@ return max; } /* See if there is an available configuration space mapping - * register in function 1. + * register in function 1. */ free_reg = 0; for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { @@ -137,7 +137,7 @@ free_reg = config_reg; continue; } - if (((config & 3) == 3) && + if (((config & 3) == 3) && (((config >> 4) & 7) == nodeid) && (((config >> 8) & 3) == link)) { break; @@ -147,7 +147,7 @@ config_reg = free_reg; } /* If we can't find an available configuration space mapping - * register skip this bus + * register skip this bus */ if (config_reg > 0xec) { return max; @@ -158,36 +158,36 @@ * so we set the subordinate bus number to 0xff for the moment. */ #if SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 + // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here - min_bus = max; - } + min_bus = max; + } #if SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif + else { + min_bus = ((max>>6) + 1) * 0x40; + } + max = min_bus; + #else + //other ... + else { + min_bus = ++max; + } + #endif #else - min_bus = ++max; + min_bus = ++max; #endif - max_bus = 0xff; + max_bus = 0xff; - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + dev->link[link].secondary = min_bus; + dev->link[link].subordinate = max_bus; /* Read the existing primary/secondary/subordinate bus * number configuration. */ busses = pci_read_config32(dev, dev->link[link].cap + 0x14); config_busses = f1_read_config32(config_reg); - + /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagates by the bridge if it is * not correctly configured @@ -199,22 +199,22 @@ pci_write_config32(dev, dev->link[link].cap + 0x14, busses); config_busses &= 0x000fc88; - config_busses |= + config_busses |= (3 << 0) | /* rw enable, no device compare */ - (( nodeid & 7) << 4) | - (( link & 3 ) << 8) | + (( nodeid & 7) << 4) | + (( link & 3 ) << 8) | ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the - * chain on the hypertranport link + * chain on the hypertranport link */ for(i=0;i<4;i++) { ht_unitid_base[i] = 0x20; } - if (min_bus == 0) + if (min_bus == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7; @@ -251,42 +251,42 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) { - unsigned nodeid; - unsigned link; - unsigned sblink = 0; + unsigned nodeid; + unsigned link; + unsigned sblink = 0; unsigned offset_unitid = 0; - nodeid = amdk8_nodeid(dev); - - if(nodeid==0) { - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + nodeid = amdk8_nodeid(dev); + + if(nodeid==0) { + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; #if SB_HT_CHAIN_ON_BUS0 > 0 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; - #endif + offset_unitid = 1; + #endif max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 #endif - } + } - for(link = 0; link < dev->links; link++) { + for(link = 0; link < dev->links; link++) { #if SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; #endif max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); - } + } - return max; + return max; } -static int reg_useable(unsigned reg, +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -303,7 +303,7 @@ result = 2; if (res) { result = 0; - if ( (goal_link == (link - 1)) && + if ( (goal_link == (link - 1)) && (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) { result = 1; @@ -370,7 +370,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) { struct resource *resource; - + /* Initialize the io space constraints on the current bus */ resource = amdk8_find_iopair(dev, nodeid, link); if (resource) { @@ -380,7 +380,7 @@ resource->gran = log2(HT_IO_HOST_ALIGN); resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[link], resource, + compute_allocate_resource(&dev->link[link], resource, IORESOURCE_IO, IORESOURCE_IO); } @@ -393,8 +393,8 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); } @@ -407,8 +407,8 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); } } @@ -439,7 +439,7 @@ if (resource->flags & IORESOURCE_STORED) { return; } - + /* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return; @@ -450,7 +450,7 @@ } /* Get the base address */ rbase = resource->base; - + /* Get the limit (rounded up) */ rend = resource_end(resource); @@ -473,14 +473,14 @@ limit |= (nodeid & 7); if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); + printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); base |= PCI_IO_BASE_VGA_EN; } if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { base |= PCI_IO_BASE_NO_ISA; } - + f1_write_config32(reg + 0x4, limit); f1_write_config32(reg, base); } @@ -513,7 +513,7 @@ * but it is too diffcult to deal with the resource allocation magic. */ #if CONFIG_CONSOLE_VGA_MULTI == 1 -extern device_t vga_pri; // the primary vga device, defined in device.c +extern device_t vga_pri; // the primary vga device, defined in device.c #endif static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) @@ -528,7 +528,7 @@ for (link = 0; link < dev->links; link++) { if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI == 1 - printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, + printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, dev->link[link].secondary,dev->link[link].subordinate); /* We need to make sure the vga_pri is under the link */ if((vga_pri->bus->secondary >= dev->link[link].secondary ) && @@ -538,7 +538,7 @@ break; } } - + /* no VGA card installed */ if (link == dev->links) return; @@ -581,7 +581,7 @@ nodeid = amdk8_nodeid(dev); amdk8_create_vga_resource(dev, nodeid); - + /* Set each resource we have found */ for(i = 0; i < dev->resources; i++) { amdk8_set_resource(dev, &dev->resource[i], nodeid); @@ -604,7 +604,7 @@ static void mcf0_control_init(struct device *dev) { -#if 0 +#if 0 printk_debug("NB: Function 0 Misc Control.. "); #endif #if 0 @@ -673,38 +673,38 @@ resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; #else - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_IO, IORESOURCE_IO); + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_IO, IORESOURCE_IO); - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); #endif } -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -759,83 +759,83 @@ struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - for (i = 0; i < 8; i++) { - uint32_t base; - uint32_t hole; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + for (i = 0; i < 8; i++) { + uint32_t base; + uint32_t hole; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } - hole = pci_read_config32(__f1_dev[i], 0xf0); - if(hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole + hole = pci_read_config32(__f1_dev[i], 0xf0); + if(hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole } - } + } - //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk - if(mem_hole.node_id==-1) { - uint32_t limitk_pri = 0; - for(i=0; i<8; i++) { - uint32_t base, limit; - unsigned base_k, limit_k; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if(mem_hole.node_id==-1) { + uint32_t limitk_pri = 0; + for(i=0; i<8; i++) { + uint32_t base, limit; + unsigned base_k, limit_k; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } - base_k = (base & 0xffff0000) >> 2; - if(limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = limitk_pri; - mem_hole.node_id = i; - break; //only one hole + base_k = (base & 0xffff0000) >> 2; + if(limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = limitk_pri; + mem_hole.node_id = i; + break; //only one hole } - limit = f1_read_config32(0x44 + (i << 3)); - limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; - limitk_pri = limit_k; - } - } - + limit = f1_read_config32(0x44 + (i << 3)); + limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + limitk_pri = limit_k; + } + } + return mem_hole; - + } static void disable_hoist_memory(unsigned long hole_startk, int i) { - int ii; - device_t dev; - uint32_t base, limit; - uint32_t hoist; + int ii; + device_t dev; + uint32_t base, limit; + uint32_t hoist; uint32_t hole_sizek; - //1. find which node has hole - //2. change limit in that node. - //3. change base and limit in later node - //4. clear that node f0 + //1. find which node has hole + //2. change limit in that node. + //3. change base and limit in later node + //4. clear that node f0 //if there is not mem hole enabled, we need to change it's base instead hole_sizek = (4*1024*1024) - hole_startk; - for(ii=7;ii>i;ii--) { + for(ii=7;ii>i;ii--) { - base = f1_read_config32(0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } limit = f1_read_config32(0x44 + (ii << 3)); - f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); - f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); - } - limit = f1_read_config32(0x44 + (i << 3)); - f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); - dev = __f1_dev[i]; + f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); + f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); + dev = __f1_dev[i]; hoist = pci_read_config32(dev, 0xf0); if(hoist & 1) { pci_write_config32(dev, 0xf0, 0); @@ -844,35 +844,35 @@ base = pci_read_config32(dev, 0x40 + (i << 3)); f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2)); } - + } static uint32_t hoist_memory(unsigned long hole_startk, int i) { - int ii; - uint32_t carry_over; - device_t dev; - uint32_t base, limit; - uint32_t basek; - uint32_t hoist; + int ii; + uint32_t carry_over; + device_t dev; + uint32_t base, limit; + uint32_t basek; + uint32_t hoist; - carry_over = (4*1024*1024) - hole_startk; + carry_over = (4*1024*1024) - hole_startk; - for(ii=7;ii>i;ii--) { + for(ii=7;ii>i;ii--) { - base = f1_read_config32(0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } limit = f1_read_config32(0x44 + (ii << 3)); - f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); - f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); - } - limit = f1_read_config32(0x44 + (i << 3)); - f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); - dev = __f1_dev[i]; - base = pci_read_config32(dev, 0x40 + (i << 3)); - basek = (base & 0xffff0000) >> 2; + f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); + f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); + dev = __f1_dev[i]; + base = pci_read_config32(dev, 0x40 + (i << 3)); + basek = (base & 0xffff0000) >> 2; if(basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow //so need to change base reg instead, new basek will be 4*1024*1024 @@ -880,19 +880,19 @@ base |= (4*1024*1024)<<2; f1_write_config32(0x40 + (i<<3), base); } - else + else { - hoist = /* hole start address */ - ((hole_startk << 10) & 0xff000000) + - /* hole address to memory controller address */ - (((basek + carry_over) >> 6) & 0x0000ff00) + - /* enable */ - 1; - - pci_write_config32(dev, 0xf0, hoist); + hoist = /* hole start address */ + ((hole_startk << 10) & 0xff000000) + + /* hole address to memory controller address */ + (((basek + carry_over) >> 6) & 0x0000ff00) + + /* enable */ + 1; + + pci_write_config32(dev, 0xf0, hoist); } - return carry_over; + return carry_over; } #endif @@ -911,68 +911,68 @@ #endif #if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; + /* Place the IO devices somewhere safe */ + io = find_resource(dev, 0); + io->base = DEVICE_IO_START; #endif #if CONFIG_PCI_64BIT_PREF_MEM == 1 - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1); + mem2 = find_resource(dev, 2); #if 1 - printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); #endif - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } #if 1 - printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); #endif - last = &dev->resource[dev->resources]; - for(resource = &dev->resource[0]; resource < last; resource++) - { + last = &dev->resource[dev->resources]; + for(resource = &dev->resource[0]; resource < last; resource++) + { #if 1 - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; #endif - compute_allocate_resource(&dev->link[0], resource, - BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); + compute_allocate_resource(&dev->link[0], resource, + BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); - resource->flags |= IORESOURCE_STORED; - report_resource_stored(dev, resource, ""); + resource->flags |= IORESOURCE_STORED; + report_resource_stored(dev, resource, ""); - } + } #endif @@ -990,50 +990,50 @@ #endif #if HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek - * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - #if K8_REV_F_SUPPORT == 0 - if (!is_cpu_pre_e0()) { - #endif + /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek + * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + #if K8_REV_F_SUPPORT == 0 + if (!is_cpu_pre_e0()) { + #endif mem_hole = get_hw_mem_hole_info(); - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore - mmio_basek = mem_hole.hole_startk; + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore + mmio_basek = mem_hole.hole_startk; reset_memhole = 0; - } - + } + //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! - // We need to reset our Mem Hole, because We want more big HOLE than we already set - //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead - disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); + // We need to reset our Mem Hole, because We want more big HOLE than we already set + //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead + disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some - uint32_t basek_pri; - for (i = 0; i < 8; i++) { - uint32_t base; + uint32_t basek_pri; + for (i = 0; i < 8; i++) { + uint32_t base; uint32_t basek; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } basek = (base & 0xffff0000) >> 2; if(mmio_basek == basek) { - mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node - break; + mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node + break; } basek_pri = basek; - } - #endif - } + } + #endif + } #if K8_REV_F_SUPPORT == 0 } // is_cpu_pre_e0 @@ -1060,12 +1060,12 @@ idx += 0x10; basek = (8*64)+(16*16); sizek = limitk - ((8*64)+(16*16)); - + } - -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu - + +// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { if (basek <= mmio_basek) { @@ -1077,13 +1077,13 @@ sizek -= pre_sizek; } #if HW_MEM_HOLE_SIZEK != 0 - if(reset_memhole) + if(reset_memhole) #if K8_REV_F_SUPPORT == 0 - if(!is_cpu_pre_e0() ) + if(!is_cpu_pre_e0() ) #endif - sizek += hoist_memory(mmio_basek,i); + sizek += hoist_memory(mmio_basek,i); #endif - + basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -1108,8 +1108,8 @@ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); - + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); + /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe. */ @@ -1151,7 +1151,7 @@ int i,j; unsigned nb_cfg_54; unsigned siblings; - int e0_later_single_core; + int e0_later_single_core; int disable_siblings; nb_cfg_54 = 0; @@ -1179,19 +1179,19 @@ } sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1; - + if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; if(bsp_apicid == 0) { /* bsp apic id is not changed */ sysconf.apicid_offset = APIC_ID_OFFSET; - } else + } else { sysconf.lift_bsp_apicid = 1; - } - + } + } /* Find which cpus are present */ @@ -1233,25 +1233,25 @@ printk_debug(" %s siblings=%d\n", dev_path(dev), j); if(nb_cfg_54) { - // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... + // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... // ----> you can mixed single core e0 and dual core e0 at any sequence // That is the typical case - if(j == 0 ){ + if(j == 0 ){ #if K8_REV_F_SUPPORT == 0 - e0_later_single_core = is_e0_later_in_bsp(i); // single core + e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 #endif - } else { - e0_later_single_core = 0; - } - if(e0_later_single_core) { + } else { + e0_later_single_core = 0; + } + if(e0_later_single_core) { printk_debug("\tFound Rev E or Rev F later single core\r\n"); - j=1; + j=1; } - + if(siblings > j ) { } else { @@ -1261,27 +1261,27 @@ siblings = j; } } - + unsigned jj; if(e0_later_single_core || disable_siblings) { jj = 0; - } else + } else { jj = siblings; } -#if 0 +#if 0 jj = 0; // if create cpu core1 path in amd_siblings by core0 #endif - - for (j = 0; j <=jj; j++ ) { - + + for (j = 0; j <=jj; j++ ) { + /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - + /* See if I can find the cpu */ cpu = find_dev_path(cpu_bus, &cpu_path); - + /* Enable the cpu if I have the processor */ if (dev && dev->enabled) { if (!cpu) { @@ -1291,7 +1291,7 @@ cpu->enabled = 1; } } - + /* Disable the cpu if I don't have the processor */ if (cpu && (!dev || !dev->enabled)) { cpu->enabled = 0; @@ -1301,14 +1301,14 @@ if (cpu) { cpu->path.u.apic.node_id = i; cpu->path.u.apic.core_id = j; - if(sysconf.enabled_apic_ext_id) { - if(sysconf.lift_bsp_apicid) { + if(sysconf.enabled_apic_ext_id) { + if(sysconf.lift_bsp_apicid) { cpu->path.u.apic.apic_id += sysconf.apicid_offset; - } else + } else { - if (cpu->path.u.apic.apic_id != 0) - cpu->path.u.apic.apic_id += sysconf.apicid_offset; - } + if (cpu->path.u.apic.apic_id != 0) + cpu->path.u.apic.apic_id += sysconf.apicid_offset; + } } printk_debug("CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); @@ -1324,7 +1324,7 @@ initialize_cpus(&dev->link[0]); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(device_t dev) { } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -4,7 +4,7 @@ 2005.02 yhlu add E0 memory hole support */ #if K8_REV_F_SUPPORT == 1 - #include "raminit_f.c" + #include "raminit_f.c" #else #include <cpu/x86/mem.h> @@ -67,7 +67,7 @@ static int controller_present(const struct mem_controller *ctrl) { - return pci_read_config32(ctrl->f0, 0) == 0x11001022; + return pci_read_config32(ctrl->f0, 0) == 0x11001022; } #if RAMINIT_SYSINFO==1 @@ -198,7 +198,7 @@ * [29:21] Address Mask (33-25) * The bits with an address mask of 1 are excluded from address comparison * [31:30] Reserved - * + * */ PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000, PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000, @@ -211,7 +211,7 @@ /* DRAM Bank Address Mapping Register * F2:0x80 * Specify the memory module size - * [ 2: 0] CS1/0 + * [ 2: 0] CS1/0 * [ 6: 4] CS3/2 * [10: 8] CS5/4 * [14:12] CS7/6 @@ -222,7 +222,7 @@ * 100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10) * 101 = 1Gbyte (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12) * 110 = 2Gbyte (Rows = 14 & Col = 12) - * 111 = reserved + * 111 = reserved * [ 3: 3] Reserved * [ 7: 7] Reserved * [11:11] Reserved @@ -338,8 +338,8 @@ * 0 = Disabled * 1 = Enabled * [ 3: 3] Disable DQS Hystersis (FIXME handle this one carefully) - * 0 = Enable DQS input filter - * 1 = Disable DQS input filtering + * 0 = Enable DQS input filter + * 1 = Disable DQS input filtering * [ 7: 4] Reserved * [ 8: 8] DRAM_Init * 0 = Initialization done or not yet started. @@ -396,12 +396,12 @@ * 111 = Oldest entry in DCQ can be bypassed 7 times * [31:28] Reserved */ - PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| + PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, + (4 << 25)|(0 << 24)| + (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| + (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| + (2 << 14)|(0 << 13)|(0 << 12)| + (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| (0 << 3) |(0 << 1) |(0 << 0), /* DRAM Config High Register * F2:0x94 @@ -548,10 +548,10 @@ int max; #if 1 - if (!controller_present(ctrl)) { -// print_debug("No memory controller present\r\n"); - return; - } + if (!controller_present(ctrl)) { +// print_debug("No memory controller present\r\n"); + return; + } #endif print_spew("setting up CPU"); print_spew_hex8(ctrl->node_id); @@ -563,8 +563,8 @@ unsigned long reg; #if 0 #if CONFIG_USE_PRINTK_IN_CAR - prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]); - #else + prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]); + #else print_spew_hex32(register_values[i]); print_spew(" <-"); print_spew_hex32(register_values[i+2]); @@ -602,7 +602,7 @@ dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); - + } static int is_dual_channel(const struct mem_controller *ctrl) @@ -614,7 +614,7 @@ static int is_opteron(const struct mem_controller *ctrl) { - /* Test to see if I am an Opteron. + /* Test to see if I am an Opteron. * FIXME Socket 939 based Athlon64 have dual channel capability, * too, so we need a better test for Opterons */ @@ -684,7 +684,7 @@ if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -743,20 +743,20 @@ if (sz.side1 != sz.side2) { sz.side2 = 0; } - + /* For each base register. * Place the dimm size in 32 MB quantities in the bits 31 - 21. * The initialize dimm size is in bits. * Set the base enable bit0. */ - + base0 = base1 = 0; /* Make certain side1 of the dimm is at least 32MB */ if (sz.side1 >= (25 +3)) { base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1; } - + /* Make certain side2 of the dimm is at least 32MB */ if (sz.side2 >= (25 + 3)) { base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1; @@ -810,9 +810,9 @@ map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { - map &= ~(0xf << ( (index + 2) * 4)); - } + if(sz.rank == 4) { + map &= ~(0xf << ( (index + 2) * 4)); + } #endif @@ -821,29 +821,29 @@ if(is_cpu_pre_d0()) { map |= (sz.side1 - (25 + 3)) << (index *4); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { - map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); - } + if(sz.rank == 4) { + map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); + } #endif } else { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { - map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); - } + if(sz.rank == 4) { + map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); + } #endif } } pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map); - + } static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; - + for(i = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (!(dimm_mask & (1 << i))) { @@ -913,11 +913,11 @@ */ if (tom_k >= 0x003f0000) { #if HW_MEM_HOLE_SIZEK != 0 - if(hole_startk != 0) { - tom_k = hole_startk; - } else + if(hole_startk != 0) { + tom_k = hole_startk; + } else #endif - tom_k = 0x3f0000; + tom_k = 0x3f0000; } msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; @@ -927,29 +927,29 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) { /* 35 - 25 */ - static const uint8_t csbase_low_shift[] = { + static const uint8_t csbase_low_shift[] = { /* 32MB */ (13 - 4), /* 64MB */ (14 - 4), - /* 128MB */ (14 - 4), + /* 128MB */ (14 - 4), /* 256MB */ (15 - 4), /* 512MB */ (15 - 4), /* 1GB */ (16 - 4), - /* 2GB */ (16 - 4), + /* 2GB */ (16 - 4), }; - static const uint8_t csbase_low_d0_shift[] = { - /* 32MB */ (13 - 4), - /* 64MB */ (14 - 4), - /* 128MB */ (14 - 4), + static const uint8_t csbase_low_d0_shift[] = { + /* 32MB */ (13 - 4), + /* 64MB */ (14 - 4), + /* 128MB */ (14 - 4), /* 128MB */ (15 - 4), - /* 256MB */ (15 - 4), - /* 512MB */ (15 - 4), - /* 256MB */ (16 - 4), - /* 512MB */ (16 - 4), - /* 1GB */ (16 - 4), + /* 256MB */ (15 - 4), + /* 512MB */ (15 - 4), + /* 256MB */ (16 - 4), + /* 512MB */ (16 - 4), + /* 1GB */ (16 - 4), /* 1GB */ (17 - 4), - /* 2GB */ (17 - 4), - }; + /* 2GB */ (17 - 4), + }; /* cs_base_high is not changed */ @@ -970,9 +970,9 @@ unsigned size; unsigned cs_mode; uint32_t value; - + value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); - + /* Is it enabled? */ if (!(value & 1)) { continue; @@ -988,15 +988,15 @@ } value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - cs_mode =( value >> ((index>>1)*4)) & 0xf; - if(cs_mode == 0 ) continue; - if(common_cs_mode == 0) { - common_cs_mode = cs_mode; - } - /* The size differed fail */ - if(common_cs_mode != cs_mode) { - return 0; - } + cs_mode =( value >> ((index>>1)*4)) & 0xf; + if(cs_mode == 0 ) continue; + if(common_cs_mode == 0) { + common_cs_mode = cs_mode; + } + /* The size differed fail */ + if(common_cs_mode != cs_mode) { + return 0; + } } /* Chip selects can only be interleaved when there is @@ -1011,26 +1011,26 @@ if(is_cpu_pre_d0()){ csbase_inc = 1 << csbase_low_shift[common_cs_mode]; if(is_dual_channel(ctrl)) { - /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ - if ((bits == 3) && (common_size == (1 << (32 - 3)))) { -// print_debug("8 4GB chip selects cannot be interleaved\r\n"); - return 0; - } + /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ + if ((bits == 3) && (common_size == (1 << (32 - 3)))) { +// print_debug("8 4GB chip selects cannot be interleaved\r\n"); + return 0; + } csbase_inc <<=1; } } else { csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; if(is_dual_channel(ctrl)) { - if( (bits==3) && (common_cs_mode > 8)) { -// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n"); - return 0; + if( (bits==3) && (common_cs_mode > 8)) { +// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n"); + return 0; } csbase_inc <<=1; - } + } } - /* Compute the initial values for csbase and csbask. + /* Compute the initial values for csbase and csbask. * In csbase just set the enable bit and the base to zero. * In csmask set the mask bits for the size and page level interleave. */ @@ -1049,7 +1049,7 @@ pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask); csbase += csbase_inc; } - + print_spew("Interleaved\r\n"); /* Return the memory size in K */ @@ -1077,12 +1077,12 @@ if (!(value & 1)) { continue; } - + /* Is it greater? */ if (value <= csbase) { continue; } - + /* Has it already been selected */ if (tom & (1 << (index + 24))) { continue; @@ -1116,7 +1116,7 @@ pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase); /* Write the new mask register */ pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask); - + } /* Return the memory size in K */ return (tom & ~0xff000000) << 15; @@ -1164,8 +1164,8 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) { - print_debug("disabling dimm"); - print_debug_hex8(index); + print_debug("disabling dimm"); + print_debug_hex8(index); print_debug("\r\n"); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); @@ -1194,7 +1194,7 @@ /* Registered dimm ? */ if (value & (1 << 1)) { registered = 1; - } + } /* Otherwise it must be an unbuffered dimm */ else { unbuffered = 1; @@ -1209,9 +1209,9 @@ if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */ - + /* set DCL_En2T if you have non-equal DDR mem types! */ - + if ((cpuid_eax(1) & 0x30) == 0x30) { /* CS[7:4] is copy of CS[3:0], should be set for 939 socket */ dcl |= DCL_UpperCSMap; @@ -1286,7 +1286,7 @@ }; /* If the dimms are not in pairs do not do dual channels */ if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) != - ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { + ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } /* If the cpu is not capable of doing dual channels don't do dual channels */ @@ -1521,7 +1521,7 @@ /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. */ - + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int latencies; int latency; @@ -1551,12 +1551,12 @@ if ((latency != min_latency) || (index >= 3)) { goto dimm_err; } - + /* Read the min_cycle_time for this latency */ value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); if (value < 0) goto hw_error; - - /* All is good if the selected clock speed + + /* All is good if the selected clock speed * is what I need or slower. */ if (value <= min_cycle_time) { @@ -1571,12 +1571,12 @@ #if QRANK_DIMM_SUPPORT if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) { int ranks = 4; - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); + if (!(dimm_mask & (1 << i))) { + continue; + } + val = spd_read_byte(ctrl->channel0[i], 5); if(val!=ranks) { ranks = val; break; @@ -1587,7 +1587,7 @@ min_cycle_time = 0x60; } } - + } #endif #endif @@ -1615,7 +1615,7 @@ value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); - + result.dimm_mask = dimm_mask; return result; hw_error: @@ -1844,9 +1844,9 @@ } #if QRANK_DIMM_SUPPORT == 1 - rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */ + rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */ if (rank < 0) { - return -1; + return -1; } #endif @@ -1943,7 +1943,7 @@ if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) { die("Unknown Trwt\r\n"); } - + dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT); dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT); @@ -2022,7 +2022,7 @@ if (dimms == 4) { /* 9ns */ async_lat = 9; - } + } else { /* 8ns */ async_lat = 8; @@ -2059,7 +2059,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask) { int i; - + init_Tref(ctrl, param); for(i = 0; i < DIMM_SOCKETS; i++) { int rc; @@ -2076,8 +2076,8 @@ /* DRAM Timing High Register */ if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err; - + /* DRAM Config Low */ if ((rc = update_dimm_x4 (ctrl, param, i)) <= 0) goto dimm_err; if ((rc = update_dimm_ecc(ctrl, param, i)) <= 0) goto dimm_err; @@ -2104,9 +2104,9 @@ } #if RAMINIT_SYSINFO==1 -static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) #endif { struct spd_set_memclk_result result; @@ -2125,19 +2125,19 @@ print_debug("No memory for this cpu\r\n"); return; } - dimm_mask = spd_enable_2channels(ctrl, dimm_mask); - if (dimm_mask < 0) + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); + if (dimm_mask < 0) goto hw_spd_err; - dimm_mask = spd_set_ram_size(ctrl , dimm_mask); - if (dimm_mask < 0) + dimm_mask = spd_set_ram_size(ctrl , dimm_mask); + if (dimm_mask < 0) goto hw_spd_err; - dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask); - if (dimm_mask < 0) + dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask); + if (dimm_mask < 0) goto hw_spd_err; result = spd_set_memclk(ctrl, dimm_mask); param = result.param; dimm_mask = result.dimm_mask; - if (dimm_mask < 0) + if (dimm_mask < 0) goto hw_spd_err; dimm_mask = spd_set_dram_timing(ctrl, param , dimm_mask); if (dimm_mask < 0) @@ -2154,108 +2154,108 @@ #if HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { - int ii; - uint32_t carry_over; - device_t dev; - uint32_t base, limit; - uint32_t basek; - uint32_t hoist; - int j; + int ii; + uint32_t carry_over; + device_t dev; + uint32_t base, limit; + uint32_t basek; + uint32_t hoist; + int j; - carry_over = (4*1024*1024) - hole_startk; + carry_over = (4*1024*1024) - hole_startk; - for(ii=controllers - 1;ii>i;ii--) { - base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + for(ii=controllers - 1;ii>i;ii--) { + base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); - for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); - pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); - } - } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); - for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); - } - dev = ctrl[i].f1; - base = pci_read_config32(dev, 0x40 + (i << 3)); - basek = (base & 0xffff0000) >> 2; - if(basek == hole_startk) { - //don't need set memhole here, because hole off set will be 0, overflow - //so need to change base reg instead, new basek will be 4*1024*1024 - base &= 0x0000ffff; - base |= (4*1024*1024)<<2; - for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); - } - } + for(j = 0; j < controllers; j++) { + pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); + pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); + } + } + limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + for(j = 0; j < controllers; j++) { + pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); + } + dev = ctrl[i].f1; + base = pci_read_config32(dev, 0x40 + (i << 3)); + basek = (base & 0xffff0000) >> 2; + if(basek == hole_startk) { + //don't need set memhole here, because hole off set will be 0, overflow + //so need to change base reg instead, new basek will be 4*1024*1024 + base &= 0x0000ffff; + base |= (4*1024*1024)<<2; + for(j = 0; j < controllers; j++) { + pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); + } + } else { - hoist = /* hole start address */ - ((hole_startk << 10) & 0xff000000) + - /* hole address to memory controller address */ - (((basek + carry_over) >> 6) & 0x0000ff00) + - /* enable */ - 1; - pci_write_config32(dev, 0xf0, hoist); + hoist = /* hole start address */ + ((hole_startk << 10) & 0xff000000) + + /* hole address to memory controller address */ + (((basek + carry_over) >> 6) & 0x0000ff00) + + /* enable */ + 1; + pci_write_config32(dev, 0xf0, hoist); } - return carry_over; + return carry_over; } static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) { - uint32_t hole_startk; - int i; + uint32_t hole_startk; + int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. - * If it is equal to the dram base address in K (base_k), + * If it is equal to the dram base address in K (base_k), * we need to decrease it. */ - uint32_t basek_pri; - for(i=0; i<controllers; i++) { - uint32_t base; - unsigned base_k; - base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - base_k = (base & 0xffff0000) >> 2; - if(base_k == hole_startk) { + uint32_t basek_pri; + for(i=0; i<controllers; i++) { + uint32_t base; + unsigned base_k; + base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + base_k = (base & 0xffff0000) >> 2; + if(base_k == hole_startk) { /* decrease memory hole startk to make sure it is - * in the middle of the previous node + * in the middle of the previous node */ - hole_startk -= (base_k - basek_pri)>>1; - break; /* only one hole */ - } - basek_pri = base_k; - } + hole_startk -= (base_k - basek_pri)>>1; + break; /* only one hole */ + } + basek_pri = base_k; + } #endif - /* Find node number that needs the memory hole configured */ - for(i=0; i<controllers; i++) { - uint32_t base, limit; - unsigned base_k, limit_k; - base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); - base_k = (base & 0xffff0000) >> 2; - limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + /* Find node number that needs the memory hole configured */ + for(i=0; i<controllers; i++) { + uint32_t base, limit; + unsigned base_k, limit_k; + base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + base_k = (base & 0xffff0000) >> 2; + limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; if ((base_k <= hole_startk) && (limit_k > hole_startk)) { - unsigned end_k; - hoist_memory(controllers, ctrl, hole_startk, i); - end_k = memory_end_k(ctrl, controllers); - set_top_mem(end_k, hole_startk); - break; /* only one hole */ - } - } + unsigned end_k; + hoist_memory(controllers, ctrl, hole_startk, i); + end_k = memory_end_k(ctrl, controllers); + set_top_mem(end_k, hole_startk); + break; /* only one hole */ + } + } } @@ -2369,10 +2369,10 @@ } #if HW_MEM_HOLE_SIZEK != 0 - // init hw mem hole here - /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ + // init hw mem hole here + /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ if(!is_cpu_pre_e0()) - set_hw_mem_hole(controllers, ctrl); + set_hw_mem_hole(controllers, ctrl); #endif //FIXME add enable node interleaving here -- yhlu @@ -2396,7 +2396,7 @@ /* The first 1M is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); - + print_debug(" done\r\n"); #endif } @@ -2408,24 +2408,24 @@ static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) { - int i; - int j; - struct mem_controller *ctrl; - for(i=0;i<controllers; i++) { - ctrl = &ctrl_a[i]; - ctrl->node_id = i; - ctrl->f0 = PCI_DEV(0, 0x18+i, 0); - ctrl->f1 = PCI_DEV(0, 0x18+i, 1); - ctrl->f2 = PCI_DEV(0, 0x18+i, 2); - ctrl->f3 = PCI_DEV(0, 0x18+i, 3); + int i; + int j; + struct mem_controller *ctrl; + for(i=0;i<controllers; i++) { + ctrl = &ctrl_a[i]; + ctrl->node_id = i; + ctrl->f0 = PCI_DEV(0, 0x18+i, 0); + ctrl->f1 = PCI_DEV(0, 0x18+i, 1); + ctrl->f2 = PCI_DEV(0, 0x18+i, 2); + ctrl->f3 = PCI_DEV(0, 0x18+i, 3); - if(spd_addr == (void *)0) continue; + if(spd_addr == (void *)0) continue; - for(j=0;j<DIMM_SOCKETS;j++) { - ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; - ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; - } - } + for(j=0;j<DIMM_SOCKETS;j++) { + ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; + ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; + } + } } #endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -21,14 +21,14 @@ //0: mean no debug info #define DQS_TRAIN_DEBUG 0 -static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) +static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x\r\n", str, val); #else - print_debug(str); print_debug_hex32(val); print_debug("\r\n"); + print_debug(str); print_debug_hex32(val); print_debug("\r\n"); #endif } #endif @@ -37,36 +37,36 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const char *str2, unsigned val2, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if(DQS_TRAIN_DEBUG > level) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); - #else - print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); - #endif - } + printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); + #else + print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); + #endif + } #endif } static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val, unsigned val2, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if(DQS_TRAIN_DEBUG > level) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else + printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); + #else print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif - } + #endif + } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); - #else - print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); - #endif + printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); + #else + print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); + #endif } @@ -74,13 +74,13 @@ { int i; - sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); + sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); for(i=0;i<8; i++) { sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); } - sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0); + sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0); } static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo) @@ -89,7 +89,7 @@ uint32_t mem_base; unsigned nodeid = ctrl->node_id; -#if HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 uint32_t hole_reg; #endif @@ -107,17 +107,17 @@ if(hole_reg & 1) { unsigned hole_startk; hole_startk = (hole_reg & (0xff<<24)) >> 10; - if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { + if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { dword += ((4*1024*1024 - hole_startk)<<2); } - } + } #endif //add 1MB offset to avoid compat area dword += (1<<(20-8)); - - //So final result is upper 32 bit addr - + + //So final result is upper 32 bit addr + return dword; } @@ -130,14 +130,14 @@ static inline unsigned long read_cr4(void) { - unsigned long cr4; - asm volatile ("movl %%cr4, %0" : "=r" (cr4)); - return cr4; + unsigned long cr4; + asm volatile ("movl %%cr4, %0" : "=r" (cr4)); + return cr4; } static inline void write_cr4(unsigned long cr4) { - asm volatile ("movl %0, %%cr4" : : "r" (cr4)); + asm volatile ("movl %0, %%cr4" : : "r" (cr4)); } @@ -151,55 +151,55 @@ static inline void disable_sse2() { - unsigned long cr4; - cr4 = read_cr4(); - cr4 &= ~(1<<9); - write_cr4(cr4); + unsigned long cr4; + cr4 = read_cr4(); + cr4 &= ~(1<<9); + write_cr4(cr4); } static void set_wrap32dis(void) { msr_t msr; - + msr = rdmsr(0xc0010015); msr.lo |= (1<<17); - + wrmsr(0xc0010015, msr); } static void clear_wrap32dis(void) { - msr_t msr; + msr_t msr; - msr = rdmsr(0xc0010015); - msr.lo &= ~(1<<17); + msr = rdmsr(0xc0010015); + msr.lo &= ~(1<<17); - wrmsr(0xc0010015, msr); + wrmsr(0xc0010015, msr); } static void set_FSBASE(uint32_t addr_hi) { - msr_t msr; + msr_t msr; - //set fs and use fs prefix to access the mem - msr.hi = addr_hi; - msr.lo = 0; - wrmsr(0xc0000100, msr); //FS_BASE + //set fs and use fs prefix to access the mem + msr.hi = addr_hi; + msr.lo = 0; + wrmsr(0xc0000100, msr); //FS_BASE } static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo) { - unsigned enabled; + unsigned enabled; unsigned nodeid = ctrl->node_id; - - enabled = sysinfo->cs_base[nodeid * 8 + cs_idx]; - enabled &= 1; - return enabled; + enabled = sysinfo->cs_base[nodeid * 8 + cs_idx]; + enabled &= 1; + return enabled; + } static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, int cs_idx, unsigned is_Width128, struct sys_info *sysinfo) @@ -209,21 +209,21 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_num) { - __asm__ volatile ( - "1:\n\t" + __asm__ volatile ( + "1:\n\t" "movdqa (%3), %%xmm0\n\t" "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" - :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) - ); + :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) + ); } -static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) +static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) { uint8_t *buf; if(p==1) { buf = buf_b; } @@ -234,18 +234,18 @@ WriteLNTestPattern(addr<<8, buf, 1); } -static void Read1LTestPattern(unsigned addr) +static void Read1LTestPattern(unsigned addr) { - unsigned value; + unsigned value; set_FSBASE(addr>>24); - + /* 1st move causes read fill (to exclusive or shared)*/ - __asm__ volatile ( - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr<<8) - ); - + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr<<8) + ); + } #define DQS_PASS 0 @@ -283,42 +283,42 @@ test_buf = (uint32_t *)TestPattern2; } - set_FSBASE(addr>>24); - + set_FSBASE(addr>>24); + addr_lo = addr<<8; - + if(is_Width128 && (channel == 1)) { addr_lo += 8; //second channel test_buf += 2; } - - __asm__ volatile ( - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + value_test = *test_buf; - - print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); - print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4); + print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); + print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4); + if(value == value_test) { addr_lo += 4; test_buf++; - __asm__ volatile ( - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); - value_test = *test_buf; - print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); - print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + value_test = *test_buf; + print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); + print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); if(value == value_test){ result = DQS_PASS; } } - + if(Pass == DQS_SECOND_PASS) { // second pass need to be inverted if(result==DQS_PASS) { result = DQS_FAIL; @@ -332,25 +332,25 @@ } -static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly) +static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly) { - uint32_t reg; + uint32_t reg; dly += (20-1); // round it dly /= 20; // convert from unit 50ps to 1ns - + dly += 6; - reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); - reg &= ~(DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT); - reg |= ((dly - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT); - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, reg); - + reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + reg &= ~(DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT); + reg |= ((dly - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT); + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, reg); + } /* - Set the Target range to WT IO (using an IORR overlapping the already existing + Set the Target range to WT IO (using an IORR overlapping the already existing WB dram type). Use IORR0 */ static void SetTargetWTIO(unsigned addr) @@ -359,19 +359,19 @@ msr.hi = addr>>24; msr.lo = addr<<8; wrmsr(0xc0010016, msr); //IORR0 BASE - + msr.hi = 0xff; msr.lo = 0xfc000800; // 64MB Mask - wrmsr(0xc0010017, msr); // IORR0 Mask + wrmsr(0xc0010017, msr); // IORR0 Mask } static void ResetTargetWTIO(void) { - msr_t msr; + msr_t msr; - msr.hi = 0; - msr.lo = 0; - wrmsr(0xc0010017, msr); // IORR0 Mask + msr.hi = 0; + msr.lo = 0; + wrmsr(0xc0010017, msr); // IORR0 Mask } static void proc_CLFLUSH(unsigned addr) @@ -379,13 +379,13 @@ set_FSBASE(addr>>24); - /* 1st move causes read fill (to exclusive or shared)*/ - __asm__ volatile ( + /* 1st move causes read fill (to exclusive or shared)*/ + __asm__ volatile ( /* clflush fs:[eax] */ "clflush %%fs:(%0)\n\t" - ::"a" (addr<<8) - ); - + ::"a" (addr<<8) + ); + } static void proc_IOCLFLUSH(unsigned addr) { @@ -411,39 +411,39 @@ static uint16_t get_exact_T1000(unsigned i) { - // 200 266, 333, 400 + // 200 266, 333, 400 static const uint16_t T1000_a[]= { 5000, 3759, 3003, 2500 }; - static const uint16_t TT_a[] = { - /*200 266 333 400 */ - /*4 */ 6250, 6250, 6250, 6250, - /*5 */ 5000, 5000, 5000, 2500, - /*6 */ 5000, 4166, 4166, 2500, - /*7 */ 5000, 4285, 3571, 2500, + static const uint16_t TT_a[] = { + /*200 266 333 400 */ + /*4 */ 6250, 6250, 6250, 6250, + /*5 */ 5000, 5000, 5000, 2500, + /*6 */ 5000, 4166, 4166, 2500, + /*7 */ 5000, 4285, 3571, 2500, - /*8 */ 5000, 3750, 3125, 2500, - /*9 */ 5000, 3888, 3333, 2500, - /*10*/ 5000, 4000, 3000, 2500, - /*11*/ 5000, 4090, 3181, 2500, + /*8 */ 5000, 3750, 3125, 2500, + /*9 */ 5000, 3888, 3333, 2500, + /*10*/ 5000, 4000, 3000, 2500, + /*11*/ 5000, 4090, 3181, 2500, - /*12*/ 5000, 3750, 3333, 2500, - /*13*/ 5000, 3846, 3076, 2500, - /*14*/ 5000, 3928, 3214, 2500, - /*15*/ 5000, 4000, 3000, 2500, - }; + /*12*/ 5000, 3750, 3333, 2500, + /*13*/ 5000, 3846, 3076, 2500, + /*14*/ 5000, 3928, 3214, 2500, + /*15*/ 5000, 4000, 3000, 2500, + }; - unsigned fid_cur; - int index; + unsigned fid_cur; + int index; - msr_t msr; - msr = rdmsr(0xc0010042); - fid_cur = msr.lo & 0x3f; + msr_t msr; + msr = rdmsr(0xc0010042); + fid_cur = msr.lo & 0x3f; - index = fid_cur>>1; + index = fid_cur>>1; - if(index>12) return T1000_a[i]; + if(index>12) return T1000_a[i]; - return TT_a[index * 4+i]; + return TT_a[index * 4+i]; } @@ -451,24 +451,24 @@ { int i; uint32_t dword; - + dword = 0x00000000; for(i=1; i<=3; i++) { - /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ - pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); + /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ + pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); } - dword = 0x2f2f2f2f; - for(i=5; i<=7; i++) { - /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ - pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); - pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); - } + dword = 0x2f2f2f2f; + for(i=5; i<=7; i++) { + /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ + pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); + } } -#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND +#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 #endif @@ -481,21 +481,21 @@ 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; - static const uint32_t TestPattern1[] = { - 0x55555555, 0x55555555, 0x55555555, 0x55555555, + static const uint32_t TestPattern1[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; - static const uint32_t TestPattern2[] = { + static const uint32_t TestPattern2[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, - 0x40385642, 0x38465245, 0x29432163, 0x05067894, - 0x12349045, 0x98723467, 0x12387634, 0x34587623, + 0x40385642, 0x38465245, 0x29432163, 0x05067894, + 0x12349045, 0x98723467, 0x12387634, 0x34587623, }; - uint8_t pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ - uint8_t *buf_a, *buf_b; + uint8_t pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ + uint8_t *buf_a, *buf_b; uint32_t ecc_bit; uint32_t dword; uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8 @@ -543,14 +543,14 @@ //disable ECC temp dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); ecc_bit = dword & DCL_DimmEccEn; - dword &= ~(DCL_DimmEccEn); + dword &= ~(DCL_DimmEccEn); pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); if(Pass == DQS_FIRST_PASS) { #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 cpu_f0_f1 = is_cpu_pre_f2_in_bsp(ctrl->node_id); - if(!cpu_f0_f1) + if(!cpu_f0_f1) #endif { #if 1 @@ -566,27 +566,27 @@ dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dword &= DCH_MemClkFreq_MASK; - T1000 = get_exact_T1000(dword); + T1000 = get_exact_T1000(dword); - // SetupRcvrPattern + // SetupRcvrPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); - buf_b = buf_a + 128; //?? + buf_b = buf_a + 128; //?? if(Pass==DQS_FIRST_PASS) { - for(i=0;i<16;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; - *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; - } + for(i=0;i<16;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; + *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; + } } else { - for(i=0;i<16;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; + for(i=0;i<16;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; - } + } } print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); - print_debug_addr("TrainRcvEn: buf_a:", buf_a); + print_debug_addr("TrainRcvEn: buf_a:", buf_a); Errors = 0; /* for each channel */ @@ -606,10 +606,10 @@ /* there are four recriver pairs, loosely associated with CS */ for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { - + unsigned index=(receiver>>1) * 3 + 0x10; - print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2); + print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2); if(is_Width128) { if(channel) { @@ -618,22 +618,22 @@ } } else { - if(channel) { + if(channel) { index += 0x20; } - } + } LastTest = DQS_FAIL; RcvrEnDlyRmin = 0xaf; - + if(!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue; /* for each DQS receiver enable setting */ - + TestAddr0 = Get_RcvrSysAddr(ctrl, channel, receiver, sysinfo); TestAddr0B = TestAddr0 + (1<<(20+2-8)); // 4MB - + if(RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) { TestAddr1 = Get_RcvrSysAddr(ctrl, channel, receiver+1, sysinfo); TestAddr1B = TestAddr1 + (1<<(20+2-8)); //4MB @@ -643,7 +643,7 @@ two_ranks = 0; } - print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2); + print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2); Write1LTestPattern(TestAddr0, 0, buf_a, buf_b); // rank0 of dimm, test p0 Write1LTestPattern(TestAddr0B, 1, buf_a, buf_b); //rank0 of dimm, test p1 @@ -654,13 +654,13 @@ } if(Pass == DQS_FIRST_PASS) { - RcvrEnDly = 0; + RcvrEnDly = 0; } else { RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver]; } while ( RcvrEnDly < 0xaf) { // Sweep Delay value here - print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); + print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); if(RcvrEnDly & 1) { /* Odd steps get another pattern such that even @@ -680,15 +680,15 @@ /* Program current Receiver enable delay */ pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); /* FIXME: 64bit MUX */ - + if(is_Width128) { /* Program current Receiver enable delay chaannel b */ pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly); } - - /* Program the MaxAsyncLat filed with the - current DQS receiver enable setting plus 6ns - */ + + /* Program the MaxAsyncLat filed with the + current DQS receiver enable setting plus 6ns + */ /*Porgram MaxAsyncLat to correspond with current delay */ SetMaxAL_RcvrDly(ctrl, RcvrEnDly); @@ -701,36 +701,36 @@ ResetDCTWrPtr(ctrl); - print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3); + print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3); if(Test0 == DQS_PASS) { Read1LTestPattern(TestAddr0B); - Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr0B); ResetDCTWrPtr(ctrl); - print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3); - + print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3); + if(Test1 == DQS_PASS) { if(two_ranks) { Read1LTestPattern(TestAddr1); - Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); - proc_IOCLFLUSH(TestAddr1); - ResetDCTWrPtr(ctrl); + Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + proc_IOCLFLUSH(TestAddr1); + ResetDCTWrPtr(ctrl); - if(Test0 == DQS_PASS) { - Read1LTestPattern(TestAddr1B); - Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); - proc_IOCLFLUSH(TestAddr1B); - ResetDCTWrPtr(ctrl); + if(Test0 == DQS_PASS) { + Read1LTestPattern(TestAddr1B); + Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + proc_IOCLFLUSH(TestAddr1B); + ResetDCTWrPtr(ctrl); - if(Test1 == DQS_PASS) { - CurrTest = DQS_PASS; - } - } - print_debug_dqs("\t\t\tTrainRcvEn544: Test0 ", Test0, 3); + if(Test1 == DQS_PASS) { + CurrTest = DQS_PASS; + } + } + print_debug_dqs("\t\t\tTrainRcvEn544: Test0 ", Test0, 3); } else { CurrTest = DQS_PASS; @@ -738,7 +738,7 @@ } } - print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3); + print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3); if(CurrTest == DQS_PASS) { if(LastTest == DQS_FAIL) { @@ -746,61 +746,61 @@ break; } } - + LastTest = CurrTest; - + /* swap the rank 0 pointers */ tmp = TestAddr0; TestAddr0 = TestAddr0B; TestAddr0B = tmp; /* swap the rank 1 pointers */ - tmp = TestAddr1; - TestAddr1 = TestAddr1B; - TestAddr1B = tmp; + tmp = TestAddr1; + TestAddr1 = TestAddr1B; + TestAddr1B = tmp; - print_debug_dqs("\t\t\tTrainRcvEn56: RcvrEnDly ", RcvrEnDly, 3); - + print_debug_dqs("\t\t\tTrainRcvEn56: RcvrEnDly ", RcvrEnDly, 3); + RcvrEnDly++; - + } // while RcvrEnDly - print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); + print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); if(RcvrEnDlyRmin == 0xaf) { //no passing window Errors |= SB_NORCVREN; } - if(Pass == DQS_FIRST_PASS) { - // We need a better value for DQSPos trainning - RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; - } else { - RcvrEnDly = RcvrEnDlyRmin; - } + if(Pass == DQS_FIRST_PASS) { + // We need a better value for DQSPos trainning + RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; + } else { + RcvrEnDly = RcvrEnDlyRmin; + } - if(RcvrEnDly > 0xae) { - //passing window too narrow, too far delayed - Errors |= SB_SmallRCVR; - RcvrEnDly = 0xae; - } + if(RcvrEnDly > 0xae) { + //passing window too narrow, too far delayed + Errors |= SB_SmallRCVR; + RcvrEnDly = 0xae; + } - if(Pass == DQS_SECOND_PASS) { //second pass must average vales - RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/; - RcvrEnDly >>= 1; - } - - dqs_rcvr_dly_a[channel * 8 + receiver] = RcvrEnDly; - - //Set final RcvrEnDly for this DIMM and Channel + if(Pass == DQS_SECOND_PASS) { //second pass must average vales + RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/; + RcvrEnDly >>= 1; + } + + dqs_rcvr_dly_a[channel * 8 + receiver] = RcvrEnDly; + + //Set final RcvrEnDly for this DIMM and Channel pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); - + if(is_Width128) { pci_write_config32_index_wait(ctrl->f2, 0x98, index+0x20, RcvrEnDly); // channel B - if(channel) { + if(channel) { pci_write_config32_index_wait(ctrl->f2, 0x98, index, CurrRcvrCHADelay); if(RcvrEnDly > CurrRcvrCHADelay) { - dword = RcvrEnDly - CurrRcvrCHADelay; + dword = RcvrEnDly - CurrRcvrCHADelay; } else { dword = CurrRcvrCHADelay - RcvrEnDly; @@ -812,53 +812,53 @@ } } - print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2); + print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2); if(RcvrEnDly > CTLRMaxDelay) { CTLRMaxDelay = RcvrEnDly; } - print_debug_dqs("\t\tTrainRcvEn64: CTLRMaxDelay ", CTLRMaxDelay, 2); - + print_debug_dqs("\t\tTrainRcvEn64: CTLRMaxDelay ", CTLRMaxDelay, 2); + } /* receiver */ } /* channel */ - print_debug_dqs("\tTrainRcvEn65: CTLRMaxDelay ", CTLRMaxDelay, 1); + print_debug_dqs("\tTrainRcvEn65: CTLRMaxDelay ", CTLRMaxDelay, 1); - /* Program the MaxAsysncLat field with the largest DQS Receiver Enable setting */ + /* Program the MaxAsysncLat field with the largest DQS Receiver Enable setting */ SetMaxAL_RcvrDly(ctrl, CTLRMaxDelay); ResetDCTWrPtr(ctrl); - //Enable ECC again - dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - dword &= ~(DCL_DimmEccEn); + //Enable ECC again + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dword &= ~(DCL_DimmEccEn); dword |= ecc_bit; - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); if(Pass == DQS_FIRST_PASS) { #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 - if(!cpu_f0_f1) + if(!cpu_f0_f1) #endif { dword = pci_read_config32(ctrl->f2, DRAM_CTRL); - dword &= ~DC_DqsRcvEnTrain; - pci_write_config32(ctrl->f2, DRAM_CTRL, dword); + dword &= ~DC_DqsRcvEnTrain; + pci_write_config32(ctrl->f2, DRAM_CTRL, dword); } } - //Clear wrap32dis + //Clear wrap32dis clear_wrap32dis(); //restore SSE2 setting disable_sse2(); -#if MEM_TRAIN_SEQ != 1 +#if MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ #if CONFIG_USE_PRINTK_IN_CAR printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay); #else - print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); + print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); #endif #endif @@ -872,20 +872,20 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, unsigned bytelane, unsigned direction, unsigned dqs_delay) { //ByteLane could be 0-8, last is for ECC - unsigned index; - uint32_t dword; + unsigned index; + uint32_t dword; unsigned shift; - dqs_delay &= 0xff; + dqs_delay &= 0xff; - index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); + index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); shift = bytelane; while(shift>3) { shift-=4; } shift <<= 3; // 8 bit - dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); + dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); dword &= ~(0x3f<<shift); dword |= (dqs_delay<<shift); pci_write_config32_index_wait(ctrl->f2, 0x98, index, dword); @@ -897,10 +897,10 @@ unsigned index; uint32_t dword; int i; - + dword = 0; dqs_delay &= 0xff; - for(i=0;i<4;i++) { + for(i=0;i<4;i++) { dword |= dqs_delay<<(i*8); } @@ -909,7 +909,7 @@ for(i=0; i<2; i++) { pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); } - + } static unsigned MiddleDQS(unsigned min_d, unsigned max_d) @@ -924,7 +924,7 @@ static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay) { - dqs_delay_a[channel * 2*9 + direction * 9 + bytelane] = dqs_delay; + dqs_delay_a[channel * 2*9 + direction * 9 + bytelane] = dqs_delay; } static void WriteDQSTestPattern(unsigned addr_lo, unsigned pattern , uint8_t *buf_a) @@ -932,58 +932,58 @@ WriteLNTestPattern(addr_lo, buf_a, (pattern+1) * 9); } -static void ReadL18TestPattern(unsigned addr_lo) +static void ReadL18TestPattern(unsigned addr_lo) { - //set fs and use fs prefix to access the mem - __asm__ volatile ( - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + //set fs and use fs prefix to access the mem + __asm__ volatile ( + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line "movl %%fs:-64(%%esi), %%eax\n\t" //+1 "movl %%fs:(%%esi), %%eax\n\t" //+2 "movl %%fs:64(%%esi), %%eax\n\t" //+3 - "movl %%fs:-128(%%edi), %%eax\n\t" //+4 - "movl %%fs:-64(%%edi), %%eax\n\t" //+5 - "movl %%fs:(%%edi), %%eax\n\t" //+6 - "movl %%fs:64(%%edi), %%eax\n\t" //+7 + "movl %%fs:-128(%%edi), %%eax\n\t" //+4 + "movl %%fs:-64(%%edi), %%eax\n\t" //+5 + "movl %%fs:(%%edi), %%eax\n\t" //+6 + "movl %%fs:64(%%edi), %%eax\n\t" //+7 - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 - "movl %%fs:(%%ebx), %%eax\n\t" //+10 - "movl %%fs:64(%%ebx), %%eax\n\t" //+11 + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 + "movl %%fs:(%%ebx), %%eax\n\t" //+10 + "movl %%fs:64(%%ebx), %%eax\n\t" //+11 - "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 - "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 - "movl %%fs:(%%ecx), %%eax\n\t" //+14 - "movl %%fs:64(%%ecx), %%eax\n\t" //+15 + "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 + "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 + "movl %%fs:(%%ecx), %%eax\n\t" //+14 + "movl %%fs:64(%%ecx), %%eax\n\t" //+15 - "movl %%fs:-128(%%edx), %%eax\n\t" //+16 - "movl %%fs:-64(%%edx), %%eax\n\t" //+17 + "movl %%fs:-128(%%edx), %%eax\n\t" //+16 + "movl %%fs:-64(%%edx), %%eax\n\t" //+17 - :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "S"(addr_lo+128), "D"(addr_lo+128+4*64) - ); + :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "S"(addr_lo+128), "D"(addr_lo+128+4*64) + ); } -static void ReadL9TestPattern(unsigned addr_lo) +static void ReadL9TestPattern(unsigned addr_lo) { - //set fs and use fs prefix to access the mem - __asm__ volatile ( + //set fs and use fs prefix to access the mem + __asm__ volatile ( - "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 - "movl %%fs:(%%ecx), %%eax\n\t" //+2 - "movl %%fs:64(%%ecx), %%eax\n\t" //+3 + "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 + "movl %%fs:(%%ecx), %%eax\n\t" //+2 + "movl %%fs:64(%%ecx), %%eax\n\t" //+3 - "movl %%fs:-128(%%edx), %%eax\n\t" //+4 - "movl %%fs:-64(%%edx), %%eax\n\t" //+5 - "movl %%fs:(%%edx), %%eax\n\t" //+6 - "movl %%fs:64(%%edx), %%eax\n\t" //+7 + "movl %%fs:-128(%%edx), %%eax\n\t" //+4 + "movl %%fs:-64(%%edx), %%eax\n\t" //+5 + "movl %%fs:(%%edx), %%eax\n\t" //+6 + "movl %%fs:64(%%edx), %%eax\n\t" //+7 - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), "d"(addr_lo+128+4*64) - ); + :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), "d"(addr_lo+128+4*64) + ); } @@ -1000,56 +1000,56 @@ static void FlushDQSTestPattern_L9(unsigned addr_lo) { - __asm__ volatile ( - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" + __asm__ volatile ( + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" - "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-128(%%ebx)\n\t" - :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), "a"(addr_lo+128+4*64) + :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), "a"(addr_lo+128+4*64) ); } static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo) { __asm__ volatile ( - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" - "clflush %%fs:-128(%%edi)\n\t" - "clflush %%fs:-64(%%edi)\n\t" - "clflush %%fs:(%%edi)\n\t" - "clflush %%fs:64(%%edi)\n\t" + "clflush %%fs:-128(%%edi)\n\t" + "clflush %%fs:-64(%%edi)\n\t" + "clflush %%fs:(%%edi)\n\t" + "clflush %%fs:64(%%edi)\n\t" - "clflush %%fs:-128(%%ebx)\n\t" - "clflush %%fs:-64(%%ebx)\n\t" - "clflush %%fs:(%%ebx)\n\t" - "clflush %%fs:64(%%ebx)\n\t" + "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-64(%%ebx)\n\t" + "clflush %%fs:(%%ebx)\n\t" + "clflush %%fs:64(%%ebx)\n\t" - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" - "clflush %%fs:-128(%%edx)\n\t" - "clflush %%fs:-64(%%edx)\n\t" + "clflush %%fs:-128(%%edx)\n\t" + "clflush %%fs:-64(%%edx)\n\t" - :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "a"(addr_lo+128), "D"(addr_lo+128+4*64) + :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "a"(addr_lo+128), "D"(addr_lo+128+4*64) ); } static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) { - + if(pattern == 0){ FlushDQSTestPattern_L9(addr_lo); } @@ -1060,7 +1060,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsigned pattern, uint8_t *buf_a) { - uint32_t *test_buf; + uint32_t *test_buf; unsigned bitmap = 0xff; unsigned bytelane; int i; @@ -1068,48 +1068,48 @@ int j; uint32_t value_test; - test_buf = (uint32_t *)buf_a; - + test_buf = (uint32_t *)buf_a; - if(pattern && channel) { - addr_lo += 8; //second channel - test_buf+= 2; - } + if(pattern && channel) { + addr_lo += 8; //second channel + test_buf+= 2; + } + bytelane = 0; for(i=0;i<9*64/4;i++) { - __asm__ volatile ( - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); value_test = *test_buf; - print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); + print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7); for(j=0;j<4*8;j+=8) { if(((value>>j)&0xff) != ((value_test>>j)& 0xff)) { bitmap &= ~(1<<bytelane); } - + bytelane++; - bytelane &= 0x7; + bytelane &= 0x7; } - print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7); + print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7); if(bytelane == 0) { - if(pattern == 1) { //dual channel + if(pattern == 1) { //dual channel addr_lo += 8; //skip over other channel's data test_buf += 2; } } addr_lo += 4; test_buf +=1; - + } - return bitmap; + return bitmap; } @@ -1119,11 +1119,11 @@ unsigned Errors; unsigned BanksPresent; - unsigned MutualCSPassW[48]; + unsigned MutualCSPassW[48]; unsigned ChipSel; unsigned DQSDelay; - + unsigned TestAddr; unsigned LastTest; @@ -1142,16 +1142,16 @@ } for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 - print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); //FIXME: process 64MUXedMode if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue; BanksPresent = 1; TestAddr = Get_MCTSysAddr(ctrl, ChipSel, sysinfo); - print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); - //set fs and use fs prefix to access the mem + //set fs and use fs prefix to access the mem set_FSBASE(TestAddr>>24); if(Direction == DQS_READDIR) { @@ -1160,28 +1160,28 @@ } for(DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); if(MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay); - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); if(Direction == DQS_WRITEDIR) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); - WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); + WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5); - ReadDQSTestPattern(TestAddr<<8, Pattern); + ReadDQSTestPattern(TestAddr<<8, Pattern); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO(TestAddr); - FlushDQSTestPattern(TestAddr<<8, Pattern); + FlushDQSTestPattern(TestAddr<<8, Pattern); ResetTargetWTIO(); } } - if(BanksPresent) + if(BanksPresent) for(ByteLane = 0; ByteLane < 8; ByteLane++) { - print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); LastTest = DQS_FAIL; RnkDlySeqPassMax = 0; @@ -1190,8 +1190,8 @@ for(DQSDelay=0; DQSDelay<48; DQSDelay++) { if(MutualCSPassW[DQSDelay] & (1<<ByteLane)) { - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); RnkDlySeqPassMax = DQSDelay; if(LastTest == DQS_FAIL) { @@ -1207,165 +1207,165 @@ LastTest = DQS_FAIL; } } - print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); if(RnkDlySeqPassMax == 0) { Errors |= SB_NODQSPOS; // no passing window } else { - print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); - print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); if((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ Errors |= SB_SMALLDQS; } else { unsigned middle_dqs; - middle_dqs = MiddleDQS(RnkDlyFilterMin, RnkDlyFilterMax); - print_debug_dqs("\t\t\t\tTrainDQSPos: 35 middle_dqs ",middle_dqs, 4); + middle_dqs = MiddleDQS(RnkDlyFilterMin, RnkDlyFilterMax); + print_debug_dqs("\t\t\t\tTrainDQSPos: 35 middle_dqs ",middle_dqs, 4); SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, middle_dqs); save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, middle_dqs); } - } + } } print_debug_dqs("\t\t\tTrainDQSPos: end", 0xff, 3); - + return Errors; - + } static unsigned TrainReadDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) { - print_debug_dqs("\t\tTrainReadPos", 0, 2); - return TrainDQSPos(ctrl, channel, DQS_READDIR, pattern, buf_a, dqs_delay_a, sysinfo); + print_debug_dqs("\t\tTrainReadPos", 0, 2); + return TrainDQSPos(ctrl, channel, DQS_READDIR, pattern, buf_a, dqs_delay_a, sysinfo); } static unsigned TrainWriteDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) { print_debug_dqs("\t\tTrainWritePos", 0, 2); - return TrainDQSPos(ctrl, channel, DQS_WRITEDIR, pattern, buf_a, dqs_delay_a, sysinfo); + return TrainDQSPos(ctrl, channel, DQS_WRITEDIR, pattern, buf_a, dqs_delay_a, sysinfo); } static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { - static const uint32_t TestPatternJD1a[] = { + static const uint32_t TestPatternJD1a[] = { 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW0-1, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW2-3, ALL-EVEN - 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW4-5, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW6-7, ALL-EVEN - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW0-1, DQ0-ODD - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW2-3, DQ0-ODD - 0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, // QW4-5, DQ0-ODD - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW6-7, DQ0-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW0-1, DQ1-ODD - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2-3, DQ1-ODD - 0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, // QW4-5, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW6-7, DQ1-ODD - 0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, // QW0-1, DQ2-ODD - 0x04040404,0x04040404,0x04040404,0x04040404, // QW2-3, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4-5, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6-7, DQ2-ODD - 0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, // QW0-1, DQ3-ODD - 0x08080808,0x08080808,0x08080808,0x08080808, // QW2-3, DQ3-ODD - 0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, // QW4-5, DQ3-ODD - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6-7, DQ3-ODD - 0x10101010,0x10101010,0x10101010,0x10101010, // QW0-1, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW2-3, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4-5, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW6-7, DQ4-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0-1, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, // QW2-3, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4-5, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6-7, DQ5-ODD - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0-1, DQ6-ODD - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW2-3, DQ6-ODD - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW4-5, DQ6-ODD - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW6-7, DQ6-ODD - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW0-1, DQ7-ODD - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW2-3, DQ7-ODD - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW4-5, DQ7-ODD - 0x80808080,0x80808080,0x80808080,0x80808080 // QW6-7, DQ7-ODD - }; - static const uint32_t TestPatternJD1b[] = { + 0x00000000,0x00000000,0x00000000,0x00000000, // QW2-3, ALL-EVEN + 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW4-5, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW6-7, ALL-EVEN + 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW0-1, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW2-3, DQ0-ODD + 0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, // QW4-5, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW6-7, DQ0-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW0-1, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2-3, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, // QW4-5, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW6-7, DQ1-ODD + 0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, // QW0-1, DQ2-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW2-3, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4-5, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6-7, DQ2-ODD + 0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, // QW0-1, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW2-3, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, // QW4-5, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6-7, DQ3-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW0-1, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW2-3, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4-5, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW6-7, DQ4-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0-1, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, // QW2-3, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4-5, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6-7, DQ5-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0-1, DQ6-ODD + 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW2-3, DQ6-ODD + 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW4-5, DQ6-ODD + 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW6-7, DQ6-ODD + 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW0-1, DQ7-ODD + 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW2-3, DQ7-ODD + 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW4-5, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080 // QW6-7, DQ7-ODD + }; + static const uint32_t TestPatternJD1b[] = { 0x00000000,0x00000000,0x00000000,0x00000000, // QW0,CHA-B, ALL-EVEN - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW1,CHA-B, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW2,CHA-B, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW3,CHA-B, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW4,CHA-B, ALL-EVEN - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW5,CHA-B, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW6,CHA-B, ALL-EVEN - 0x00000000,0x00000000,0x00000000,0x00000000, // QW7,CHA-B, ALL-EVEN - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW0,CHA-B, DQ0-ODD - 0x01010101,0x01010101,0x01010101,0x01010101, // QW1,CHA-B, DQ0-ODD - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW2,CHA-B, DQ0-ODD - 0x01010101,0x01010101,0x01010101,0x01010101, // QW3,CHA-B, DQ0-ODD - 0x01010101,0x01010101,0x01010101,0x01010101, // QW4,CHA-B, DQ0-ODD - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW5,CHA-B, DQ0-ODD - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW6,CHA-B, DQ0-ODD - 0x01010101,0x01010101,0x01010101,0x01010101, // QW7,CHA-B, DQ0-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2,CHA-B, DQ1-ODD - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW3,CHA-B, DQ1-ODD - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW6,CHA-B, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW7,CHA-B, DQ1-ODD - 0x04040404,0x04040404,0x04040404,0x04040404, // QW0,CHA-B, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW1,CHA-B, DQ2-ODD - 0x04040404,0x04040404,0x04040404,0x04040404, // QW2,CHA-B, DQ2-ODD - 0x04040404,0x04040404,0x04040404,0x04040404, // QW3,CHA-B, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4,CHA-B, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW5,CHA-B, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6,CHA-B, DQ2-ODD - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW7,CHA-B, DQ2-ODD - 0x08080808,0x08080808,0x08080808,0x08080808, // QW0,CHA-B, DQ3-ODD - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW1,CHA-B, DQ3-ODD - 0x08080808,0x08080808,0x08080808,0x08080808, // QW2,CHA-B, DQ3-ODD - 0x08080808,0x08080808,0x08080808,0x08080808, // QW3,CHA-B, DQ3-ODD - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW4,CHA-B, DQ3-ODD - 0x08080808,0x08080808,0x08080808,0x08080808, // QW5,CHA-B, DQ3-ODD - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6,CHA-B, DQ3-ODD - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW7,CHA-B, DQ3-ODD - 0x10101010,0x10101010,0x10101010,0x10101010, // QW0,CHA-B, DQ4-ODD - 0x10101010,0x10101010,0x10101010,0x10101010, // QW1,CHA-B, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW2,CHA-B, DQ4-ODD - 0x10101010,0x10101010,0x10101010,0x10101010, // QW3,CHA-B, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4,CHA-B, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW5,CHA-B, DQ4-ODD - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW6,CHA-B, DQ4-ODD - 0x10101010,0x10101010,0x10101010,0x10101010, // QW7,CHA-B, DQ4-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0,CHA-B, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW1,CHA-B, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW2,CHA-B, DQ5-ODD - 0x20202020,0x20202020,0x20202020,0x20202020, // QW3,CHA-B, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4,CHA-B, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW5,CHA-B, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6,CHA-B, DQ5-ODD - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW7,CHA-B, DQ5-ODD - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0,CHA-B, DQ6-ODD - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW1,CHA-B, DQ6-ODD - 0x40404040,0x40404040,0x40404040,0x40404040, // QW2,CHA-B, DQ6-ODD - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW3,CHA-B, DQ6-ODD - 0x40404040,0x40404040,0x40404040,0x40404040, // QW4,CHA-B, DQ6-ODD - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW5,CHA-B, DQ6-ODD - 0x40404040,0x40404040,0x40404040,0x40404040, // QW6,CHA-B, DQ6-ODD - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW7,CHA-B, DQ6-ODD - 0x80808080,0x80808080,0x80808080,0x80808080, // QW0,CHA-B, DQ7-ODD - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW1,CHA-B, DQ7-ODD - 0x80808080,0x80808080,0x80808080,0x80808080, // QW2,CHA-B, DQ7-ODD - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW3,CHA-B, DQ7-ODD - 0x80808080,0x80808080,0x80808080,0x80808080, // QW4,CHA-B, DQ7-ODD - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW5,CHA-B, DQ7-ODD - 0x80808080,0x80808080,0x80808080,0x80808080, // QW6,CHA-B, DQ7-ODD - 0x80808080,0x80808080,0x80808080,0x80808080 // QW7,CHA-B, DQ7-ODD - }; - uint8_t pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ - uint8_t *buf_a; + 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW1,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW2,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW3,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW4,CHA-B, ALL-EVEN + 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW5,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW6,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW7,CHA-B, ALL-EVEN + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW0,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW1,CHA-B, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW2,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW3,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW4,CHA-B, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW5,CHA-B, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW6,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW7,CHA-B, DQ0-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW3,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW6,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW7,CHA-B, DQ1-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW0,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW1,CHA-B, DQ2-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW2,CHA-B, DQ2-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW3,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW5,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW7,CHA-B, DQ2-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW0,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW1,CHA-B, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW2,CHA-B, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW3,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW4,CHA-B, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW5,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW7,CHA-B, DQ3-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW0,CHA-B, DQ4-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW1,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW2,CHA-B, DQ4-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW3,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW5,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW6,CHA-B, DQ4-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW7,CHA-B, DQ4-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW1,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW2,CHA-B, DQ5-ODD + 0x20202020,0x20202020,0x20202020,0x20202020, // QW3,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW5,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW7,CHA-B, DQ5-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW1,CHA-B, DQ6-ODD + 0x40404040,0x40404040,0x40404040,0x40404040, // QW2,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW3,CHA-B, DQ6-ODD + 0x40404040,0x40404040,0x40404040,0x40404040, // QW4,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW5,CHA-B, DQ6-ODD + 0x40404040,0x40404040,0x40404040,0x40404040, // QW6,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW7,CHA-B, DQ6-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW0,CHA-B, DQ7-ODD + 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW1,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW2,CHA-B, DQ7-ODD + 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW3,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW4,CHA-B, DQ7-ODD + 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW5,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW6,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080 // QW7,CHA-B, DQ7-ODD + }; + uint8_t pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ + uint8_t *buf_a; unsigned pattern; uint32_t dword; @@ -1377,25 +1377,25 @@ unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128; uint8_t *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9 - //enable SSE2 - enable_sse2(); + //enable SSE2 + enable_sse2(); - //wrap32dis - set_wrap32dis(); + //wrap32dis + set_wrap32dis(); - //disable ECC temp - dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - ecc_bit = dword & DCL_DimmEccEn; - dword &= ~(DCL_DimmEccEn); - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + //disable ECC temp + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + ecc_bit = dword & DCL_DimmEccEn; + dword &= ~(DCL_DimmEccEn); + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); //SetupDqsPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); if(is_Width128){ pattern = 1; - for(i=0;i<16*18;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; + for(i=0;i<16*18;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { @@ -1403,10 +1403,10 @@ for(i=0; i<16*9;i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; } - + } - print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); + print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); print_debug_addr("TrainDQSRdWrPos: buf_a:", buf_a); @@ -1419,46 +1419,46 @@ } while( (channel<2) && (!Errors)) { - print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); + print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); for(DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { unsigned err; SetDQSDelayAllCSR(ctrl, channel, DQS_WRITEDIR, DQSWrDelay); - print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); + print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); err= TrainReadDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); - print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); + print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); if(err == 0) break; Errors |= err; } - print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); + print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); if(DQSWrDelay < 48) { Errors = TrainWriteDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); - print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); + print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); } channel++; if(!is_Width128){ - //FIXME: 64MuxMode?? + //FIXME: 64MuxMode?? channel++; // skip channel if 64-bit mode } } - //Enable ECC again - dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - dword &= ~(DCL_DimmEccEn); - dword |= ecc_bit; - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + //Enable ECC again + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dword &= ~(DCL_DimmEccEn); + dword |= ecc_bit; + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); - //Clear wrap32dis + //Clear wrap32dis - clear_wrap32dis(); + clear_wrap32dis(); - //restore SSE2 setting - disable_sse2(); + //restore SSE2 setting + disable_sse2(); - print_debug_dqs("TrainDQSRdWrPos: ", 5, 0); - + print_debug_dqs("TrainDQSRdWrPos: ", 5, 0); + return Errors; } @@ -1469,16 +1469,16 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned ByteLane1, unsigned InterFactor, unsigned Direction, uint8_t *dqs_delay_a) /* InterFactor: 0: 100% ByteLane 0 - 0x80: 50% between ByteLane 0 and 1 + 0x80: 50% between ByteLane 0 and 1 0xff: 99.6% ByteLane 1 and 0.4% like 0 */ { unsigned DQSDelay0, DQSDelay1; unsigned DQSDelay; - + DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a); - DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); - + DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); + if(DQSDelay0>DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; InterFactor = 0xff - InterFactor; @@ -1491,19 +1491,19 @@ DQSDelay >>= 8; // /255 - if(DQSDelay0>DQSDelay1) { - DQSDelay += DQSDelay1; - } - else { - DQSDelay += DQSDelay0; - } + if(DQSDelay0>DQSDelay1) { + DQSDelay += DQSDelay1; + } + else { + DQSDelay += DQSDelay0; + } return DQSDelay; } static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) -{ +{ unsigned channel; unsigned ByteLane; unsigned Direction; @@ -1521,7 +1521,7 @@ Direction = direction[i]; lane0 = 4; lane1 = 5; ratio = 0; dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay); save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay); } @@ -1530,92 +1530,92 @@ static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); if(TrainRcvrEn(ctrl, Pass, sysinfo)) { return 1; } - print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); return 0; - + } static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); + print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); return 1; } else { SetEccDQSRdWrPos(ctrl, sysinfo); } - print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); return 0; - + } #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo) { - tsc_t tsc1[8]; + tsc_t tsc1[8]; unsigned cpu_f0_f1[8]; int i; - print_debug_addr("dqs_timing: tsc1[8] :", tsc1); + print_debug_addr("dqs_timing: tsc1[8] :", tsc1); - for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[i]) - continue; + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; - /* Skip everything if I don't have any memory on this controller */ + /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - uint32_t dword; + uint32_t dword; - cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); + cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); - if(!cpu_f0_f1[i]) continue; + if(!cpu_f0_f1[i]) continue; - dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); - dword &= ~DC_DqsRcvEnTrain; - pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword); + dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); + dword &= ~DC_DqsRcvEnTrain; + pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword); - dword = pci_read_config32(ctrl[i].f2, DRAM_INIT); - dword |= DI_EnDramInit; - pci_write_config32(ctrl[i].f2, DRAM_INIT, dword); - dword &= ~DI_EnDramInit; - pci_write_config32(ctrl[i].f2, DRAM_INIT, dword); + dword = pci_read_config32(ctrl[i].f2, DRAM_INIT); + dword |= DI_EnDramInit; + pci_write_config32(ctrl[i].f2, DRAM_INIT, dword); + dword &= ~DI_EnDramInit; + pci_write_config32(ctrl[i].f2, DRAM_INIT, dword); - tsc1[i] = rdtsc(); - print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); + tsc1[i] = rdtsc(); + print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); - dword = tsc1[i].lo + tsc0[i].lo; - if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { - tsc1[i].hi++; - } - tsc1[i].lo = dword; - tsc1[i].hi+= tsc0[i].hi; + dword = tsc1[i].lo + tsc0[i].lo; + if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { + tsc1[i].hi++; + } + tsc1[i].lo = dword; + tsc1[i].hi+= tsc0[i].hi; - print_debug_dqs_tsc("end : tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); + print_debug_dqs_tsc("end : tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); - } + } - for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[i]) - continue; + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; - /* Skip everything if I don't have any memory on this controller */ + /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; if(!cpu_f0_f1[i]) continue; - tsc_t tsc; + tsc_t tsc; - do { - tsc = rdtsc(); - } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo))); + do { + tsc = rdtsc(); + } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo))); - print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2); - } + print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2); + } } @@ -1624,211 +1624,211 @@ /* setting variable mtrr, comes from linux kernel source */ static void set_var_mtrr_dqs( - unsigned int reg, unsigned long basek, unsigned long sizek, - unsigned char type, unsigned address_bits) + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits) { - msr_t base, mask; - unsigned address_mask_high; + msr_t base, mask; + unsigned address_mask_high; - address_mask_high = ((1u << (address_bits - 32u)) - 1u); + address_mask_high = ((1u << (address_bits - 32u)) - 1u); - base.hi = basek >> 22; - base.lo = basek << 10; + base.hi = basek >> 22; + base.lo = basek << 10; - if (sizek < 4*1024*1024) { - mask.hi = address_mask_high; - mask.lo = ~((sizek << 10) -1); - } - else { - mask.hi = address_mask_high & (~((sizek >> 22) -1)); - mask.lo = 0; - } + if (sizek < 4*1024*1024) { + mask.hi = address_mask_high; + mask.lo = ~((sizek << 10) -1); + } + else { + mask.hi = address_mask_high & (~((sizek >> 22) -1)); + mask.lo = 0; + } - if (reg >= 8) - return; + if (reg >= 8) + return; - if (sizek == 0) { - msr_t zero; - zero.lo = zero.hi = 0; - /* The invalid bit is kept in the mask, so we simply clear the - relevant mask register to disable a range. */ - wrmsr (MTRRphysMask_MSR(reg), zero); - } else { - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - base.lo |= type; - mask.lo |= 0x800; - wrmsr (MTRRphysBase_MSR(reg), base); - wrmsr (MTRRphysMask_MSR(reg), mask); - } + if (sizek == 0) { + msr_t zero; + zero.lo = zero.hi = 0; + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR(reg), zero); + } else { + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + base.lo |= type; + mask.lo |= 0x800; + wrmsr (MTRRphysBase_MSR(reg), base); + wrmsr (MTRRphysMask_MSR(reg), mask); + } } /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { - int r; + int r; - __asm__("bsrl %1,%0\n\t" - "jnz 1f\n\t" - "movl $0,%0\n" - "1:" : "=r" (r) : "g" (x)); - return r; + __asm__("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; } /* fms: find least sigificant bit set */ static inline unsigned int fls(unsigned int x) { - int r; + int r; - __asm__("bsfl %1,%0\n\t" - "jnz 1f\n\t" - "movl $32,%0\n" - "1:" : "=r" (r) : "g" (x)); - return r; + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; } static unsigned int range_to_mtrr(unsigned int reg, - unsigned long range_startk, unsigned long range_sizek, - unsigned long next_range_startk, unsigned char type, unsigned address_bits) + unsigned long range_startk, unsigned long range_sizek, + unsigned long next_range_startk, unsigned char type, unsigned address_bits) { - if (!range_sizek || (reg >= 8)) { - return reg; - } - while(range_sizek) { - unsigned long max_align, align; - unsigned long sizek; - /* Compute the maximum size I can make a range */ - max_align = fls(range_startk); - align = fms(range_sizek); - if (align > max_align) { - align = max_align; - } - sizek = 1 << align; + if (!range_sizek || (reg >= 8)) { + return reg; + } + while(range_sizek) { + unsigned long max_align, align; + unsigned long sizek; + /* Compute the maximum size I can make a range */ + max_align = fls(range_startk); + align = fms(range_sizek); + if (align > max_align) { + align = max_align; + } + sizek = 1 << align; #if MEM_TRAIN_SEQ != 1 #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", - reg, range_startk >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") - ); + printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", + reg, range_startk >>10, sizek >> 10, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + ); #else - print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); - print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); + print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); + print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); print_debug( (type==MTRR_TYPE_UNCACHEABLE)?"UC\r\n": - ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n") - ); + ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n") + ); #endif #endif - set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); - range_startk += sizek; - range_sizek -= sizek; - if (reg >= 8) - break; - } - return reg; + set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); + range_startk += sizek; + range_sizek -= sizek; + if (reg >= 8) + break; + } + return reg; } static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k) { - msr_t msr; + msr_t msr; - /* Now set top of memory */ - msr.lo = (tom2_k & 0x003fffff) << 10; - msr.hi = (tom2_k & 0xffc00000) >> 22; - wrmsr(TOP_MEM2, msr); + /* Now set top of memory */ + msr.lo = (tom2_k & 0x003fffff) << 10; + msr.hi = (tom2_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM2, msr); - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(TOP_MEM, msr); + msr.lo = (tom_k & 0x003fffff) << 10; + msr.hi = (tom_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM, msr); } static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k){ - unsigned reg; - msr_t msr; + unsigned reg; + msr_t msr; #if 0 - //still enable from cache_as_ram.inc - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR,msr); + //still enable from cache_as_ram.inc + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR,msr); #endif - //[0,512k), [512k, 640k) - msr.hi = 0x1e1e1e1e; - msr.lo = msr.hi; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + //[0,512k), [512k, 640k) + msr.hi = 0x1e1e1e1e; + msr.lo = msr.hi; + wrmsr(0x250, msr); + wrmsr(0x258, msr); - //[1M, TOM) - reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); + //[1M, TOM) + reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); - //[4G, TOM2) - if(tom2_k) { - //enable tom2 and type - msr = rdmsr(SYSCFG_MSR); - msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB - wrmsr(SYSCFG_MSR, msr); - } + //[4G, TOM2) + if(tom2_k) { + //enable tom2 and type + msr = rdmsr(SYSCFG_MSR); + msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB + wrmsr(SYSCFG_MSR, msr); + } } static void clear_mtrr_dqs(unsigned tom2_k){ - msr_t msr; - unsigned i; + msr_t msr; + unsigned i; - //still enable from cache_as_ram.inc - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR,msr); + //still enable from cache_as_ram.inc + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR,msr); - //[0,512k), [512k, 640k) - msr.hi = 0; - msr.lo = msr.hi; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + //[0,512k), [512k, 640k) + msr.hi = 0; + msr.lo = msr.hi; + wrmsr(0x250, msr); + wrmsr(0x258, msr); - //[1M, TOM) - for(i=0x204;i<0x210;i++) { - wrmsr(i, msr); - } + //[1M, TOM) + for(i=0x204;i<0x210;i++) { + wrmsr(i, msr); + } - //[4G, TOM2) - if(tom2_k) { - //enable tom2 and type - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB - wrmsr(SYSCFG_MSR, msr); - } + //[4G, TOM2) + if(tom2_k) { + //enable tom2 and type + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB + wrmsr(SYSCFG_MSR, msr); + } } static void set_htic_bit(unsigned i, unsigned val, unsigned bit) { - uint32_t dword; - dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); - dword &= ~(1<<bit); - dword |= ((val & 1) <<bit); - pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword); + uint32_t dword; + dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); + dword &= ~(1<<bit); + dword |= ((val & 1) <<bit); + pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword); } static unsigned get_htic_bit(unsigned i, unsigned bit) { - uint32_t dword; - dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); - dword &= (1<<bit); - return dword; + uint32_t dword; + dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); + dword &= (1<<bit); + return dword; } static void wait_till_sysinfo_in_ram(void) { - while(1) { - if(get_htic_bit(0, 9)) return; - } + while(1) { + if(get_htic_bit(0, 9)) return; + } } static void set_sysinfo_in_ram(unsigned val) { - set_htic_bit(0, val, 9); + set_htic_bit(0, val, 9); } @@ -1845,32 +1845,32 @@ tsc_t tsc[5]; - //need to enable mtrr, so dqs training could access the test address - setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); + //need to enable mtrr, so dqs training could access the test address + setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); - for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[ i ]) - continue; + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[ i ]) + continue; - /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); } tsc[0] = rdtsc(); - for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[ i ]) - continue; + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[ i ]) + continue; - /* Skip everything if I don't have any memory on this controller */ + /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass1: "); - print_debug_hex8(i); - if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - print_debug(" done\r\n"); - } + print_debug("DQS Training:RcvrEn:Pass1: "); + print_debug_hex8(i); + if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; + print_debug(" done\r\n"); + } tsc[1] = rdtsc(); #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 @@ -1878,33 +1878,33 @@ #endif tsc[2] = rdtsc(); - for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[i]) - continue; + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; - /* Skip everything if I don't have any memory on this controller */ + /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:DQSPos: "); - print_debug_hex8(i); - if(train_DqsPos(ctrl+i, sysinfo)) goto out; - print_debug(" done\r\n"); - } + print_debug("DQS Training:DQSPos: "); + print_debug_hex8(i); + if(train_DqsPos(ctrl+i, sysinfo)) goto out; + print_debug(" done\r\n"); + } tsc[3] = rdtsc(); - for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[i]) - continue; + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; - /* Skip everything if I don't have any memory on this controller */ + /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - print_debug("DQS Training:RcvrEn:Pass2: "); - print_debug_hex8(i); - if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - print_debug(" done\r\n"); + print_debug("DQS Training:RcvrEn:Pass2: "); + print_debug_hex8(i); + if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; + print_debug(" done\r\n"); sysinfo->mem_trained[i]=1; - } + } out: tsc[4] = rdtsc(); @@ -1916,82 +1916,82 @@ } - + } #endif -#if MEM_TRAIN_SEQ > 0 +#if MEM_TRAIN_SEQ > 0 static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned v) { - int ii; + int ii; - tsc_t tsc[4]; + tsc_t tsc[4]; if(sysinfo->mem_trained[i] != 0x80) return; #if MEM_TRAIN_SEQ == 1 - //need to enable mtrr, so dqs training could access the test address - setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); + //need to enable mtrr, so dqs training could access the test address + setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif fill_mem_cs_sysinfo(i, ctrl, sysinfo); if(v) { - tsc[0] = rdtsc(); + tsc[0] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass1: "); - print_debug_hex8(i); + print_debug("set DQS timing:RcvrEn:Pass1: "); + print_debug_hex8(i); } - if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { + if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // goto out; } if(v) { - print_debug(" done\r\n"); - tsc[1] = rdtsc(); - print_debug("set DQS timing:DQSPos: "); - print_debug_hex8(i); + print_debug(" done\r\n"); + tsc[1] = rdtsc(); + print_debug("set DQS timing:DQSPos: "); + print_debug_hex8(i); } - if(train_DqsPos(ctrl, sysinfo)) { + if(train_DqsPos(ctrl, sysinfo)) { sysinfo->mem_trained[i]=0x82; // goto out; } - + if(v) { - print_debug(" done\r\n"); - tsc[2] = rdtsc(); + print_debug(" done\r\n"); + tsc[2] = rdtsc(); - print_debug("set DQS timing:RcvrEn:Pass2: "); - print_debug_hex8(i); + print_debug("set DQS timing:RcvrEn:Pass2: "); + print_debug_hex8(i); } - if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ + if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // goto out; } if(v) { - print_debug(" done\r\n"); + print_debug(" done\r\n"); - tsc[3] = rdtsc(); + tsc[3] = rdtsc(); } out: #if MEM_TRAIN_SEQ == 1 - clear_mtrr_dqs(sysinfo->tom2_k); + clear_mtrr_dqs(sysinfo->tom2_k); #endif if(v) { - for(ii=0;ii<4;ii++) { - print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); - } + for(ii=0;ii<4;ii++) { + print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); + } } - + if(sysinfo->mem_trained[i] == 0x80) { sysinfo->mem_trained[i]=1; } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -51,7 +51,7 @@ unsigned addr; uint32_t value; addr = dev | where; - value = pci_register[addr] | + value = pci_register[addr] | (pci_register[addr + 1] << 8) | (pci_register[addr + 2] << 16) | (pci_register[addr + 3] << 24); @@ -128,23 +128,23 @@ unsigned long log2(unsigned long x) { - // assume 8 bits per byte. - unsigned long i = 1 << (sizeof(x)*8 - 1); - unsigned long pow = sizeof(x) * 8 - 1; + // assume 8 bits per byte. + unsigned long i = 1 << (sizeof(x)*8 - 1); + unsigned long pow = sizeof(x) * 8 - 1; - if (! x) { + if (! x) { static const char errmsg[] = " called with invalid parameter of 0\n"; write(STDERR_FILENO, __func__, sizeof(__func__) - 1); write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1); - hlt(); - } - for(; i > x; i >>= 1, pow--) - ; + hlt(); + } + for(; i > x; i >>= 1, pow--) + ; - return pow; + return pow; } -typedef struct msr_struct +typedef struct msr_struct { unsigned lo; unsigned hi; @@ -188,10 +188,10 @@ } -static uint8_t spd_mt4lsdt464a[256] = +static uint8_t spd_mt4lsdt464a[256] = { - 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, - 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, + 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, + 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F, 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E, @@ -200,46 +200,46 @@ 0x06, 0x07, 0x08, 0x09, 0x00, }; -static uint8_t spd_micron_512MB_DDR333[256] = +static uint8_t spd_micron_512MB_DDR333[256] = { - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31, - 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, - 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, + 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, + 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, + 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31, + 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, + 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; -static uint8_t spd_micron_256MB_DDR333[256] = +static uint8_t spd_micron_256MB_DDR333[256] = { - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, + 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, + 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, + 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36, + 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36, 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31, 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -247,17 +247,17 @@ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }; #define MAX_DIMMS 16 @@ -273,7 +273,7 @@ } else { device -= 0x50; - + if (address > 256) { result = -1; } @@ -390,13 +390,13 @@ #endif raminit_main(); - + #if 0 print_debug("spd_count: "); print_debug_hex32(spd_count); print_debug("\r\n"); #endif - + } @@ -413,10 +413,10 @@ print_debug("\r\nSPD will fail after: "); print_debug_hex32(spd_fail_count); print_debug(" accesses.\r\n"); - + memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); - + raminit_main(); done: @@ -429,7 +429,7 @@ for(i = 0; i < 0x48; i++) { do_test2(i); } - + } int main(int argc, char **argv) Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -54,29 +54,29 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - unsigned reg; + unsigned reg; - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; } static unsigned get_sblk(void) { - uint32_t reg; - /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - return ((reg>>8) & 3) ; + uint32_t reg; + /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + return ((reg>>8) & 3) ; } static unsigned get_sbbusn(unsigned sblk) Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -139,7 +139,7 @@ * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -195,7 +195,7 @@ * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -203,7 +203,7 @@ * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c 2008-10-02 19:20:22 UTC (rev 3632) @@ -1,44 +1,44 @@ #define RES_DEBUG 0 static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) -{ - int i; +{ + int i; // print_debug("setting up resource map offset...."); #if 0 - print_debug("\r\n"); + print_debug("\r\n"); #endif - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; + for(i = 0; i < max; i += 3) { + device_t dev; + unsigned where; + unsigned long reg; #if 0 #if CONFIG_USE_PRINTK_IN_CAR - prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]); - #else - print_debug_hex32(register_values[i] + offset_pci_dev); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\r\n"); - #endif + prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]); + #else + print_debug_hex32(register_values[i] + offset_pci_dev); + print_debug(" <-"); + print_debug_hex32(register_values[i+2]); + print_debug("\r\n"); + #endif #endif - dev = (register_values[i] & ~0xfff) + offset_pci_dev; - where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2] + offset_io_base; - pci_write_config32(dev, where, reg); + dev = (register_values[i] & ~0xfff) + offset_pci_dev; + where = register_values[i] & 0xfff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+1]; + reg |= register_values[i+2] + offset_io_base; + pci_write_config32(dev, where, reg); #if 0 - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); + reg = pci_read_config32(register_values[i]); + reg &= register_values[i+1]; + reg |= register_values[i+2] & ~register_values[i+1]; + pci_write_config32(register_values[i], reg); #endif - } + } // print_debug("done.\r\n"); } #define RES_PCI_IO 0x10 -#define RES_PORT_IO_8 0x22 +#define RES_PORT_IO_8 0x22 #define RES_PORT_IO_32 0x20 #define RES_MEM_IO 0x40 @@ -57,29 +57,29 @@ for(i = 0; i < max; i += 4) { #if RES_DEBUG #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", - i>>2, register_values[i], - register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), - register_values[i+2], + printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", + i>>2, register_values[i], + register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), + register_values[i+2], register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); - #else - print_debug_hex16(i>>2); - print_debug(": "); - print_debug_hex8(register_values[i]); - print_debug(" "); - print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) ); - print_debug(" <- & "); - print_debug_hex32(register_values[i+2]); - print_debug(" | "); - print_debug_hex32(register_values[i+3] + + #else + print_debug_hex16(i>>2); + print_debug(": "); + print_debug_hex8(register_values[i]); + print_debug(" "); + print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) ); + print_debug(" <- & "); + print_debug_hex32(register_values[i+2]); + print_debug(" | "); + print_debug_hex32(register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); - print_debug("\r\n"); + print_debug("\r\n"); #endif #endif switch (register_values[i]) { - case RES_PCI_IO: //PCI + case RES_PCI_IO: //PCI { device_t dev; unsigned where; @@ -115,7 +115,7 @@ } break; #if 0 - case RES_MEM_IO: //mem + case RES_MEM_IO: //mem { unsigned where; unsigned long reg; @@ -127,10 +127,10 @@ } break; #endif - + } // switch - - + + } #if RES_DEBUG @@ -138,195 +138,195 @@ #endif } static void setup_resource_map_x(const unsigned int *register_values, int max) -{ - int i; +{ + int i; #if RES_DEBUG - print_debug("setting up resource map ex offset...."); + print_debug("setting up resource map ex offset...."); #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\r\n"); #endif - for(i = 0; i < max; i += 4) { + for(i = 0; i < max; i += 4) { #if RES_DEBUG #if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", - i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); - #else - print_debug_hex16(i/4); - print_debug(": "); - print_debug_hex8(register_values[i]); - print_debug(" "); - print_debug_hex32(register_values[i+1]); - print_debug(" <- & "); - print_debug_hex32(register_values[i+2]); - print_debug(" | "); - print_debug_hex32(register_values[i+3]); - print_debug("\r\n"); - #endif + printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", + i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); + #else + print_debug_hex16(i/4); + print_debug(": "); + print_debug_hex8(register_values[i]); + print_debug(" "); + print_debug_hex32(register_values[i+1]); + print_debug(" <- & "); + print_debug_hex32(register_values[i+2]); + print_debug(" | "); + print_debug_hex32(register_values[i+3]); + print_debug("\r\n"); + #endif #endif - switch (register_values[i]) { - case RES_PCI_IO: //PCI - { - device_t dev; - unsigned where; - unsigned long reg; - dev = register_values[i+1] & ~0xfff; - where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - pci_write_config32(dev, where, reg); - } - break; - case RES_PORT_IO_8: // io 8 - { - unsigned where; - unsigned reg; - where = register_values[i+1]; - reg = inb(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outb(reg, where); - } - break; - case RES_PORT_IO_32: //io32 - { - unsigned where; - unsigned long reg; - where = register_values[i+1]; - reg = inl(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outl(reg, where); - } - break; + switch (register_values[i]) { + case RES_PCI_IO: //PCI + { + device_t dev; + unsigned where; + unsigned long reg; + dev = register_values[i+1] & ~0xfff; + where = register_values[i+1] & 0xfff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+2]; + reg |= register_values[i+3]; + pci_write_config32(dev, where, reg); + } + break; + case RES_PORT_IO_8: // io 8 + { + unsigned where; + unsigned reg; + where = register_values[i+1]; + reg = inb(where); + reg &= register_values[i+2]; + reg |= register_values[i+3]; + outb(reg, where); + } + break; + case RES_PORT_IO_32: //io32 + { + unsigned where; + unsigned long reg; + where = register_values[i+1]; + reg = inl(where); + reg &= register_values[i+2]; + reg |= register_values[i+3]; + outl(reg, where); + } + break; #if 0 - case RES_MEM_IO: //mem - { - unsigned where; - unsigned long reg; - where = register_values[i+1]; - reg = read32(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - write32( where, reg); - } - break; + case RES_MEM_IO: //mem + { + unsigned where; + unsigned long reg; + where = register_values[i+1]; + reg = read32(where); + reg &= register_values[i+2]; + reg |= register_values[i+3]; + write32( where, reg); + } + break; #endif - } // switch + } // switch - } + } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\r\n"); #endif } static void setup_iob_resource_map(const unsigned int *register_values, int max) { - int i; - + int i; + for(i = 0; i < max; i += 3) { - unsigned where; + unsigned where; unsigned reg; - + where = register_values[i]; #if 0 - udelay(2000); - print_debug_hex16(where); + udelay(2000); + print_debug_hex16(where); #endif - reg = inb(where); + reg = inb(where); #if 0 - print_debug("="); - print_debug_hex8(reg); + print_debug("="); + print_debug_hex8(reg); #endif - reg &= register_values[i+1]; - reg |= register_values[i+2]; + reg &= register_values[i+1]; + reg |= register_values[i+2]; #if 0 - print_debug(" <- "); - print_debug_hex8(reg); + print_debug(" <- "); + print_debug_hex8(reg); #endif - outb(reg, where); + outb(reg, where); #if 0 - print_debug(" -> "); + print_debug(" -> "); reg = inb(where); - print_debug_hex8(reg); + print_debug_hex8(reg); print_debug("\r\n"); #endif - } + } } static void setup_io_resource_map(const unsigned int *register_values, int max) { - int i; - + int i; + for(i = 0; i < max; i += 3) { - unsigned where; + unsigned where; unsigned long reg; - + where = register_values[i]; #if 0 - udelay(2000); - print_debug_hex16(where); + udelay(2000); + print_debug_hex16(where); #endif - reg = inl(where); + reg = inl(where); #if 0 udelay(2000); - print_debug("="); - print_debug_hex32(reg); + print_debug("="); + print_debug_hex32(reg); #endif - reg &= register_values[i+1]; - reg |= register_values[i+2]; + reg &= register_values[i+1]; + reg |= register_values[i+2]; #if 0 udelay(2000); - print_debug(" <- "); - print_debug_hex32(reg); + print_debug(" <- "); + print_debug_hex32(reg); #endif - outl(reg, where); + outl(reg, where); #if 0 udelay(2000); - print_debug(" -> "); - reg = inl(where); - print_debug_hex32(reg); + print_debug(" -> "); + reg = inl(where); + print_debug_hex32(reg); print_debug("\r\n"); #endif - } + } } #if 0 static void setup_mem_resource_map(const unsigned int *register_values, int max) { - int i; - + int i; + for(i = 0; i < max; i += 3) { - unsigned where; + unsigned where; unsigned long reg; #if 0 - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); + print_debug_hex32(register_values[i]); + print_debug(" <-"); + print_debug_hex32(register_values[i+2]); #endif - where = register_values[i]; - reg = read32(where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - write32( where, reg); + where = register_values[i]; + reg = read32(where); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + write32( where, reg); #if 0 - print_debug(" RB "); - reg = read32(where); - print_debug_hex32(reg); - print_debug("\r\n"); + print_debug(" RB "); + reg = read32(where); + print_debug_hex32(reg); + print_debug("\r\n"); #endif - } + } } #endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h 2008-10-02 19:20:22 UTC (rev 3632) @@ -1,7 +1,7 @@ /* SPDs for DDR2 SDRAM */ -#define SPD_MEM_TYPE 2 - #define SPD_MEM_TYPE_SDRAM_DDR 0x07 - #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 +#define SPD_MEM_TYPE 2 + #define SPD_MEM_TYPE_SDRAM_DDR 0x07 + #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 #define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ #define SPD_DIMM_TYPE_RDIMM (1<<0) @@ -11,9 +11,9 @@ #define SPD_DIMM_TYPE_mRDIMM (1<<4) #define SPD_DIMM_TYPE_mUDIMM (1<<5) #define SPD_MOD_ATTRIB 21 - #define SPD_MOD_ATTRIB_DIFCK 0x20 - #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ - #define SPD_MOD_ATTRIB_PROBE 0x40 + #define SPD_MOD_ATTRIB_DIFCK 0x20 + #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ + #define SPD_MOD_ATTRIB_PROBE 0x40 #define SPD_DEV_ATTRIB 22 /* Device attributes --- general */ #define SPD_DIMM_CONF_TYPE 11 @@ -22,16 +22,16 @@ #define SPD_ROW_NUM 3 /* Number of Row addresses */ #define SPD_COL_NUM 4 /* Number of Column addresses */ -#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */ - -#define SPD_MOD_ATTRIB_RANK 5 /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */ +#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */ + +#define SPD_MOD_ATTRIB_RANK 5 /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */ #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 - #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 + #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 #define SPD_MOD_ATTRIB_RANK_NUM_BASE 1 #define SPD_MOD_ATTRIB_RANK_NUM_MIN 1 #define SPD_MOD_ATTRIB_RANK_NUM_MAX 8 -#define SPD_RANK_SIZE 31 /* Only one bit is set */ +#define SPD_RANK_SIZE 31 /* Only one bit is set */ #define SPD_RANK_SIZE_1GB (1<<0) #define SPD_RANK_SIZE_2GB (1<<1) #define SPD_RANK_SIZE_4GB (1<<2) @@ -58,7 +58,7 @@ #define SPD_TRAS 30 #define SPD_TWR 36 /* x */ #define SPD_TWTR 37 /* x */ -#define SPD_TRTP 38 /* x */ +#define SPD_TRTP 38 /* x */ #define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/ #define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/ Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl 2008-10-02 18:19:17 UTC (rev 3631) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl 2008-10-02 19:20:22 UTC (rev 3632) @@ -10,45 +10,45 @@ Scope (\_SB.PCI0) { - Name (BUSN, Package (0x04) - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444 - }) - Name (MMIO, Package (0x10) - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222 - }) - Name (PCIO, Package (0x08) - { - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee - }) - Name (SBLK, 0x11) - Name (TOM1, 0xaaaaaaaa) + Name (BUSN, Package (0x04) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Name (MMIO, Package (0x10) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222 + }) + Name (PCIO, Package (0x08) + { + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee + }) + Name (SBLK, 0x11) + Name (TOM1, 0xaaaaaaaa) Name (SBDN, 0xbbbbbbbb) Name (HCLK, Package (0x08) { @@ -56,22 +56,22 @@ 0x22222222, 0x33333333, 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 }) - Name (HCDN, Package (0x08) - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) + Name (HCDN, Package (0x08) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) Name (CBST, 0x88) } }

1 0

lpgcc calling itself
by Stephen Crocker 02 Oct '08

02 Oct '08

I have noticed a problem with lpgcc under Fedora Core 9 when building Tint. Instead of calling gcc, it calls itself. Looking at the Makefile and the script itself, I think I can see why: From lpgcc: if [ "$CC" != "" ]; then DEFAULT_CC=$CC else DEFAULT_CC=gcc fi From the tint Makefile: CC := $(LIBPAYLOAD_DIR)/bin/lpgcc Is this a bug in tint or a bug in libpayload?

2 2

r3631 build service
by coreboot information 02 Oct '08

02 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3631 to the coreboot source repository and caused the following changes: Change Log: CK804 coding-style fixed based on an 'indent' run (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3631&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3631&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3631&device=epia-cn&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3631 - trunk/coreboot-v2/src/southbridge/nvidia/ck804
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: uwe Date: 2008-10-02 20:19:17 +0200 (Thu, 02 Oct 2008) New Revision: 3631 Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc Log: CK804 coding-style fixed based on an 'indent' run (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h 2008-10-02 18:19:17 UTC (rev 3631) @@ -1,8 +1,7 @@ #ifndef CK804_CHIP_H #define CK804_CHIP_H -struct southbridge_nvidia_ck804_config -{ +struct southbridge_nvidia_ck804_config { unsigned int usb1_hc_reset : 1; unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; @@ -16,4 +15,4 @@ struct chip_operations; extern struct chip_operations southbridge_nvidia_ck804_ops; -#endif /* CK804_CHIP_H */ +#endif Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -4,9 +4,7 @@ */ #include <console/console.h> - #include <arch/io.h> - #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -15,178 +13,167 @@ static uint32_t final_reg; -static device_t find_lpc_dev( device_t dev, unsigned devfn) +static device_t find_lpc_dev(device_t dev, unsigned devfn) { - device_t lpc_dev; - lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + if (!lpc_dev) + return lpc_dev; - if ( !lpc_dev ) return lpc_dev; + if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) + || ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) + && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) + && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE))) + { + uint32_t id; + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); + if ((id != (PCI_VENDOR_ID_NVIDIA | + (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) + && (id != (PCI_VENDOR_ID_NVIDIA | + (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) + && (id != (PCI_VENDOR_ID_NVIDIA | + (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))) + { + lpc_dev = 0; + } + } - if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || ( - (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) && - (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) && - (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ( (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) && - (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) && - (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))) - ) { - lpc_dev = 0; - } - } - return lpc_dev; } void ck804_enable(device_t dev) { device_t lpc_dev; - unsigned index = 0; - unsigned index2 = 0; + unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; uint32_t reg_old, reg; uint8_t byte; - unsigned deviceid; - unsigned vendorid; - struct southbridge_nvidia_ck804_config *conf; - conf = dev->chip_info; + struct southbridge_nvidia_ck804_config *conf; + conf = dev->chip_info; - unsigned devfn; - - if(dev->device==0x0000) { + if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid>>16) & 0xffff; -// vendorid &= 0xffff; + deviceid = (vendorid >> 16) & 0xffff; + /* vendorid &= 0xffff; */ } else { -// vendorid = dev->vendor; + /* vendorid = dev->vendor; */ deviceid = dev->device; } devfn = (dev->path.u.pci.devfn) & ~7; - switch(deviceid) { - case PCI_DEVICE_ID_NVIDIA_CK804_SM: - index = 16; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_USB: - devfn -= (1<<3); - index = 8; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_USB2: - devfn -= (1<<3); - index = 20; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_NIC: - devfn -= (9<<3); - index = 10; - dev->rom_address = conf->nic_rom_address; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: - devfn -= (9<<3); - index = 10; - dev->rom_address = conf->nic_rom_address; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_ACI: - devfn -= (3<<3); - index = 12; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_MCI: - devfn -= (3<<3); - index = 13; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_IDE: - devfn -= (5<<3); - index = 14; - dev->rom_address = conf->raid_rom_address; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: - devfn -= (6<<3); - index = 22; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: - devfn -= (7<<3); - index = 18; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_PCI: - devfn -= (8<<3); - index = 15; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: - devfn -= (0xa<<3); - index2 = 19; - break; - default: - index = 0; + switch (deviceid) { + case PCI_DEVICE_ID_NVIDIA_CK804_SM: + index = 16; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_USB: + devfn -= (1 << 3); + index = 8; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_USB2: + devfn -= (1 << 3); + index = 20; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_NIC: + devfn -= (9 << 3); + index = 10; + dev->rom_address = conf->nic_rom_address; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: + devfn -= (9 << 3); + index = 10; + dev->rom_address = conf->nic_rom_address; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_ACI: + devfn -= (3 << 3); + index = 12; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_MCI: + devfn -= (3 << 3); + index = 13; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_IDE: + devfn -= (5 << 3); + index = 14; + dev->rom_address = conf->raid_rom_address; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: + devfn -= (6 << 3); + index = 22; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: + devfn -= (7 << 3); + index = 18; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_PCI: + devfn -= (8 << 3); + index = 15; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: + devfn -= (0xa << 3); + index2 = 19; + break; + default: + index = 0; } - if(index2!=0) { + if (index2 != 0) { int i; - for(i=0;i<4;i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); - if(!lpc_dev) continue; + for (i = 0; i < 4; i++) { + lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); + if (!lpc_dev) + continue; index2 -= i; break; } - if ( lpc_dev ) { - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - - if (!dev->enabled) { - reg |= (1<<index2); - } - - if (reg != reg_old) { - pci_write_config32(lpc_dev, 0xe4, reg); - } + if (lpc_dev) { + reg_old = reg = pci_read_config32(lpc_dev, 0xe4); + if (!dev->enabled) + reg |= (1 << index2); + if (reg != reg_old) + pci_write_config32(lpc_dev, 0xe4, reg); } index2 = 0; return; } - lpc_dev = find_lpc_dev(dev, devfn); + if (!lpc_dev) + return; - if ( !lpc_dev ) return; - - if ( index == 0) { - + if (index == 0) { final_reg = pci_read_config32(lpc_dev, 0xe8); - final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15)); - pci_write_config32(lpc_dev, 0xe8, final_reg); + final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10) + | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22) + | (1 << 18) | (1 << 15)); + pci_write_config32(lpc_dev, 0xe8, final_reg); - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - reg |= (1<<20); - if (reg != reg_old) { - pci_write_config32(lpc_dev, 0xe4, reg); - } + reg_old = reg = pci_read_config32(lpc_dev, 0xe4); + reg |= (1 << 20); + if (reg != reg_old) + pci_write_config32(lpc_dev, 0xe4, reg); - byte = pci_read_config8(lpc_dev, 0x74); - byte |= ((1<<1)); - pci_write_config8(dev, 0x74, byte); + byte = pci_read_config8(lpc_dev, 0x74); + byte |= ((1 << 1)); + pci_write_config8(dev, 0x74, byte); - byte = pci_read_config8(lpc_dev, 0xdd); - byte |= ((1<<0)|(1<<3)); - pci_write_config8(dev, 0xdd, byte); + byte = pci_read_config8(lpc_dev, 0xdd); + byte |= ((1 << 0) | (1 << 3)); + pci_write_config8(dev, 0xdd, byte); return; + } - } + if (!dev->enabled) + final_reg |= (1 << index); - if (!dev->enabled) { - final_reg |= (1 << index); - } - - if(index == 10 ) { + if (index == 10) { reg_old = pci_read_config32(lpc_dev, 0xe8); - if (final_reg != reg_old) { - pci_write_config32(lpc_dev, 0xe8, final_reg); - } - + if (final_reg != reg_old) + pci_write_config32(lpc_dev, 0xe8, final_reg); } - } struct chip_operations southbridge_nvidia_ck804_ops = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h 2008-10-02 18:19:17 UTC (rev 3631) @@ -5,4 +5,4 @@ void ck804_enable(device_t dev); -#endif /* CK804_H */ +#endif Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -11,19 +12,19 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; -static struct device_operations ac97audio_ops = { +static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -// .enable = ck804_enable, + // .enable = ck804_enable, .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, @@ -35,12 +36,11 @@ .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, }; - -static struct device_operations ac97modem_ops = { +static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -// .enable = ck804_enable, + // .enable = ck804_enable, .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + static int set_ht_link_ck804(uint8_t ht_c_num) { unsigned vendorid = 0x10de; @@ -9,10 +10,10 @@ return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) +static void setup_ss_table(unsigned index, unsigned where, unsigned control, + const unsigned int *register_values, int max) { int i; - unsigned val; val = inl(control); @@ -21,7 +22,7 @@ outl(0, index); - for(i = 0; i < max; i++) { + for (i = 0; i < max; i++) { unsigned long reg; reg = register_values[i]; outl(reg, where); @@ -29,67 +30,61 @@ val = inl(control); val |= 1; outl(val, control); - } #define ANACTRL_IO_BASE 0x7000 #define ANACTRL_REG_POS 0x68 - #define SYSCTRL_IO_BASE 0x6000 #define SYSCTRL_REG_POS 0x64 /* - 16 1 1 2 :0 - 8 8 2 2 :1 - 8 8 4 :2 - 8 4 4 4 :3 - 16 4 :4 + * 16 1 1 2 :0 + * 8 8 2 2 :1 + * 8 8 4 :2 + * 8 4 4 4 :3 + * 16 4 :4 */ #ifndef CK804_PCI_E_X - #define CK804_PCI_E_X 4 +#define CK804_PCI_E_X 4 #endif #if CK804_NUM > 1 - #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000) - #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000) - - #ifndef CK804B_BUSN - #define CK804B_BUSN 0x80 - #endif - - #ifndef CK804B_PCI_E_X - #define CK804B_PCI_E_X 4 - #endif +#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) +#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000) +#ifndef CK804B_BUSN +#define CK804B_BUSN 0x80 #endif +#ifndef CK804B_PCI_E_X +#define CK804B_PCI_E_X 4 +#endif +#endif #ifndef CK804_USE_NIC - #define CK804_USE_NIC 0 +#define CK804_USE_NIC 0 #endif #ifndef CK804_USE_ACI - #define CK804_USE_ACI 0 +#define CK804_USE_ACI 0 #endif #define CK804_CHIP_REV 3 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - #define CK804B_DEVN_BASE 1 +#define CK804B_DEVN_BASE 1 #else - #define CK804B_DEVN_BASE CK804_DEVN_BASE +#define CK804B_DEVN_BASE CK804_DEVN_BASE #endif - static void ck804_early_set_port(void) { - static const unsigned int ctrl_devport_conf[] = { PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, #if CK804_NUM > 1 @@ -103,12 +98,10 @@ }; setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); - } static void ck804_early_clear_port(void) { - static const unsigned int ctrl_devport_conf_clear[] = { PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, #if CK804_NUM > 1 @@ -122,84 +115,70 @@ }; setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); - } static void ck804_early_setup(void) { - static const unsigned int ctrl_conf[] = { + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, - - #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, #endif + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, - - #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, #endif + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, - #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, #endif + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, - #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, #endif + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, - - - #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, @@ -208,139 +187,125 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, #if CK804_NUM > 1 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, #endif - // Activate master port on primary SATA controller - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000, + /* Activate master port on primary SATA controller. */ + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, - + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, #endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), #endif - - - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), + RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), #endif #if CK804_USE_ACI == 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif #if CK804_NUM > 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), #endif - #if CK804_NUM > 1 - #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), - #endif +#if CK804_USE_NIC == 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif +#endif - - #ifdef CK804_MB_SETUP CK804_MB_SETUP #endif - }; - - setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); - setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); #if CK804_NUM > 1 - setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64); - setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64); - setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64); + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); #endif #if 0 dump_io_resources(ANACTRL_IO_BASE); dump_io_resources(SYSCTRL_IO_BASE); #endif - } static int ck804_early_setup_x(void) @@ -369,4 +334,3 @@ outb(0x06, 0x0cf9); #endif } - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -11,365 +11,339 @@ return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) +static void setup_ss_table(unsigned index, unsigned where, unsigned control, + const unsigned int *register_values, int max) { int i; - unsigned val; + val = inl(control); val &= 0xfffffffe; outl(val, control); outl(0, index); - for(i = 0; i < max; i++) { + for (i = 0; i < max; i++) { unsigned long reg; - reg = register_values[i]; outl(reg, where); } + val = inl(control); val |= 1; outl(val, control); - } #define ANACTRL_IO_BASE 0x3000 #define ANACTRL_REG_POS 0x68 - #define SYSCTRL_IO_BASE 0x2000 #define SYSCTRL_REG_POS 0x64 /* - 16 1 1 2 :0 - 8 8 2 2 :1 - 8 8 4 :2 - 8 4 4 4 :3 - 16 4 :4 + * 16 1 1 2 :0 + * 8 8 2 2 :1 + * 8 8 4 :2 + * 8 4 4 4 :3 + * 16 4 :4 */ #ifndef CK804_PCI_E_X - #define CK804_PCI_E_X 4 +#define CK804_PCI_E_X 4 #endif - /* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */ - #define CK804B_ANACTRL_IO_BASE 0x3000 - #define CK804B_SYSCTRL_IO_BASE 0x2000 +/* + * We will use the offset in setup_resource_map_x_offset and + * setup_resource_map_offset. + */ +#define CK804B_ANACTRL_IO_BASE 0x3000 +#define CK804B_SYSCTRL_IO_BASE 0x2000 - #ifdef CK804B_BUSN - #undef CK804B_BUSN - #endif - #define CK804B_BUSN 0x0 +#ifdef CK804B_BUSN +#undef CK804B_BUSN +#endif +#define CK804B_BUSN 0x0 - #ifndef CK804B_PCI_E_X - #define CK804B_PCI_E_X 4 - #endif +#ifndef CK804B_PCI_E_X +#define CK804B_PCI_E_X 4 +#endif #ifndef CK804_USE_NIC - #define CK804_USE_NIC 0 +#define CK804_USE_NIC 0 #endif #ifndef CK804_USE_ACI - #define CK804_USE_ACI 0 +#define CK804_USE_ACI 0 #endif #define CK804_CHIP_REV 3 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - #define CK804B_DEVN_BASE 1 +#define CK804B_DEVN_BASE 1 #else - #define CK804B_DEVN_BASE CK804_DEVN_BASE +#define CK804B_DEVN_BASE CK804_DEVN_BASE #endif -static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) +static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, + unsigned *io_base) { - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, }; static const unsigned int ctrl_devport_conf_b[] = { - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, }; int j; - for(j = 0; j < ck804_num; j++ ) { - if(busn[j]==0) { //sb chain + for (j = 0; j < ck804_num; j++) { + if (busn[j] == 0) { //sb chain setup_resource_map_offset(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf), - PCI_DEV(busn[j], 0, 0) , io_base[j]); + PCI_DEV(busn[j], 0, 0), io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_b, - ARRAY_SIZE(ctrl_devport_conf_b), - PCI_DEV(busn[j], 0, 0) , io_base[j]); + ARRAY_SIZE(ctrl_devport_conf_b), + PCI_DEV(busn[j], 0, 0), io_base[j]); } } -static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) +static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, + unsigned *io_base) { - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, }; static const unsigned int ctrl_devport_conf_clear_b[] = { - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, }; int j; - for(j = 0; j < ck804_num; j++ ) { - if(busn[j]==0) { //sb chain + for (j = 0; j < ck804_num; j++) { + if (busn[j] == 0) { //sb chain setup_resource_map_offset(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear), - PCI_DEV(busn[j], 0, 0) , io_base[j]); + PCI_DEV(busn[j], 0, 0), io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_clear_b, - ARRAY_SIZE(ctrl_devport_conf_clear_b), - PCI_DEV(busn[j], 0, 0) , io_base[j]); + ARRAY_SIZE(ctrl_devport_conf_clear_b), + PCI_DEV(busn[j], 0, 0), io_base[j]); } - - } - -static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base) +static void ck804_early_setup(unsigned ck804_num, unsigned *busn, + unsigned *io_base) { - static const unsigned int ctrl_conf_master[] = { + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, - - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, - - #ifdef CK804_MB_SETUP - CK804_MB_SETUP + CK804_MB_SETUP #endif - - #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, - + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, #endif #if CK804_NUM == 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, - + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), +// PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, -//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), - - //SYSCTRL - - - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif #if CK804_USE_ACI == 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif #if CK804_NUM > 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), #endif - - }; - - - static const unsigned int ctrl_conf_slave[] = { + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, +//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), - - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), - -//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, - - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, - - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), - - #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), - #endif - +#if CK804_USE_NIC == 1 + RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), +#endif }; int j; - - for(j=0; j<ck804_num; j++) { - if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(busn[0],0,0), io_base[0]); + for (j = 0; j < ck804_num; j++) { + if (busn[j] == 0) { + setup_resource_map_x_offset(ctrl_conf_master, + ARRAY_SIZE(ctrl_conf_master), + PCI_DEV(busn[0], 0, 0), io_base[0]); continue; } - - setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave), - PCI_DEV(busn[j],0,0), io_base[j]); + setup_resource_map_x_offset(ctrl_conf_slave, + ARRAY_SIZE(ctrl_conf_slave), + PCI_DEV(busn[j], 0, 0), io_base[j]); } - for(j=0; j< ck804_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, - io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, - io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); -//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, -// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); + for (j = 0; j < ck804_num; j++) { + /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ + /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ + /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, + io_base[j] + ANACTRL_IO_BASE + 0x44, + io_base[j] + ANACTRL_IO_BASE + 0x48, + pcie_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, + io_base[j] + ANACTRL_IO_BASE + 0xb4, + io_base[j] + ANACTRL_IO_BASE + 0xb8, + sata_ss_tbl, 64); +//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, +// io_base[j] + ANACTRL_IO_BASE + 0xc4, +// io_base[j] + ANACTRL_IO_BASE + 0xc8, +// cpu_ss_tbl, 64); } - - } static int ck804_early_setup_x(void) { - unsigned busn[4]; - unsigned io_base[4]; - int ck804_num = 0; - int i; + unsigned busn[4], io_base[4]; + int i, ck804_num = 0; - for(i=0;i<4;i++) { + for (i = 0; i < 4; i++) { uint32_t id; device_t dev; - if(i == 0) { // SB chain - dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0); - } - else { - dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0); - } + if (i == 0) // SB chain + dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); + else + dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); - if(id == 0x005e10de) { + if (id == 0x005e10de) { busn[ck804_num] = i * 0x40; io_base[ck804_num] = i * 0x4000; ck804_num++; @@ -379,6 +353,7 @@ ck804_early_set_port(ck804_num, busn, io_base); ck804_early_setup(ck804_num, busn, io_base); ck804_early_clear_port(ck804_num, busn, io_base); + return set_ht_link_ck804(4); } @@ -399,4 +374,3 @@ outb(0x02, 0x0cf9); outb(0x06, 0x0cf9); } - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h 2008-10-02 18:19:17 UTC (rev 3631) @@ -69,6 +69,7 @@ 0x0C5042040, 0x0C5042040, }; + static const unsigned int sata_ss_tbl[] = { 0x0c9044042, 0x0c9044042, @@ -202,5 +203,3 @@ 0x0C5039037, 0x0C5039037, }; - - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -11,16 +11,18 @@ { device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } + if (dev == PCI_DEV_INVALID) + die("SMBus controller not found\r\n"); print_debug("SMBus controller enabled\r\n"); - /* set smbus iobase */ + + /* Set SMBus I/O base. */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - /* Set smbus iospace enable */ + + /* Set SMBus I/O space enable. */ pci_write_config16(dev, 0x4, 0x01); - /* clear any lingering errors, so the transaction will run */ + + /* Clear any lingering errors, so the transaction will run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } @@ -28,7 +30,9 @@ { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) + +static int smbus_write_byte(unsigned device, unsigned address, + unsigned char val) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,10 +2,11 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif static void ck804_enable_rom(void) @@ -13,11 +14,11 @@ unsigned char byte; device_t addr; - /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ - /* Locate the ck804 LPC */ - addr = PCI_DEV(0, (CK804_DEVN_BASE+1), 0); + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ + /* Locate the ck804 LPC. */ + addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); - /* Set the 4MB enable bit bit */ + /* Set the 4MB enable bit. */ byte = pci_read_config8(addr, 0x88); byte |= 0x80; pci_write_config8(addr, 0x88, byte); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -12,13 +13,14 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations ht_ops = { +static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -32,4 +34,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, }; - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -13,61 +13,61 @@ static void ide_init(struct device *dev) { struct southbridge_nvidia_ck804_config *conf; - /* Enable ide devices so the linux ide driver will work */ uint32_t dword; uint16_t word; uint8_t byte; + conf = dev->chip_info; word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled */ + /* Ensure prefetch is disabled. */ word &= ~((1 << 15) | (1 << 13)); if (conf->ide1_enable) { - /* Enable secondary ide interface */ - word |= (1<<0); + /* Enable secondary IDE interface. */ + word |= (1 << 0); printk_debug("IDE1 \t"); } if (conf->ide0_enable) { - /* Enable primary ide interface */ - word |= (1<<1); + /* Enable primary IDE interface. */ + word |= (1 << 1); printk_debug("IDE0\n"); } - word |= (1<<12); - word |= (1<<14); + word |= (1 << 12); + word |= (1 << 14); pci_write_config16(dev, 0x50, word); - - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; /* Latency: 64 --> 32 */ pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); dword |= 12; pci_write_config32(dev, 0xf8, dword); + #if CONFIG_PCI_ROM_RUN == 1 pci_dev_init(dev); #endif - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations ide_ops = { +static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = ck804_enable, - .ops_pci = &lops_pci, + .init = ide_init, + .scan_bus = 0, + // .enable = ck804_enable, + .ops_pci = &lops_pci, }; static const struct pci_driver ide_driver __pci_driver = { @@ -75,4 +75,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, }; - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -4,6 +4,7 @@ * by yhlu(a)tyan.com * 2006.1 yhlu add dest apicid for IRQ0 */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -44,30 +45,30 @@ #define INT (1 << 8) /* IO-APIC virtual wire mode configuration */ /* mask, trigger, polarity, destination, delivery, vector */ - { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, - { 1, DISABLED, NONE}, - { 2, DISABLED, NONE}, - { 3, DISABLED, NONE}, - { 4, DISABLED, NONE}, - { 5, DISABLED, NONE}, - { 6, DISABLED, NONE}, - { 7, DISABLED, NONE}, - { 8, DISABLED, NONE}, - { 9, DISABLED, NONE}, - { 10, DISABLED, NONE}, - { 11, DISABLED, NONE}, - { 12, DISABLED, NONE}, - { 13, DISABLED, NONE}, - { 14, DISABLED, NONE}, - { 15, DISABLED, NONE}, - { 16, DISABLED, NONE}, - { 17, DISABLED, NONE}, - { 18, DISABLED, NONE}, - { 19, DISABLED, NONE}, - { 20, DISABLED, NONE}, - { 21, DISABLED, NONE}, - { 22, DISABLED, NONE}, - { 23, DISABLED, NONE}, + {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, + {1, DISABLED, NONE}, + {2, DISABLED, NONE}, + {3, DISABLED, NONE}, + {4, DISABLED, NONE}, + {5, DISABLED, NONE}, + {6, DISABLED, NONE}, + {7, DISABLED, NONE}, + {8, DISABLED, NONE}, + {9, DISABLED, NONE}, + {10, DISABLED, NONE}, + {11, DISABLED, NONE}, + {12, DISABLED, NONE}, + {13, DISABLED, NONE}, + {14, DISABLED, NONE}, + {15, DISABLED, NONE}, + {16, DISABLED, NONE}, + {17, DISABLED, NONE}, + {18, DISABLED, NONE}, + {19, DISABLED, NONE}, + {20, DISABLED, NONE}, + {21, DISABLED, NONE}, + {22, DISABLED, NONE}, + {23, DISABLED, NONE}, /* Be careful and don't write past the end... */ }; @@ -75,23 +76,22 @@ { int i; unsigned long value_low, value_high; -// unsigned long ioapic_base = 0xfec00000; + /* unsigned long ioapic_base = 0xfec00000; */ volatile unsigned long *l; struct ioapicreg *a = ioapicregvalues; - ioapicregvalues[0].value_high = lapicid()<<(56-32); + ioapicregvalues[0].value_high = lapicid() << (56 - 32); - l = (unsigned long *) ioapic_base; + l = (unsigned long *)ioapic_base; - for (i = 0; i < ARRAY_SIZE(ioapicregvalues); - i++, a++) { + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; value_low = l[4]; - l[0] = (a->reg *2) + 0x11; + l[0] = (a->reg * 2) + 0x11; l[4] = a->value_high; value_high = l[4]; - if ((i==0) && (value_low == 0xffffffff)) { + if ((i == 0) && (value_low == 0xffffffff)) { printk_warning("IO APIC not responding.\n"); return; } @@ -117,20 +117,19 @@ uint8_t byte; uint32_t dword; - /* IO APIC initialization */ + /* I/O APIC initialization */ byte = pci_read_config8(dev, 0x74); - byte |= (1<<0); // enable APIC + byte |= (1 << 0); /* Enable APIC. */ pci_write_config8(dev, 0x74, byte); - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ setup_ioapic(dword); #if 1 dword = pci_read_config32(dev, 0xe4); - dword |= (1<<23); + dword |= (1 << 23); pci_write_config32(dev, 0xe4, dword); #endif - } static void lpc_slave_init(device_t dev) @@ -138,132 +137,123 @@ lpc_common_init(dev); } -static void rom_dummy_write(device_t dev){ +static void rom_dummy_write(device_t dev) +{ uint8_t old, new; uint8_t *p; old = pci_read_config8(dev, 0x88); new = old | 0xc0; - if (new != old) { + if (new != old) pci_write_config8(dev, 0x88, new); - } - // enable write + /* Enable write. */ old = pci_read_config8(dev, 0x6d); new = old | 0x01; - if (new != old) { + if (new != old) pci_write_config8(dev, 0x6d, new); - } - /* dummy write */ - p = (uint8_t *)0xffffffe0; + /* Dummy write. */ + p = (uint8_t *) 0xffffffe0; old = 0; *p = old; old = *p; - // disable write + /* Disable write. */ old = pci_read_config8(dev, 0x6d); new = old & 0xfe; - if (new != old) { + if (new != old) pci_write_config8(dev, 0x6d, new); - - } - } + #if 0 static void enable_hpet(struct device *dev) { unsigned long hpet_address; - pci_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk_debug("enabling HPET @0x%x\n", hpet_address); + pci_write_config32(dev, 0x44, 0xfed00001); + hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; + printk_debug("Enabling HPET @0x%x\n", hpet_address); } #endif static void lpc_init(device_t dev) { - uint8_t byte; - uint8_t byte_old; - int on; - int nmi_option; + uint8_t byte, byte_old; + int on, nmi_option; lpc_common_init(dev); #if CK804_CHIP_REV==1 - if(dev->bus->secondary!=1) return; + if (dev->bus->secondary != 1) + return; #endif #if 0 - /* posted memory write enable */ + /* Posted memory write enable */ byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); - + pci_write_config8(dev, 0x46, byte | (1 << 0)); #endif - /* power after power fail */ + /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; - if (!on) { + if (!on) byte |= 0x40; - } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + printk_info("set power %s after power fail\n", on ? "on" : "off"); - /* Throttle the CPU speed down for testing */ + /* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); - if(on) { + if (on) { uint16_t pm10_bar; uint32_t dword; - pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); - outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); + pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); + outl(((on << 1) + 0x10), (pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); - on = 8-on; + on = 8 - on; printk_debug("Throttling CPU %2d.%1.1d percent.\n", - (on*12)+(on>>1),(on&1)*5); + (on * 12) + (on >> 1), (on & 1) * 5); } - #if 0 // default is enabled - /* Enable Port 92 fast reset */ + /* Enable Port 92 fast reset. */ byte = pci_read_config8(dev, 0xe8); byte |= ~(1 << 3); pci_write_config8(dev, 0xe8, byte); #endif - /* Enable Error reporting */ - /* Set up sync flood detected */ + /* Enable Error reporting. */ + /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); byte |= (1 << 1); pci_write_config8(dev, 0x47, byte); - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 + /* Set up NMI on errors. */ + byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ + byte &= ~(1 << 7); /* Set NMI. */ } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ } - if( byte != byte_old) { + if (byte != byte_old) outb(0x70, byte); - } - /* Initialize the real time clock */ + /* Initialize the real time clock (RTC). */ rtc_init(0); - /* Initialize isa dma */ + /* Initialize ISA DMA. */ isa_dma_init(); - /* Initialize the High Precision Event Timers */ -// enable_hpet(dev); + /* Initialize the High Precision Event Timers (HPET). */ + /* enable_hpet(dev); */ rom_dummy_write(dev); - } static void ck804_lpc_read_resources(device_t dev) @@ -271,43 +261,43 @@ struct resource *res; unsigned long index; - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP + /* Get the normal PCI resources of this device. */ + /* We got one for APIC, or one more for TRAP. */ + pci_dev_read_resources(dev); - /* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */ - for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. + /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ + for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ pci_get_resource(dev, index); - } compact_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + res->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } /** - * @brief Enable resources for children devices + * Enable resources for children devices. * - * @param dev the device whos children's resources are to be enabled - * - * This function is call by the global enable_resources() indirectly via the + * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. * * Indirect mutual recursion: * enable_childrens_resources() -> enable_resources() * enable_resources() -> device_operation::enable_resources() * device_operation::enable_resources() -> enable_children_resources() + * + * @param dev The device whose children's resources are to be enabled. */ static void ck804_lpc_enable_childrens_resources(device_t dev) { unsigned link; uint32_t reg, reg_var[4]; - int i; - int var_num = 0; + int i, var_num = 0; reg = pci_read_config32(dev, 0xa0); @@ -315,44 +305,49 @@ device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { - for(i=0;i<child->resources;i++) { + if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + for (i = 0; i < child->resources; i++) { struct resource *res; - unsigned long base, end; // don't need long long + unsigned long base, end; // don't need long long res = &child->resource[i]; - if(!(res->flags & IORESOURCE_IO)) continue; + if (!(res->flags & IORESOURCE_IO)) + continue; base = res->base; end = resource_end(res); - printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); - switch(base) { - case 0x3f8: // COM1 - reg |= (1<<0); break; - case 0x2f8: // COM2 - reg |= (1<<1); break; - case 0x378: // Parallal 1 - reg |= (1<<24); break; - case 0x3f0: // FD0 - reg |= (1<<20); break; - case 0x220: // Aduio 0 - reg |= (1<<8); break; - case 0x300: // Midi 0 - reg |= (1<<12); break; + printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end); + switch (base) { + case 0x3f8: // COM1 + reg |= (1 << 0); + break; + case 0x2f8: // COM2 + reg |= (1 << 1); + break; + case 0x378: // Parallel 1 + reg |= (1 << 24); + break; + case 0x3f0: // FD0 + reg |= (1 << 20); + break; + case 0x220: // Audio 0 + reg |= (1 << 8); + break; + case 0x300: // Midi 0 + reg |= (1 << 12); + break; } - if( base == 0x290 || base >= 0x400) { - if(var_num>=4) continue; // only 4 var ; compact them ? - reg |= (1<<(28+var_num)); - reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); + if (base == 0x290 || base >= 0x400) { + if (var_num >= 4) + continue; // only 4 var ; compact them ? + reg |= (1 << (28 + var_num)); + reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); } } } } } pci_write_config32(dev, 0xa0, reg); - for(i=0;i<var_num;i++) { - pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); - } - - + for (i = 0; i < var_num; i++) + pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } static void ck804_lpc_enable_resources(device_t dev) @@ -364,22 +359,23 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations lpc_ops = { +static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = ck804_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, -// .enable = ck804_enable, + // .enable = ck804_enable, .ops_pci = &lops_pci, }; + static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_NVIDIA, @@ -399,12 +395,12 @@ .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, }; #else -static struct device_operations lpc_slave_ops = { +static struct device_operations lpc_slave_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_slave_init, -// .enable = ck804_enable, + // .enable = ck804_enable, .ops_pci = &lops_pci, }; Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <device/smbus.h> @@ -11,21 +12,16 @@ #include <arch/io.h> #include "ck804.h" - static void nic_init(struct device *dev) { - uint32_t dword, old; - uint32_t mac_h, mac_l; + uint32_t dword, old, mac_h, mac_l; int eeprom_valid = 0; struct southbridge_nvidia_ck804_config *conf; - static uint32_t nic_index = 0; - uint8_t *base; struct resource *res; res = find_resource(dev, 0x10); - base = res->base; #define NvRegPhyInterface 0xC0 @@ -36,37 +32,37 @@ old = dword = pci_read_config32(dev, 0x30); dword &= ~(0xf); dword |= 0xf; - if(old != dword) { - pci_write_config32(dev, 0x30 , dword); - } + if (old != dword) + pci_write_config32(dev, 0x30, dword); conf = dev->chip_info; - if(conf->mac_eeprom_smbus != 0) { -// read MAC address from EEPROM at first + if (conf->mac_eeprom_smbus != 0) { + /* Read MAC address from EEPROM at first. */ struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); + dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, + conf->mac_eeprom_addr); - if(dev_eeprom) { - // if that is valid we will use that + if (dev_eeprom) { + /* If that is valid we will use that. */ unsigned char dat[6]; - int status; - int i; - for(i=0;i<6;i++) { + int i, status; + for (i = 0; i < 6; i++) { status = smbus_read_byte(dev_eeprom, i); - if(status < 0) break; + if (status < 0) + break; dat[i] = status & 0xff; } - if(status >= 0) { + if (status >= 0) { mac_l = 0; - for(i=3;i>=0;i--) { + for (i = 3; i >= 0; i--) { mac_l <<= 8; mac_l += dat[i]; } - if(mac_l != 0xffffffff) { + if (mac_l != 0xffffffff) { mac_l += nic_index; mac_h = 0; - for(i=5;i>=4;i--) { + for (i = 5; i >= 4; i--) { mac_h <<= 8; mac_h += dat[i]; } @@ -75,21 +71,22 @@ } } } -// if that is invalid we will read that from romstrap - if(!eeprom_valid) { + + /* If that is invalid we will read that from romstrap. */ + if (!eeprom_valid) { unsigned long mac_pos; - mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds + mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ mac_l = readl(mac_pos) + nic_index; mac_h = readl(mac_pos + 4); } #if 1 -// set that into NIC MMIO + /* Set that into NIC MMIO. */ #define NvRegMacAddrA 0xA8 #define NvRegMacAddrB 0xAC writel(mac_l, base + NvRegMacAddrA); writel(mac_h, base + NvRegMacAddrB); #else -// set that into NIC + /* Set that into NIC. */ pci_write_config32(dev, 0xa8, mac_l); pci_write_config32(dev, 0xac, mac_h); #endif @@ -97,35 +94,36 @@ nic_index++; #if CONFIG_PCI_ROM_RUN == 1 - pci_dev_init(dev);// it will init option rom + pci_dev_init(dev); /* It will init Option ROM. */ #endif - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations nic_ops = { +static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nic_init, .scan_bus = 0, -// .enable = ck804_enable, + // .enable = ck804_enable, .ops_pci = &lops_pci, }; + static const struct pci_driver nic_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, }; + static const struct pci_driver nic_bridge_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_NVIDIA, Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -12,70 +12,72 @@ static void pci_init(struct device *dev) { - uint32_t dword; #if CONFIG_PCI_64BIT_PREF_MEM == 1 device_t pci_domain_dev; struct resource *mem1, *mem2; #endif - /* System error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ + dword |= (1 << 8); /* System error enable */ + dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); #if 0 word = pci_read_config16(dev, 0x48); - word |= (1<<0); /* MRL2MRM */ - word |= (1<<2); /* MR2MRM */ + word |= (1 << 0); /* MRL2MRM */ + word |= (1 << 2); /* MR2MRM */ pci_write_config16(dev, 0x48, word); #endif #if 1 dword = pci_read_config32(dev, 0x4c); - dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ + dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ pci_write_config32(dev, 0x4c, dword); #endif #if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; - while(pci_domain_dev) { - if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; + while (pci_domain_dev) { + if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) + break; pci_domain_dev = pci_domain_dev->bus->dev; } - if(!pci_domain_dev) return; // impossiable - mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit - mem2 = find_resource(pci_domain_dev, 2); // mem - if(mem1->base > mem2->base) { - dword = mem2->base & (0xffff0000UL); + if (!pci_domain_dev) + return; /* Impossible */ + + mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit + mem2 = find_resource(pci_domain_dev, 2); // mem + if (mem1->base > mem2->base) { + dword = mem2->base & (0xffff0000UL); printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); } else { - dword = mem1->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); + dword = mem1->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", + mem1->base); } #else dword = dev_root.resource[1].base & (0xffff0000UL); - printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); + printk_debug("dev_root mem base = 0x%010Lx\n", + dev_root.resource[1].base); #endif printk_debug("[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); //TOM - + pci_write_config32(dev, 0x50, dword); /* TOM */ } static struct pci_operations lops_pci = { .set_subsystem = 0, }; -static struct device_operations pci_ops = { +static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, -// .enable = ck804_enable, + // .enable = ck804_enable, .ops_pci = &lops_pci, }; @@ -84,4 +86,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, }; - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -12,29 +12,26 @@ static void pcie_init(struct device *dev) { - - /* Enable pci error detecting */ uint32_t dword; - /* System error enable */ + /* Enable PCI error detecting. */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ + dword |= (1 << 8); /* System error enable */ + dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); - } static struct pci_operations lops_pci = { .set_subsystem = 0, }; -static struct device_operations pcie_ops = { +static struct device_operations pcie_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pcie_init, .scan_bus = pci_scan_bridge, -// .enable = ck804_enable, + // .enable = ck804_enable, .ops_pci = &lops_pci, }; @@ -43,4 +40,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, }; - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -15,7 +15,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) { unsigned addr; - addr = (dev>>4) | where; + addr = (dev >> 4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } @@ -23,7 +23,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = (dev>>4) | where; + addr = (dev >> 4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } @@ -33,8 +33,7 @@ void hard_reset(void) { set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); + /* Try rebooting through port 0xcf9. */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); } - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <delay.h> @@ -10,7 +11,6 @@ #include <device/pci_ops.h> #include "ck804.h" - static void sata_com_reset(struct device *dev, unsigned reset) // reset = 1 : reset // reset = 0 : clear @@ -23,12 +23,12 @@ printk_debug("base = %08x\r\n", base); - if(reset) { - *(base + 4) = 0xffffffff; - *(base + 0x44) = 0xffffffff; + if (reset) { + *(base + 4) = 0xffffffff; + *(base + 0x44) = 0xffffffff; } - dword = *(base +8); + dword = *(base + 8); dword &= ~(0xf); dword |= reset; @@ -42,87 +42,89 @@ *(base + 0x48) = dword; #endif - if(reset) return; + if (reset) + return; - dword = *(base+ 0); - printk_debug("*(base+0)=%08x\r\n",dword); - if(dword == 0x113) { - loop = 200000;// 2 + dword = *(base + 0); + printk_debug("*(base+0)=%08x\r\n", dword); + if (dword == 0x113) { + loop = 200000; // 2 do { - dword = *(base + 4); - if((dword & 0x10000)!=0) break; + dword = *(base + 4); + if ((dword & 0x10000) != 0) + break; udelay(10); - } while (--loop>0); - printk_debug("loop=%d, *(base+4)=%08x\r\n",loop, dword); + } while (--loop > 0); + printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword); } - dword = *(base+ 0x40); - printk_debug("*(base+0x40)=%08x\r\n",dword); - if(dword == 0x113) { - loop = 200000;//2 - do { - dword = *(base + 0x44); - if((dword & 0x10000)!=0) break; + dword = *(base + 0x40); + printk_debug("*(base+0x40)=%08x\r\n", dword); + if (dword == 0x113) { + loop = 200000; //2 + do { + dword = *(base + 0x44); + if ((dword & 0x10000) != 0) + break; udelay(10); - } while (--loop>0); - printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop, dword); + } while (--loop > 0); + printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword); } } static void sata_init(struct device *dev) { - uint32_t dword; + struct southbridge_nvidia_ck804_config *conf; - struct southbridge_nvidia_ck804_config *conf; conf = dev->chip_info; dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled */ + /* Ensure prefetch is disabled. */ dword &= ~((1 << 15) | (1 << 13)); if (conf->sata1_enable) { - /* Enable secondary SATA interface */ - dword |= (1<<0); - printk_debug("SATA S \t"); + /* Enable secondary SATA interface. */ + dword |= (1 << 0); + printk_debug("SATA S \t"); } if (conf->sata0_enable) { - /* Enable primary SATA interface */ - dword |= (1<<1); - printk_debug("SATA P \n"); + /* Enable primary SATA interface. */ + dword |= (1 << 1); + printk_debug("SATA P \n"); } #if 0 -// write back - dword |= (1<<12); - dword |= (1<<14); + /* Write back */ + dword |= (1 << 12); + dword |= (1 << 14); #endif #if 0 -// ADMA - dword |= (1<<16); - dword |= (1<<17); + /* ADMA */ + dword |= (1 << 16); + dword |= (1 << 17); #endif #if 1 -//DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. - dword &= ~(0x1f<<24); - dword |= (0x15<<24); + /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ + dword &= ~(0x1f << 24); + dword |= (0x15 << 24); #endif pci_write_config32(dev, 0x50, dword); #if 0 -//SLUMBER_DURING_D3. + /* SLUMBER_DURING_D3 */ dword = pci_read_config32(dev, 0x7c); - dword &= ~(1<<4); + dword &= ~(1 << 4); pci_write_config32(dev, 0x7c, dword); dword = pci_read_config32(dev, 0xd0); - dword &= ~(0xff<<24); - dword |= (0x68<<24); + dword &= ~(0xff << 24); + dword |= (0x68 << 24); pci_write_config32(dev, 0xd0, dword); dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff<<24); - dword |= (0x68<<24); + dword &= ~(0xff << 24); + dword |= (0x68 << 24); pci_write_config32(dev, 0xe0, dword); #endif @@ -132,11 +134,11 @@ #if 0 dword = pci_read_config32(dev, 0xac); - dword &= ~((1<<13)|(1<<14)); - dword |= (1<<13)|(0<<14); + dword &= ~((1 << 13) | (1 << 14)); + dword |= (1 << 13) | (0 << 14); pci_write_config32(dev, 0xac, dword); - sata_com_reset(dev, 1); // for discover some s-atapi device + sata_com_reset(dev, 1); /* For discover some s-atapi device. */ #endif } @@ -144,17 +146,18 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations sata_ops = { +static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -// .enable = ck804_enable, + // .enable = ck804_enable, .init = sata_init, .scan_bus = 0, .ops_pci = &lops_pci, Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -68,6 +69,7 @@ return do_smbus_write_byte(res->base, device, address, val); } + static struct smbus_bus_operations lops_smbus_bus = { .recv_byte = lsmbus_recv_byte, .send_byte = lsmbus_send_byte, @@ -78,25 +80,26 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; + static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, -// .enable = ck804_enable, + // .enable = ck804_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; + static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, }; - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,19 +2,21 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <device/smbus_def.h> -#define SMBHSTSTAT 0x1 -#define SMBHSTPRTCL 0x0 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x2 -#define SMBHSTDAT0 0x4 -#define SMBHSTDAT1 0x5 +#define SMBHSTSTAT 0x1 +#define SMBHSTPRTCL 0x0 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x2 +#define SMBHSTDAT0 0x4 +#define SMBHSTDAT1 0x5 -/* Between 1-10 seconds, We should never timeout normally +/* + * Between 1-10 seconds, We should never timeout normally. * Longer than this is just painful when a timeout condition occurs. */ -#define SMBUS_TIMEOUT (100*1000*10) +#define SMBUS_TIMEOUT (100 * 1000 * 10) static inline void smbus_delay(void) { @@ -30,11 +32,10 @@ smbus_delay(); val = inb(smbus_io_base + SMBHSTSTAT); val &= 0x1f; - if (val == 0) { + if (val == 0) return 0; - } - outb(val,smbus_io_base + SMBHSTSTAT); - } while(--loops); + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); return -2; } @@ -45,158 +46,164 @@ do { unsigned char val; smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - if ( (val & 0xff) != 0) { + if ((val & 0xff) != 0) return 0; - } - } while(--loops); + } while (--loops); return -3; } + static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { - unsigned char global_status_register; - unsigned char byte; + unsigned char global_status_register, byte; + #if 0 -// Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; - } #endif - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + /* Set the device I'm talking to. */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); - /* set the command/address... */ + + /* Set the command/address. */ outb(0, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* byte data recv */ + + /* Byte data recv */ outb(0x05, smbus_io_base + SMBHSTPRTCL); smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - /* read results of transaction */ + /* Read results of transaction. */ byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + /* Lose check, otherwise it should be 0. */ + if (global_status_register != 0x80) return -1; - } + return byte; } -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) + +static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, + unsigned char val) { unsigned global_status_register; #if 0 -// Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; - } #endif outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); - /* set the device I'm talking too */ + /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); smbus_delay(); outb(0, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* set up for a byte data write */ + /* Set up for a byte data write. */ outb(0x04, smbus_io_base + SMBHSTPRTCL); smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - if (global_status_register != 0x80) { + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; + + if (global_status_register != 0x80) return -1; - } + return 0; } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) + +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, + unsigned address) { - unsigned char global_status_register; - unsigned char byte; + unsigned char global_status_register, byte; + #if 0 -// Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; - } #endif - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + /* Set the device I'm talking to. */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); - /* set the command/address... */ + + /* Set the command/address. */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* byte data read */ + + /* Byte data read */ outb(0x07, smbus_io_base + SMBHSTPRTCL); smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - /* read results of transaction */ + /* Read results of transaction. */ byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + /* Lose check, otherwise it should be 0. */ + if (global_status_register != 0x80) return -1; - } + return byte; } - -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, + unsigned address, unsigned char val) { unsigned global_status_register; #if 0 -// Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; - } #endif outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); - /* set the device I'm talking too */ + /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); smbus_delay(); outb(address & 0xff, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* set up for a byte data write */ + /* Set up for a byte data write. */ outb(0x06, smbus_io_base + SMBHSTPRTCL); smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - if (global_status_register != 0x80) { + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; + + if (global_status_register != 0x80) return -1; - } + return 0; } - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -9,34 +10,41 @@ #include <device/pci_ops.h> #include "ck804.h" -static void usb1_init(struct device *dev) { - struct southbridge_nvidia_ck804_config const * conf=dev->chip_info; +static void usb1_init(struct device *dev) +{ + struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; if (conf->usb1_hc_reset) { - //Somehow the warm reset does not really resets the USB controller. - //Later, during boot, when the Bus Master bit is set, the USB - //controller trashes the memory, causing weird misbehavior. - //Was detected on Sun Ultra40, where mptable was damaged. - uint32_t bar0=pci_read_config32(dev,0x10); - uint32_t* regs=(uint32_t*)(bar0&~0xfff); - regs[2]|=1; //OHCI USB HCCommandStatus Register, HostControllerReset bit + /* + * Somehow the warm reset does not really reset the USB + * controller. Later, during boot, when the Bus Master bit is + * set, the USB controller trashes the memory, causing weird + * misbehavior. Was detected on Sun Ultra40, where mptable + * was damaged. + */ + uint32_t bar0 = pci_read_config32(dev, 0x10); + uint32_t *regs = (uint32_t *) (bar0 & ~0xfff); + + /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ + regs[2] |= 1; } } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations usb_ops = { +static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb1_init, -// .enable = ck804_enable, + // .enable = ck804_enable, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -46,4 +54,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, }; - Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -11,7 +12,6 @@ static void usb2_init(struct device *dev) { - uint32_t dword; dword = pci_read_config32(dev, 0xf8); dword |= 40; @@ -21,18 +21,19 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; -static struct device_operations usb2_ops = { +static struct device_operations usb2_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb2_init, -// .enable = ck804_enable, + // .enable = ck804_enable, .scan_bus = 0, .ops_pci = &lops_pci, }; Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc 2008-10-02 18:19:17 UTC (rev 3631) @@ -1,4 +1,3 @@ - .section ".id", "a", @progbits .globl __id_start @@ -7,9 +6,9 @@ .asciz MAINBOARD_VENDOR part: .asciz MAINBOARD_PART_NUMBER -.long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ -.long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */ +.long __id_end + 0x80 - vendor /* Reverse offset to the vendor ID */ +.long __id_end + 0x80 - part /* Reverse offset to the part number */ +.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this ROM image */ .globl __id_end __id_end: Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc 2008-10-02 15:42:14 UTC (rev 3630) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc 2008-10-02 18:19:17 UTC (rev 3631) @@ -2,6 +2,7 @@ * Copyright 2004 Tyan Computer * by yhlu(a)tyan.com */ + .section ".romstrap", "a", @progbits

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2008

2007

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2005

2004

2003

2002

coreboot October 2008