coreboot October 2008

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r74 - trunk/filo/main/grub
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: oxygene Date: 2008-10-02 09:38:29 +0200 (Thu, 02 Oct 2008) New Revision: 74 Modified: trunk/filo/main/grub/builtins.c Log: Make the FILO 'color' command set a more helpful errnum rather than using the one from the integer parser. Signed-off-by: Alex Mauer <hawke(a)hawkensest.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/filo/main/grub/builtins.c =================================================================== --- trunk/filo/main/grub/builtins.c 2008-09-30 21:14:11 UTC (rev 73) +++ trunk/filo/main/grub/builtins.c 2008-10-02 07:38:29 UTC (rev 74) @@ -218,8 +218,10 @@ highlight = skip_to(0, arg); new_normal_color = color_number(normal); - if (new_normal_color < 0 && !safe_parse_maxint(&normal, &new_normal_color)) + if (new_normal_color < 0 && !safe_parse_maxint(&normal, &new_normal_color)) { + errnum = ERR_BAD_ARGUMENT; return 1; + } /* The second argument is optional, so set highlight_color to inverted NORMAL_COLOR. */ if (!*highlight) @@ -227,8 +229,10 @@ | ((new_normal_color & 0xf) << 4)); else { new_highlight_color = color_number(highlight); - if (new_highlight_color < 0 && !safe_parse_maxint(&highlight, &new_highlight_color)) + if (new_highlight_color < 0 && !safe_parse_maxint(&highlight, &new_highlight_color)) { + errnum = ERR_BAD_ARGUMENT; return 1; + } } console_setcolor(new_normal_color, new_highlight_color);

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r3629 build service
by coreboot information 02 Oct '08

02 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3629 to the coreboot source repository and caused the following changes: Change Log: Fix a typo. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:dbm690t has been fixed Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3629&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3629&device=epia-cn&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3629 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: hailfinger Date: 2008-10-02 03:35:03 +0200 (Thu, 02 Oct 2008) New Revision: 3629 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c Log: Fix a typo. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-10-02 00:52:53 UTC (rev 3628) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-10-02 01:35:03 UTC (rev 3629) @@ -45,6 +45,7 @@ static const char oem[8] = "ATI "; static const char productid[12] = "DBM690T "; struct mp_config_table *mc; + int j; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc));

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r3628 build service
by coreboot information 02 Oct '08

02 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3628 to the coreboot source repository and caused the following changes: Change Log: Use easily readable macros to setup interrupt routing. Change a few PCI bus/dev/fn to use hexadecimal numbers. Kill unused variables. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3628&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3628&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3628&device=epia-cn&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH v2] AMD DBM690T IRQ cleanup
by Carl-Daniel Hailfinger 02 Oct '08

02 Oct '08

Hi, I decided to prepare a patch for the stuff I mentioned in the DBM690T review. Use easily readable macros to setup interrupt routing. Change a few PCI bus/dev/fn to use hexadecimal numbers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c =================================================================== --- LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c (Revision 3624) +++ LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c (Arbeitskopie) @@ -122,94 +122,72 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb600, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x1, apicid_sb600, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x0, apicid_sb600, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x3, apicid_sb600, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x4, apicid_sb600, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x6, apicid_sb600, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x7, apicid_sb600, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xc, apicid_sb600, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xd, apicid_sb600, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xe, apicid_sb600, 0xe); + /* ISA ints are edge-triggered, and usually originate from the ISA bus, + * or its remainings. + */ +#define ISA_INT(intr, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin)) + + ISA_INT(0x1, 0x1); + ISA_INT(0x0, 0x2); + ISA_INT(0x3, 0x3); + ISA_INT(0x4, 0x4); + ISA_INT(0x6, 0x6); + ISA_INT(0x7, 0x7); + ISA_INT(0xc, 0xc); + ISA_INT(0xd, 0xd); + ISA_INT(0xe, 0xe); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + /* usb */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 0, apicid_sb600, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 1, apicid_sb600, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 2, apicid_sb600, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 3, apicid_sb600, 0x13); + PCI_INT(0, 0x13, 2, 0); + PCI_INT(0, 0x13, 2, 1); + PCI_INT(0, 0x13, 2, 2); + PCI_INT(0, 0x13, 2, 3); /* sata */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 18 << 2 | 0, apicid_sb600, 22); + PCI_INT(0, 0x12, 2, 0); /* HD Audio: b0:d20:f1:reg63 should be 0. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 20 << 2 | 0, apicid_sb600, 16); + PCI_INT(0, 0x14, 2, 0); /* on board NIC & Slot PCIE. */ i = 2; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19); + PCI_INT(bus_rs690[1], 0x5, 2, 0); + PCI_INT(bus_rs690[1], 0x5, 2, 1); + PCI_INT(bus_rs690[2], 0x0, 2, 0); + PCI_INT(bus_rs690[3], 0x0, 2, 0); + PCI_INT(bus_rs690[4], 0x0, 2, 0); + PCI_INT(bus_rs690[5], 0x0, 2, 0); + PCI_INT(bus_rs690[6], 0x0, 2, 0); + PCI_INT(bus_rs690[7], 0x0, 2, 0); /* PCI slots */ i += 6; j = 5; /* PCI_SLOT 0. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23); + PCI_INT(bus_sb600[1], 5, 2, 0); + PCI_INT(bus_sb600[1], 5, 2, 1); + PCI_INT(bus_sb600[1], 5, 2, 2); + PCI_INT(bus_sb600[1], 5, 2, 3); /* PCI_SLOT 1. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20); + PCI_INT(bus_sb600[1], 6, 2, 0); + PCI_INT(bus_sb600[1], 6, 2, 1); + PCI_INT(bus_sb600[1], 6, 2, 2); + PCI_INT(bus_sb600[1], 6, 2, 3); /* PCI_SLOT 2. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21); + PCI_INT(bus_sb600[1], 7, 2, 0); + PCI_INT(bus_sb600[1], 7, 2, 1); + PCI_INT(bus_sb600[1], 7, 2, 2); + PCI_INT(bus_sb600[1], 7, 2, 3); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, -- http://www.hailfinger.org/

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r3628 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: hailfinger Date: 2008-10-02 02:52:53 +0200 (Thu, 02 Oct 2008) New Revision: 3628 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c Log: Use easily readable macros to setup interrupt routing. Change a few PCI bus/dev/fn to use hexadecimal numbers. Kill unused variables. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-10-01 22:15:20 UTC (rev 3627) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-10-02 00:52:53 UTC (rev 3628) @@ -45,7 +45,6 @@ static const char oem[8] = "ATI "; static const char productid[12] = "DBM690T "; struct mp_config_table *mc; - int i, j; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -119,104 +118,77 @@ } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, - 0x0, apicid_sb600, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x1, apicid_sb600, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x0, apicid_sb600, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x3, apicid_sb600, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x4, apicid_sb600, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x6, apicid_sb600, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x7, apicid_sb600, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xc, apicid_sb600, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xd, apicid_sb600, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xe, apicid_sb600, 0xe); +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0); + /* ISA ints are edge-triggered, and usually originate from the ISA bus, + * or its remainings. + */ +#define ISA_INT(intr, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin)) + + ISA_INT(0x1, 0x1); + ISA_INT(0x0, 0x2); + ISA_INT(0x3, 0x3); + ISA_INT(0x4, 0x4); + ISA_INT(0x6, 0x6); + ISA_INT(0x7, 0x7); + ISA_INT(0xc, 0xc); + ISA_INT(0xd, 0xd); + ISA_INT(0xe, 0xe); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + /* usb */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 0, apicid_sb600, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 1, apicid_sb600, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 2, apicid_sb600, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 19 << 2 | 3, apicid_sb600, 0x13); + PCI_INT(0x0, 0x13, 0x0, 0x10); + PCI_INT(0x0, 0x13, 0x1, 0x11); + PCI_INT(0x0, 0x13, 0x2, 0x12); + PCI_INT(0x0, 0x13, 0x3, 0x13); /* sata */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 18 << 2 | 0, apicid_sb600, 22); + PCI_INT(0x0, 0x12, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0, 20 << 2 | 0, apicid_sb600, 16); + PCI_INT(0x0, 0x14, 0x0, 0x10); /* on board NIC & Slot PCIE. */ - i = 2; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19); + PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); + PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); + PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12); + PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13); + PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10); + PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11); + PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12); + PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13); /* PCI slots */ - i += 6; - j = 5; /* PCI_SLOT 0. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23); + PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20); + PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21); + PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, - 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x0, MP_APIC_ALL, 0x1); + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */

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Re: [coreboot] Some v3 Kconfig options into dts?
by Peter Stuge 02 Oct '08

02 Oct '08

Thanks for the cleanup Uwe! Reading it through I saw several options that I think should be in dts files instead. Please comment. svn(a)coreboot.org wrote: > config K8_SCAN_PCI_BUS > + Whether to scan the PCI bus in stage1. > > config K8_ALLOCATE_IO_RANGE > + Whether to allocate I/O space in stage1. > > config K8_ALLOCATE_MMIO_RANGE > + Whether to allocate MMIO space in stage1. We'll have to add some text about when any of these should be enabled too. Later. > config LOGICAL_CPUS > + How many logical CPUs there are. FIXME. > > config MAX_PHYSICAL_CPUS > + Maximum number of physical CPUs (sockets). dts? > config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED > + Config with 4 CPUs even if more are installed. But I think this should stay in Kconfig. > config CROSS_BAR_47_56 > + Configure for the type of crossbar on the mainboard. dts? > help > This option is used to determine whether the mainboard has > + a PIRQ table, which is the old way to set up interrupt routing. > It is usually set in mainboard/*/Kconfig. > > config ACPI_TABLE > boolean > help > This option is used to determine whether the mainboard has > + an ACPI table. > It is usually set in mainboard/*/Kconfig. dts? > config SMP > depends CPU_I586 || CPU_AMD_K8 > default 0 > help > + This option is used to enable certain functions to make coreboot > + work correctly on symmetric multi processor systems. > It is usually set in mainboard/*/Kconfig. Could this be derived from the number of logical CPUs? > config IOAPIC > @@ -153,7 +152,7 @@ > depends ARCH_X86 && CPU_AMD_K8 > default 0 > help > + If you want to configure an IOAPIC, set this. Will the builder really have an opinion on this? Isn't it chip dependent? (ie -> dts?) > config K8_HT_FREQ_1G_SUPPORT > + 1 GHz support. Opteron E0 or later can support 1G HT, > + but still depends on the mainboard. dts? > config HT_FREQ_800MHZ > + Can we run HT at 800 MHz. dts? > config USBDEBUG_DIRECT > depends SOUTHBRIDGE_NVIDIA_MCP55 Chip specific and board specific so a chip dts setting that is filtered through the board dts and can make a Kconfig option visible that the builder can use to disabled USB debug output? > config APIC_ID_OFFSET > + This is entirely mainboard dependent. dts? //Peter

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r3627 build service
by coreboot information 02 Oct '08

02 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3627 to the coreboot source repository and caused the following changes: Change Log: Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se. This fixes that build error. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Compilation of asus:m2v-mx_se has been fixed Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3627&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3627&device=epia-cn&vendor… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3627 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
by svn＠coreboot.org 02 Oct '08

02 Oct '08

Author: mjones Date: 2008-10-02 00:15:20 +0200 (Thu, 02 Oct 2008) New Revision: 3627 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb Log: Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se. This fixes that build error. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2008-10-01 20:16:58 UTC (rev 3626) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2008-10-01 22:15:20 UTC (rev 3627) @@ -91,6 +91,7 @@ uses SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_USE_PRINTK_IN_CAR default ROM_SIZE = 512 * 1024 default FALLBACK_SIZE = 256 * 1024 @@ -158,6 +159,7 @@ default CC = "$(CROSS_COMPILE)gcc -m32" default HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 +default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 default TTYS0_BAUD = 115200 default TTYS0_BASE = 0x3f8

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r3626 build service
by coreboot information 01 Oct '08

01 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3626 to the coreboot source repository and caused the following changes: Change Log: Add some more Super I/O IDs/names (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3626&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3626&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3626&device=epia-cn&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot October 2008