coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

[PATCH]libpayload: stub USB functions, if not compiled in
by Patrick Georgi 06 Oct '08

06 Oct '08

Hi, some people had issues with libpayload without USB features, and payloads failing to build because some functions were missing. This patch adds stubs in case USB is not selected. It's mostly a temporary measure, until there's some proper mechanism to figure out how libpayload was configured, and it probably shouldn't get into the official tree at all, but I won't decide that one. :-) Regards, Patrick

2 1

patch: print out msg level on printk
by ron minnich 06 Oct '08

06 Oct '08

This patch provides output like this: <8>dynamic PCI: 00:0b.1(PCI: 00:0b.1): enabled 1 have_resources 1 initialized 1 <7>Stage2 code done. <6>LAR: Attempting to open 'normal/payload/segment0'. <8>LAR: Start 0xfff80000 len 0x80000 <8>LAR: seen member normal/option_table@0xfff80000, size 1776 <8>LAR: seen member normal/initram/segment0@0xfff80740, size 31644 We can thus get SPEW data but then easily filter it by log level. Index: lib/console.c =================================================================== --- lib/console.c (revision 884) +++ lib/console.c (working copy) @@ -136,8 +136,14 @@ return 0; } + console_tx_byte('<', (void *)0); + console_tx_byte(msg_level + '0', (void *)0); + console_tx_byte('>', (void *)0); + + i = 3; + va_start(args, fmt); - i = vtxprintf(console_tx_byte, (void *)0, fmt, args); + i += vtxprintf(console_tx_byte, (void *)0, fmt, args); va_end(args); return i; Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> But better code is welcome. ron

4 4

r891 - coreboot-v3/mainboard/gigabyte/m57sli
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 07:19:58 +0200 (Mon, 06 Oct 2008) New Revision: 891 Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/gigabyte/m57sli/initram.c coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h coreboot-v3/mainboard/gigabyte/m57sli/stage1.c Log: Get it to build, this is as far as I want to take this board with its obsolete chip. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-10-06 05:18:22 UTC (rev 890) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-10-06 05:19:58 UTC (rev 891) @@ -25,16 +25,19 @@ $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/stage1.c \ + $(src)/northbridge/amd/k8/get_nodes.c \ + $(src)/northbridge/amd/k8/incoherent_ht_chain.c \ + $(src)/northbridge/amd/k8/libstage1.c \ $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ - $(src)/northbridge/amd/k8/coherent_ht.c \ - $(src)/northbridge/amd/k8/incoherent_ht.c \ - $(src)/northbridge/amd/k8/libstage1.c \ + $(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/k8/raminit.c \ $(src)/northbridge/amd/k8/dqs.c \ $(src)/northbridge/amd/k8/reset_test.c \ $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ + $(src)/northbridge/amd/k8/incoherent_ht.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/arch/x86/amd/model_fxx/dualcore.c \ $(src)/arch/x86/amd/model_fxx/fidvid.c \ $(src)/arch/x86/amd/model_fxx/init_cpus.c \ Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-10-06 05:18:22 UTC (rev 890) +++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-10-06 05:19:58 UTC (rev 891) @@ -30,15 +30,14 @@ #include <msr.h> #include <io.h> #include <cpu.h> +#include <globalvars.h> #include <amd/k8/k8.h> #include <southbridge/nvidia/mcp55/mcp55_smbus.h> #include <mc146818rtc.h> #include <spd.h> -# warning fix hard_reset -void hard_reset(void) -{ -} +void hard_reset(void); + void memreset_setup(void) { } @@ -58,9 +57,99 @@ */ int main(void) { - printk(BIOS_DEBUG, "Hi there from stage1\n"); - post_code(POST_START_OF_MAIN); + void enable_smbus(void); + void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); + void soft_reset_x(unsigned sbbusn, unsigned sbdn); + int cpu_init_detected(unsigned int nodeid); + void start_all_cores(void); + void set_sysinfo_in_ram(unsigned val); + int mcp55_early_setup_x(void); + void soft_reset(void); - printk(BIOS_DEBUG, "stage1 returns\n"); + struct msr msr; + static const u16 spd_addr[] = { + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, +#endif + }; + struct sys_info *sysinfo = &(global_vars()->sys_info); + + int needs_reset = 0; + unsigned bsp_apicid = 0; + int init_detected; + struct node_core_id me; + + me = get_node_core_id(); + printk(BIOS_DEBUG, "Hi there from stage1, cpu%d, core%d\n", me.nodeid, me.coreid); + + init_detected = cpu_init_detected(me.nodeid); + printk(BIOS_DEBUG, "init_detected: %d\n", init_detected); + /* well, here we are. For starters, we need to know if this is cpu0 core0. + * cpu0 core 0 will do all the DRAM setup. + */ + bsp_apicid = init_cpus(init_detected, sysinfo); + + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + setup_coherent_ht_domain(); // routing table and start other core0 + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + /* because optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_all_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", msr.hi, msr.lo); + + + enable_fid_change(); + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + init_fidvid_bsp(bsp_apicid); + + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "end msr fid, vid %08x:%08x\n", msr.hi, msr.lo); + + + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); + + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid); + + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + + memreset_setup(); + + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + printk(BIOS_DEBUG, "initram returns\n"); return 0; } + Modified: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-06 05:18:22 UTC (rev 890) +++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-06 05:19:58 UTC (rev 891) @@ -46,3 +46,6 @@ /* you don't want to set this in Kconfig or dts either. It's dangerous! */ #define CONFIG_AP_CODE_IN_CAR 0 +/* MCP55 is another fun challenge */ +#define MCP55_NUM 1 +#define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-10-06 05:18:22 UTC (rev 890) +++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-10-06 05:19:58 UTC (rev 891) @@ -295,11 +295,12 @@ }; - void hardware_stage1(void) { void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase); void enumerate_ht_chain(void); + void sio_setup(u32 devn); + void mcp55_enable_rom(void); int max; u8 tmp; @@ -325,6 +326,8 @@ setup_resource_map(register_values, max); enumerate_ht_chain(); + sio_setup(MCP55_DEVN_BASE); + mcp55_enable_rom(); printk(BIOS_ERR, "Done.\n"); post_code(POST_START_OF_MAIN);

1 0

r890 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 07:18:22 +0200 (Mon, 06 Oct 2008) New Revision: 890 Added: coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c Log: Cleanup to get to building a bios. This is as far as I want to take this awful chip. But it builds. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-10-05 04:56:29 UTC (rev 889) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-10-06 05:18:22 UTC (rev 890) @@ -28,8 +28,10 @@ #include <amd/k8/k8.h> #include "mcp55.h" -#warning fix disgusting define of MCP55_NUM it is mainboard dependent -#define MCP55_NUM 1 +#ifndef MCP55_NUM +#error MCP55_NUM should be defined in mainboard.h (in the mainboard directory) +#endif + int set_ht_link_mcp55(u8 ht_c_num) { int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); @@ -441,10 +443,10 @@ } +void set_bios_reset(void); void hard_reset(void) { -#warning what is set_bios_reset -// set_bios_reset(); + set_bios_reset(); /* full reset */ outb(0x0a, 0x0cf9); @@ -460,12 +462,31 @@ void soft_reset(void) { -#warning what is set_bios_reset -// set_bios_reset(); -#if 1 + set_bios_reset(); /* link reset */ outb(0x02, 0x0cf9); outb(0x06, 0x0cf9); -#endif } +/* this seems to be needed. The mcp55 is a real mess. I won't miss it. */ +void sio_setup(u32 devn) +{ + + unsigned value; + u32 dword; + u8 byte; + + byte = pci_conf1_read_config8(PCI_BDF(0, devn+1 , 0), 0x7b); + byte |= 0x20; + pci_conf1_write_config8(PCI_BDF(0, devn+1 , 0), 0x7b, byte); + + dword = pci_conf1_read_config32(PCI_BDF(0, devn+1 , 0), 0xa0); + dword |= (1<<0); + pci_conf1_write_config32(PCI_BDF(0, devn+1 , 0), 0xa0, dword); + + dword = pci_conf1_read_config32(PCI_BDF(0, devn+1 , 0), 0xa4); + dword |= (1<<16); + pci_conf1_write_config32(PCI_BDF(0, devn+1 , 0), 0xa4, dword); +} + + Added: coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c 2008-10-06 05:18:22 UTC (rev 890) @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <mainboard.h> +#include <types.h> +#include <lib.h> +#include <device/device.h> +#include <device/pci.h> +void mcp55_enable_rom(void) +{ + u8 byte; + u16 word; + u32 addr; + + /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ + addr = PCI_BDF(0, (MCP55_DEVN_BASE+1), 0); + + /* Set the 4MB enable bit bit */ + byte = pci_conf1_read_config8(addr, 0x88); + byte |= 0xff; //256K + pci_conf1_write_config8(addr, 0x88, byte); + byte = pci_conf1_read_config8(addr, 0x8c); + byte |= 0xff; //1M + pci_conf1_write_config8(addr, 0x8c, byte); + word = pci_conf1_read_config16(addr, 0x90); + word |= 0x7fff; //15M + pci_conf1_write_config16(addr, 0x90, word); +} Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c 2008-10-05 04:56:29 UTC (rev 889) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c 2008-10-06 05:18:22 UTC (rev 890) @@ -21,13 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This should probably be a config variable. */ -#if HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE HT_CHAIN_END_UNITID_BASE -#else - #define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE -#endif - +#include <mainboard.h> #define EHCI_BAR_INDEX 0x10 #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0x98

1 0

cmos.layout, nvramtool, options
by Uwe Hermann 06 Oct '08

06 Oct '08

Hi, please checkout http://www.coreboot.org/Nvramtool#Commonly_used_CMOS.2FNVRAM_options where I tried to document all CMOS/NVRAM options coreboot v2 currently recognizes and uses in the code, as well as options used by FILO and Etherboot. Any other payloads using NVRAM bits which I missed? The option table in the wiki may not be complete yet, and it's also missing a lot of documentation about what the options actually do, and which boards/chipsets are able to make use of them etc. Please help filling in the blanks. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

v3 parallel port console?
by Carl-Daniel Hailfinger 06 Oct '08

06 Oct '08

Hi, since the market share of machines with a serial port is shrinking rapidly and USB debug cables are not affordable at all for hobbyists, we may need to support console on parallel port. I do realize that not all machines lacking a serial port will have a parallel port, but as long as it improves our console coverage, I'm inclined to suggest parallel console support as a viable option. Parallel port console support has the advantage of being faster than serial port console, at the same time keeping the cost for a cable in the single digit dollar range. What do you think? Do we have any other devices on board which don't require interrupts to run? Floppy connector? POST cards? PC speaker (with 1-wire protocol)? Is it possible to use any of them with cheap home-built adaptors? Regards, Carl-Daniel -- http://www.hailfinger.org/

6 8

[PATCH]libpayload: weak usbdisk_* symbols
by Patrick Georgi 05 Oct '08

05 Oct '08

Hi, attached patch makes it optional for payloads to implement usbdisk_* functions if they don't need them. Regards, Patrick

1 0

r80 - trunk/filo/drivers/newusb
by svn＠coreboot.org 05 Oct '08

05 Oct '08

Author: oxygene Date: 2008-10-05 20:02:45 +0200 (Sun, 05 Oct 2008) New Revision: 80 Modified: trunk/filo/drivers/newusb/usb.c Log: Make the new USB driver work with multiple USB sticks. Also remove the attempt to work around issues with a non-USB libpayload build with USB-capable FILO. It's needs a solution, this isn't one. Modified: trunk/filo/drivers/newusb/usb.c =================================================================== --- trunk/filo/drivers/newusb/usb.c 2008-10-05 18:00:55 UTC (rev 79) +++ trunk/filo/drivers/newusb/usb.c 2008-10-05 18:02:45 UTC (rev 80) @@ -22,20 +22,32 @@ #include <usb/usbmsc.h> -static usbdev_t* devs[4]; // FIXME: only 4 devices +// FIXME: should be dynamic? +#define maxdevs 4 +static usbdev_t* devs[maxdevs]; static int count = -1; void usbdisk_create (usbdev_t* dev) { - if (count == 3) return; + if (count == maxdevs-1) return; devs[++count] = dev; } void usbdisk_remove (usbdev_t* dev) { - /* FIXME: actually remove the right device */ + int i; if (count == -1) return; - count--; + if (devs[count] == dev) { + count--; + return; + } + for (i=0; i<count; i++) { + if (devs[i] == dev) { + devs[i] = devs[count]; + count--; + return; + } + } } int usb_new_probe(int drive) @@ -46,7 +58,7 @@ must be more clever for that. */ usb_poll(); - if (count >= drive) return drive; + if (count >= drive) return 0; return -1; } @@ -56,21 +68,3 @@ int result = -readwrite_blocks(devs[drive], sector, size, cbw_direction_data_in, buffer); return result; } - -int __attribute__((weak)) usb_initialize(void) -{ - printf("NOTE: In order to use USB support, your libpayload needs USB" - " support enabled, too.\n"); - - return 0; -} - -int __attribute__((weak)) readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf) -{ - return 1; -} - -void __attribute__((weak)) usb_poll(void) -{ -} -

1 0

r79 - trunk/filo/fs
by svn＠coreboot.org 05 Oct '08

05 Oct '08

Author: oxygene Date: 2008-10-05 20:00:55 +0200 (Sun, 05 Oct 2008) New Revision: 79 Modified: trunk/filo/fs/fat.h trunk/filo/fs/fsys_fat.c Log: FAT32 didn't work because of a minor bug in the data structure (it was misaligned, to the type string field couldn't be found) Also document a sanity check that confused me all the time. Modified: trunk/filo/fs/fat.h =================================================================== --- trunk/filo/fs/fat.h 2008-10-05 18:00:00 UTC (rev 78) +++ trunk/filo/fs/fat.h 2008-10-05 18:00:55 UTC (rev 79) @@ -49,7 +49,7 @@ __u32 root_cluster; /* first cluster in root directory */ __u16 info_sector; /* filesystem info sector */ __u16 backup_boot; /* backup boot sector */ - __u16 reserved2[12]; /* Reserved */ + __u8 reserved2[12]; /* Reserved */ /* from here on it looks like the fat12/fat16 code */ __u8 drive_number; /* Physical Drive Number */ __u8 reserved; /* "current head" */ Modified: trunk/filo/fs/fsys_fat.c =================================================================== --- trunk/filo/fs/fsys_fat.c 2008-10-05 18:00:00 UTC (rev 78) +++ trunk/filo/fs/fsys_fat.c 2008-10-05 18:00:55 UTC (rev 79) @@ -110,6 +110,8 @@ if (!bpb.fat_length) { /* This is a FAT32 */ + + /* FAT32 should have 0 in this field, as its root directory can grow dynamically now */ if (FAT_CVT_U16(bpb.dir_entries)) return 0;

1 0

r78 - trunk/filo/drivers
by svn＠coreboot.org 05 Oct '08

05 Oct '08

Author: oxygene Date: 2008-10-05 20:00:00 +0200 (Sun, 05 Oct 2008) New Revision: 78 Modified: trunk/filo/drivers/ide.c Log: The braces were only added to work around a bug in the printf macro. That bug is fixed now Modified: trunk/filo/drivers/ide.c =================================================================== --- trunk/filo/drivers/ide.c 2008-10-03 19:11:48 UTC (rev 77) +++ trunk/filo/drivers/ide.c 2008-10-05 18:00:00 UTC (rev 78) @@ -809,11 +809,10 @@ cmd.sector_count = drive_info[6]; cmd.command = IDE_CMD_INITIALIZE_DRIVE_PARAMETERS; debug("Init device params... "); - if (pio_non_data(ctrl, &cmd) < 0) { + if (pio_non_data(ctrl, &cmd) < 0) debug("failed (ok for newer drives)\n"); - } else { + else debug("ok\n"); - } } printf("hd%c: %s",

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coreboot October 2008