coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

v3 stage0
by Carl-Daniel Hailfinger 06 Oct '08

06 Oct '08

Hi, currently we have 3 different files with stage0 asm code sharing lots of delicate code: - amd/stage0.S - geodelx/stage0.S - stage0_i586.S and all of them share at least the complete 16bit code which is near unreadable in itself. Can we extract the 16bit code into a common file and include it? I know that choice isn't going to be too popular because it makes the code more greppy. However, keeping all instances of that code in sync is a major headache and we even have remaining bugs in the common copied 32bit parts of that code. If that's not possible, I'd like to at least enforce a rule which keeps the common 16-bit code bit-for-bit identical including comments. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

r898 - in coreboot-v3/mainboard/amd: . serengeti
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:17:40 +0200 (Mon, 06 Oct 2008) New Revision: 898 Modified: coreboot-v3/mainboard/amd/Kconfig coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/mainboard/amd/serengeti/initram.c Log: delete commented out incorrect code in initram. Add dbm690t support to amd/Kconfig. Fix serengeti Makefile. dbe62 was tested and works i.e. this does no harm. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/amd/Kconfig =================================================================== --- coreboot-v3/mainboard/amd/Kconfig 2008-10-06 17:16:05 UTC (rev 897) +++ coreboot-v3/mainboard/amd/Kconfig 2008-10-06 17:17:40 UTC (rev 898) @@ -35,6 +35,19 @@ help AMD DB800 Geode LX development board. +config BOARD_AMD_DBM690T + bool "dbm690t" + select ARCH_X86 + select OPTION_TABLE + select CPU_AMD_K8 + select NORTHBRIDGE_AMD_K8 + select SOUTHBRIDGE_AMD_SB600 + select SOUTHBRIDGE_AMD_RS690 + select SUPERIO_ITE_IT8712F + select IOAPIC + help + AMD dbm690t development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86 @@ -67,6 +80,11 @@ config MAINBOARD_DIR string + default amd/dbm690t + depends BOARD_AMD_DBM690T + +config MAINBOARD_DIR + string default amd/norwich depends BOARD_AMD_NORWICH @@ -74,4 +92,3 @@ string default amd/serengeti depends BOARD_AMD_SERENGETI - Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-06 17:16:05 UTC (rev 897) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-06 17:17:40 UTC (rev 898) @@ -24,18 +24,19 @@ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ $(src)/arch/x86/stage1_mtrr.c \ + $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ + $(src)/northbridge/amd/k8/get_nodes.c \ + $(src)/northbridge/amd/k8/libstage1.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ $(src)/southbridge/amd/amd8111/stage1_ctrl.c \ $(src)/southbridge/amd/amd8111/stage1_enable_rom.c \ - $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ - $(src)/arch/x86/amd/model_fxx/stage1.c \ - $(src)/northbridge/amd/k8/coherent_ht.c \ - $(src)/northbridge/amd/k8/libstage1.c \ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/k8/raminit.c \ $(src)/northbridge/amd/k8/dqs.c \ $(src)/northbridge/amd/k8/reset_test.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/northbridge/amd/k8/incoherent_ht.c \ $(src)/arch/x86/pci_ops_conf1.c \ $(src)/arch/x86/stage1_mtrr.c \ Modified: coreboot-v3/mainboard/amd/serengeti/initram.c =================================================================== --- coreboot-v3/mainboard/amd/serengeti/initram.c 2008-10-06 17:16:05 UTC (rev 897) +++ coreboot-v3/mainboard/amd/serengeti/initram.c 2008-10-06 17:17:40 UTC (rev 898) @@ -249,9 +249,6 @@ dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif -#warning re-implement post_cache_as_ram - // post_cache_as_ram(); // bsp switch stack to ram and copy sysinfo ram now - printk(BIOS_DEBUG, "stage1 returns\n"); return 0; }

1 0

r897 - coreboot-v3/superio/ite/it8712f
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:16:05 +0200 (Mon, 06 Oct 2008) New Revision: 897 Modified: coreboot-v3/superio/ite/it8712f/superio.c Log: Changes to get this wrapped up and compiling. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/superio/ite/it8712f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8712f/superio.c 2008-10-06 17:15:21 UTC (rev 896) +++ coreboot-v3/superio/ite/it8712f/superio.c 2008-10-06 17:16:05 UTC (rev 897) @@ -38,7 +38,7 @@ outb(0x01, dev->path.pnp.port); outb(0x55, dev->path.pnp.port); - if (dev->dev->path.pnp.port == 0x4e) { + if (dev->path.pnp.port == 0x4e) { outb(0xaa, dev->path.pnp.port); } else { outb(0x55, dev->path.pnp.port); @@ -59,18 +59,19 @@ return; } - conf = dev->chip_info; + conf = dev->device_configuration; - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case IT8712F_FDC: /* TODO. */ break; case IT8712F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); +#warning no init_uart8250 yet +// init_uart8250(res0->base, &conf->com1); break; case IT8712F_SP2: res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); +// init_uart8250(res0->base, &conf->com2); break; case IT8712F_PP: /* TODO. */ break; @@ -79,8 +80,9 @@ case IT8712F_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - set_kbc_ps2_mode(); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); +#warning no set_kbc_ps2_mode yet +// set_kbc_ps2_mode(); +// init_pc_keyboard(res0->base, res1->base, &conf->keyboard); break; case IT8712F_KBCM: /* TODO. */ break; @@ -115,6 +117,7 @@ pnp_exit_ext_func_mode(dev); } static void it8712f_setup_scan_bus(struct device *dev); + struct device_operations it8712f_ops = { .phase2_setup_scan_bus = it8712f_setup_scan_bus, .phase4_read_resources = pnp_read_resources,

1 0

r896 - coreboot-v3/include/device
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:15:21 +0200 (Mon, 06 Oct 2008) New Revision: 896 Modified: coreboot-v3/include/device/pci_ids.h Log: Add vendor id (trivial) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/include/device/pci_ids.h =================================================================== --- coreboot-v3/include/device/pci_ids.h 2008-10-06 17:14:41 UTC (rev 895) +++ coreboot-v3/include/device/pci_ids.h 2008-10-06 17:15:21 UTC (rev 896) @@ -203,6 +203,8 @@ #define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097 #define PCI_DEVICE_ID_AMD_CS5536_B0_IDE 0x209A +#define PCI_VENDOR_ID_ATI 0x1002 + #define PCI_VENDOR_ID_CIRRUS 0x1013 #define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */

1 0

r895 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:14:41 +0200 (Mon, 06 Oct 2008) New Revision: 895 Added: coreboot-v3/northbridge/amd/k8/get_nodes.c coreboot-v3/northbridge/amd/k8/incoherent_ht_chain.c Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c Log: Changes to make a get_nodes that can be built into stage1 and (for m57sli) add incoherent ht chain support to stage1 as well. dbe62 was tested and works i.e. this does no harm. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-10-06 17:13:36 UTC (rev 894) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-10-06 17:14:41 UTC (rev 895) @@ -1689,17 +1689,6 @@ return needs_reset; } -/** - * get_nodes - * see page 46 of the BKDG Publication # 26094 Revision: 3.30 Issue Date: February 2006 - * @returns an int containing the number of nodes. - * The format of the register is 32 bits, and the node count is in bits 4-6 - */ -unsigned int get_nodes(void) -{ - return ((pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), NODEID)>>4) & 7) + 1; -} - int optimize_link_coherent_ht(void) { int needs_reset = 0; Copied: coreboot-v3/northbridge/amd/k8/get_nodes.c (from rev 875, coreboot-v3/northbridge/amd/k8/coherent_ht.c) =================================================================== --- coreboot-v3/northbridge/amd/k8/get_nodes.c (rev 0) +++ coreboot-v3/northbridge/amd/k8/get_nodes.c 2008-10-06 17:14:41 UTC (rev 895) @@ -0,0 +1,49 @@ +/* + * coherent hypertransport initialization for AMD64 + * This file is part of the coreboot project. + * + * written by Stefan Reinauer <stepan(a)openbios.org> + * (c) 2003-2004 by SuSE Linux AG + * + * (c) 2004 Tyan Computer + * 2004.12 yhlu added support to create routing table dynamically. + * it also support 8 ways too. (8 ways ladder or 8 ways crossbar) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <mainboard.h> +#include <console.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <device/hypertransport_def.h> +#include <mc146818rtc.h> +#include <lib.h> + +/** + * get_nodes + * see page 46 of the BKDG Publication # 26094 Revision: 3.30 Issue Date: February 2006 + * @returns an int containing the number of nodes. + * The format of the register is 32 bits, and the node count is in bits 4-6 + */ +unsigned int get_nodes(void) +{ + return ((pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), NODEID)>>4) & 7) + 1; +} + Copied: coreboot-v3/northbridge/amd/k8/incoherent_ht_chain.c (from rev 875, coreboot-v3/northbridge/amd/k8/incoherent_ht.c) =================================================================== --- coreboot-v3/northbridge/amd/k8/incoherent_ht_chain.c (rev 0) +++ coreboot-v3/northbridge/amd/k8/incoherent_ht_chain.c 2008-10-06 17:14:41 UTC (rev 895) @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * Copyright (C) 2004 YingHai Lu + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +/* + This should be done by Eric + 2004.12 yhlu add multi ht chain dynamically support + 2005.11 yhlu add let real sb to use small unitid +*/ +#include <mainboard.h> +#include <console.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <device/hypertransport_def.h> +#include <mc146818rtc.h> +#include <lib.h> + +int set_ht_link_buffer_count(u8 node, u8 linkn, u8 linkt, unsigned val) +{ + u32 dword; + u8 link_type; + unsigned regpos; + u32 bdf; + + /* This works on an Athlon64 because unimplemented links return 0 */ + regpos = 0x98 + (linkn * 0x20); + bdf = PCI_BDF(0,0x18+node,0); + dword = pci_conf1_read_config32(bdf, regpos); + link_type = dword & 0xff; + + if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + regpos = 0x90 + (linkn * 0x20); + dword = pci_conf1_read_config32(bdf, regpos ); + + if (dword != val) { + pci_conf1_write_config32(bdf, regpos, val); + return 1; + } + } + + return 0; +} + +int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val) +{ + int reset_needed; + u8 i; + + reset_needed = 0; + + for (i = 0; i < ht_c_num; i++) { + u32 reg; + u8 nodeid, linkn; + u8 busn; + unsigned devn; + + reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); + if((reg & 3) != 3) continue; // not enabled + + nodeid = ((reg & 0xf0)>>4); // nodeid + linkn = ((reg & 0xf00)>>8); // link n + busn = (reg & 0xff0000)>>16; //busn + + for(devn = 0; devn < 0x20; devn++) { + reg = pci_conf1_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); //1? + if ( (reg & 0xffff) == vendorid ) { + reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); + break; + } + } + } + + return reset_needed; +} +

1 0

r894 - coreboot-v3
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:13:36 +0200 (Mon, 06 Oct 2008) New Revision: 894 Modified: coreboot-v3/Kconfig Log: This is a dbm690t that compiles. Stage0 is 23K, too large. dbe62 was tested and works i.e. this does no harm. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-10-06 17:12:38 UTC (rev 893) +++ coreboot-v3/Kconfig 2008-10-06 17:13:36 UTC (rev 894) @@ -102,6 +102,10 @@ boolean config SOUTHBRIDGE_AMD_AMD8111 boolean +config SOUTHBRIDGE_AMD_SB600 + boolean +config SOUTHBRIDGE_AMD_RS690 + boolean # Super I/Os: config SUPERIO_WINBOND_W83627HF @@ -110,6 +114,8 @@ boolean config SUPERIO_ITE_IT8716F boolean +config SUPERIO_ITE_IT8712F + boolean menu "Payload"

1 0

r893 - in coreboot-v3/southbridge/amd: rs690 sb600
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:12:38 +0200 (Mon, 06 Oct 2008) New Revision: 893 Added: coreboot-v3/southbridge/amd/rs690/Makefile coreboot-v3/southbridge/amd/sb600/Makefile Modified: coreboot-v3/southbridge/amd/rs690/cmn.c coreboot-v3/southbridge/amd/rs690/gfx.c coreboot-v3/southbridge/amd/rs690/ht.c coreboot-v3/southbridge/amd/rs690/pcie.c coreboot-v3/southbridge/amd/rs690/rs690.c coreboot-v3/southbridge/amd/rs690/rs690.h coreboot-v3/southbridge/amd/rs690/stage1.c coreboot-v3/southbridge/amd/sb600/hda.c coreboot-v3/southbridge/amd/sb600/hda.dts coreboot-v3/southbridge/amd/sb600/ide.c coreboot-v3/southbridge/amd/sb600/lpc.c coreboot-v3/southbridge/amd/sb600/pci.c coreboot-v3/southbridge/amd/sb600/sata.c coreboot-v3/southbridge/amd/sb600/sb600.c coreboot-v3/southbridge/amd/sb600/sb600.h coreboot-v3/southbridge/amd/sb600/sb600_smbus.h coreboot-v3/southbridge/amd/sb600/sm.c coreboot-v3/southbridge/amd/sb600/stage1.c coreboot-v3/southbridge/amd/sb600/stage1_reset.c coreboot-v3/southbridge/amd/sb600/usb.c Log: This sb600 and rs690 support for a dbm690t that compiles. Stage0 is 23K, too large. dbe62 was tested and works i.e. this does no harm. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: coreboot-v3/southbridge/amd/rs690/Makefile =================================================================== --- coreboot-v3/southbridge/amd/rs690/Makefile (rev 0) +++ coreboot-v3/southbridge/amd/rs690/Makefile 2008-10-06 17:12:38 UTC (rev 893) @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/rs690/cmn.c \ + $(src)/southbridge/amd/rs690/gfx.c \ + $(src)/southbridge/amd/rs690/ht.c \ + $(src)/southbridge/amd/rs690/pcie.c \ + $(src)/southbridge/amd/rs690/rs690.c + +STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/rs690/stage1.c + + +endif Modified: coreboot-v3/southbridge/amd/rs690/cmn.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/cmn.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/cmn.c 2008-10-06 17:12:38 UTC (rev 893) @@ -48,9 +48,9 @@ /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c); printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.u.pci.devfn); + dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ - dev->path.u.pci.devfn << 12 | reg; + dev->path.pci.devfn << 12 | reg; return *((u32 *) addr); } @@ -61,9 +61,9 @@ /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c); printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.u.pci.devfn); + dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ - dev->path.u.pci.devfn << 12 | reg_pos; + dev->path.pci.devfn << 12 | reg_pos; reg = reg_old = *((u32 *) addr); reg &= ~mask; @@ -244,7 +244,7 @@ { u16 count = 5000; u32 lc_state, reg; - int8_t current, res = 0; + u8 current, res = 0; while (count--) { mdelay(40); @@ -304,6 +304,7 @@ */ void rs690_set_tom(struct device * nb_dev) { + extern unsigned long uma_memory_start; /* set TOM */ pci_write_config32(nb_dev, 0x90, uma_memory_start); nbmc_write_index(nb_dev, 0x1e, uma_memory_start); Modified: coreboot-v3/southbridge/amd/rs690/gfx.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-06 17:12:38 UTC (rev 893) @@ -76,7 +76,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) { unsigned short deviceid, vendorid; - struct southbridge_amd_rs690_gfx_dts_config *cfg = dev->device_configuration; + struct southbridge_amd_rs690_gfx_config *cfg = dev->device_configuration; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n", @@ -126,10 +126,10 @@ { u32 l_dword; int i; - struct device * k8_f0 = 0, k8_f2 = 0; + struct device * k8_f0 = 0, *k8_f2 = 0; struct device * nb_dev = dev_find_slot(0, 0); - printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, + printk(BIOS_INFO, "rs690_internal_gfx_enable dev=%p, nb_dev=%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ @@ -214,7 +214,7 @@ { u8 result, width; u32 reg32; - struct southbridge_amd_rs690_gfx_dts_config *cfg = nb_dev->device_configuration; + struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration; printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n"); @@ -271,8 +271,7 @@ { u8 result, width; u32 reg32; - struct southbridge_amd_rs690_config *cfg = - (struct southbridge_amd_rs690_config *)nb_dev->chip_info; + struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration; /* step 15: Training for Device 2 */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); @@ -350,8 +349,7 @@ { u32 reg32; struct device * sb_dev; - struct southbridge_amd_rs690_config *cfg = - (struct southbridge_amd_rs690_config *)nb_dev->chip_info; + struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration; /* step 5.9.1.1 */ reg32 = nbpcie_p_read_index(dev, 0xa2); @@ -395,10 +393,9 @@ void rs690_gfx_init(struct device * nb_dev, struct device * dev, u32 port) { u16 reg16; - struct southbridge_amd_rs690_config *cfg = - (struct southbridge_amd_rs690_config *)nb_dev->chip_info; + struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration; - printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", + printk(BIOS_INFO, "rs690_gfx_init, nb_dev=%p dev=%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ @@ -572,7 +569,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, .constructor = default_device_constructor, - .phase2_setup_scanbus = rs690_internal_gfx_enable, + .phase2_setup_scan_bus = rs690_internal_gfx_enable, .phase3_scan = 0, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources, Modified: coreboot-v3/southbridge/amd/rs690/ht.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-06 17:12:38 UTC (rev 893) @@ -78,11 +78,14 @@ .set_subsystem = pci_dev_set_subsystem, }; -struct device_operations rs690_gfx = { +void rs690_enable(struct device * dev); + +struct device_operations rs690_ht = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, .constructor = default_device_constructor, + .phase2_setup_scan_bus = rs690_enable, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-06 17:12:38 UTC (rev 893) @@ -51,10 +51,10 @@ 0 /* GppPwr */ }; -static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port); -static void ValidatePortEn(device_t nb_dev); +static void PciePowerOffGppPorts(struct device * nb_dev, struct device * dev, u32 port); +static void ValidatePortEn(struct device * nb_dev); -static void ValidatePortEn(device_t nb_dev) +static void ValidatePortEn(struct device * nb_dev) { } @@ -63,11 +63,11 @@ * Compliant with CIM_33's PCIEPowerOffGppPorts * Power off unused GPP lines *****************************************************************/ -static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) +static void PciePowerOffGppPorts(struct device * nb_dev, struct device * dev, u32 port) { u32 reg; u16 state_save; - struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->device_configuration; + struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration; u8 state = cfg->port_enable; if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) @@ -109,7 +109,7 @@ /* Enable pci error detecting */ u32 dword; - printk_debug("pcie_init in rs690_pcie.c\n"); + printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -121,10 +121,10 @@ /********************************************************************** **********************************************************************/ -static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) +static void switching_gpp_configurations(struct device * nb_dev, struct device * sb_dev) { u32 reg; - struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->device_configuration; + struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration; /* enables GPP reconfiguration */ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); @@ -165,9 +165,9 @@ * The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration * Space to a 256MB range within the first 4GB of addressable memory. *****************************************************************/ -void enable_pcie_bar3(device_t nb_dev) +void enable_pcie_bar3(struct device * nb_dev) { - printk_debug("enable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); @@ -181,9 +181,9 @@ * We should disable bar3 when we want to exit rs690_enable, because bar3 will be * remapped in set_resource later. *****************************************************************/ -void disable_pcie_bar3(device_t nb_dev) +void disable_pcie_bar3(struct device * nb_dev) { - printk_debug("disable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); @@ -198,13 +198,13 @@ * port: * p2p bridge number, 4-8 *****************************************/ -void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) +void rs690_gpp_sb_init(struct device * nb_dev, struct device * dev, u32 port) { u8 reg8; u16 reg16; - device_t sb_dev; - struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->device_configuration; - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); + struct device * sb_dev; + struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration; + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=%p, dev=%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, @@ -260,7 +260,7 @@ PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); - printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } @@ -331,10 +331,10 @@ /***************************************** * Compliant with CIM_33's PCIEConfigureGPPCore *****************************************/ -void config_gpp_core(device_t nb_dev, device_t sb_dev) +void config_gpp_core(struct device * nb_dev, struct device * sb_dev) { u32 reg; - struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->chip_info; + struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration; reg = nbmisc_read_index(nb_dev, 0x20); if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP) @@ -352,10 +352,9 @@ /***************************************** * Compliant with CIM_33's PCIEMiscClkProg *****************************************/ -void pcie_config_misc_clk(device_t nb_dev) +void pcie_config_misc_clk(struct device * nb_dev) { u32 reg; - struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; @@ -368,9 +367,9 @@ set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_conf1_read_config32(PCI_BDF(0, 0, 1), 0x94); reg &= ~(1 << 16); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_conf1_write_config32(PCI_BDF(0, 0, 1), 0x94, reg); } if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { @@ -380,9 +379,9 @@ set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_conf1_read_config32(PCI_BDF(0, 0, 1),0x94); reg &= ~(1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_conf1_write_config32(PCI_BDF(0, 0, 1), 0x94, reg); } reg = pci_read_config32(nb_dev, 0x4c); @@ -419,4 +418,4 @@ .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8, }; -*/ \ No newline at end of file +*/ Modified: coreboot-v3/southbridge/amd/rs690/rs690.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/rs690.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/rs690.c 2008-10-06 17:12:38 UTC (rev 893) @@ -37,8 +37,8 @@ if (!nb_dev) return nb_dev; - if ((nb_dev->vendor != PCI_VENDOR_ID_ATI) - || (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) { + if ((nb_dev->id.pci.vendor != PCI_VENDOR_ID_ATI) + || (nb_dev->id.pci.device != PCI_DEVICE_ID_ATI_RS690_HT)) { u32 id; id = pci_read_config32(nb_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) { @@ -51,38 +51,38 @@ /***************************************** * Compliant with CIM_33's ATINB_MiscClockCtrl *****************************************/ -void static rs690_config_misc_clk(struct device * nb_dev) +static void rs690_config_misc_clk(struct device * nb_dev) { u32 reg; u16 word; /* u8 byte; */ - struct bus pbus; /* fake bus for dev0 fun1 */ + u32 dev0fun1 = PCI_BDF(0,0,1); reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; pci_write_config32(nb_dev, 0x4c, reg); - word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8); + word = pci_conf1_read_config16(dev0fun1, 0xf8); word &= 0xf00; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); + pci_conf1_write_config16(dev0fun1, 0xf8, word); - word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8); + word = pci_conf1_read_config16(dev0fun1, 0xe8); word &= ~((1 << 12) | (1 << 13) | (1 << 14)); word |= 1 << 13; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word); + pci_conf1_write_config16(dev0fun1, 0xe8, word); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_conf1_read_config32(dev0fun1, 0x94); reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_conf1_write_config32(dev0fun1, 0x94, reg); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); + reg = pci_conf1_read_config32(dev0fun1, 0x8c); reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); reg |= 1 << 13; - pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); + pci_conf1_write_config32(dev0fun1, 0x8c, reg); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_conf1_read_config32(dev0fun1, 0xcc); reg |= 1 << 24; - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_conf1_write_config32(dev0fun1, 0xcc, reg); reg = nbmc_read_index(nb_dev, 0x7a); reg &= ~0x3f; @@ -91,25 +91,25 @@ set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); nbmc_write_index(nb_dev, 0x7a, reg); /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_conf1_read_config32(dev0fun1, 0xcc); reg &= ~(1 << 23); reg |= 1 << 24; - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_conf1_write_config32(dev0fun1, 0xcc, reg); #if 0 /* Powerdown reference clock to graphics core PLL in northbridge only mode */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); + reg = pci_conf1_read_config32(dev0fun1, 0x8c); reg |= 1 << 21; - pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); + pci_conf1_write_config32(dev0fun1, 0x8c, reg); /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_conf1_read_config32(dev0fun1, 0xcc); reg |= (1 << 23) | (1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_conf1_write_config32(dev0fun1, 0xcc, reg); /* Powerdown clock to memory controller in northbridge only mode */ - byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4); + byte = pci_conf1_read_config32(dev0fun1, 0xe4); byte |= 1 << 0; - pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); + pci_conf1_write_config32(dev0fun1, 0xe4, reg); /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ @@ -138,7 +138,7 @@ ***********************************************/ void rs690_enable(struct device * dev) { - struct device * nb_dev = 0, sb_dev = 0; + struct device * nb_dev = 0, *sb_dev = 0; int index = -1; u32 i; u32 devfn; @@ -152,7 +152,7 @@ /********************************************************** * Work for bus0, internal GFX located on bus1 and will return after find_nb_dev. **********************************************************/ - i = (dev->path.u.pci.devfn) & ~7; + i = (dev->path.pci.devfn) & ~7; for (devfn = 0; devfn <= i; devfn += (1 << 3)) { nb_dev = find_nb_dev(dev, devfn); if (nb_dev) @@ -170,8 +170,8 @@ for (;;) ; } - printk(BIOS_INFO, "rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3); - switch (dev->path.u.pci.devfn - devfn) { + printk(BIOS_INFO, "rs690_enable bus0, dev=0x%x\n", (dev->path.pci.devfn - devfn) >> 3); + switch (dev->path.pci.devfn - devfn) { case 0: /* bus0, dev0, fun0; */ printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ @@ -190,7 +190,7 @@ case 2 << 3: /* bus0, dev2,3, two GFX */ case 3 << 3: printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); - index = (dev->path.u.pci.devfn - devfn) >> 3; + index = (dev->path.pci.devfn - devfn) >> 3; set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index, (dev->enabled ? 0 : 1) << index); if (dev->enabled) @@ -202,7 +202,7 @@ case 7 << 3: printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); - index = (dev->path.u.pci.devfn - devfn) >> 3; + index = (dev->path.pci.devfn - devfn) >> 3; set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index, (dev->enabled ? 0 : 1) << index); if (dev->enabled) @@ -220,20 +220,3 @@ printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } } - -struct chip_operations southbridge_amd_rs690_ops = { - CHIP_NAME("ATI RS690") - .enable_dev = rs690_enable, -}; -struct device_operations rs690_sb = { - .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE}}}, - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, -}; Modified: coreboot-v3/southbridge/amd/rs690/rs690.h =================================================================== --- coreboot-v3/southbridge/amd/rs690/rs690.h 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/rs690.h 2008-10-06 17:12:38 UTC (rev 893) @@ -19,9 +19,8 @@ #ifndef __RS690_H__ #define __RS690_H__ +#include <types.h> -#include <stdint.h> - #define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2 0x7913 @@ -115,37 +114,37 @@ extern PCIE_CFG AtiPcieCfg; /* ----------------- export functions ----------------- */ -u32 nbmisc_read_index(device_t nb_dev, u32 index); -void nbmisc_write_index(device_t nb_dev, u32 index, u32 data); -u32 nbpcie_p_read_index(device_t dev, u32 index); -void nbpcie_p_write_index(device_t dev, u32 index, u32 data); -u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); -void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); -u32 htiu_read_index(device_t nb_dev, u32 index); -void htiu_write_index(device_t nb_dev, u32 index, u32 data); -u32 nbmc_read_index(device_t nb_dev, u32 index); -void nbmc_write_index(device_t nb_dev, u32 index, u32 data); +u32 nbmisc_read_index(struct device * nb_dev, u32 index); +void nbmisc_write_index(struct device * nb_dev, u32 index, u32 data); +u32 nbpcie_p_read_index(struct device * dev, u32 index); +void nbpcie_p_write_index(struct device * dev, u32 index, u32 data); +u32 nbpcie_ind_read_index(struct device * nb_dev, u32 index); +void nbpcie_ind_write_index(struct device * nb_dev, u32 index, u32 data); +u32 htiu_read_index(struct device * nb_dev, u32 index); +void htiu_write_index(struct device * nb_dev, u32 index, u32 data); +u32 nbmc_read_index(struct device * nb_dev, u32 index); +void nbmc_write_index(struct device * nb_dev, u32 index, u32 data); -u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); -void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); +u32 pci_ext_read_config32(struct device * nb_dev, struct device * dev, u32 reg); +void pci_ext_write_config32(struct device * nb_dev, struct device * dev, u32 reg, u32 mask, u32 val); -void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val); -void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val); -void rs690_set_tom(device_t nb_dev); +void set_nbcfg_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_nbcfg_enable_bits_8(struct device * nb_dev, u32 reg_pos, u8 mask, u8 val); +void set_nbmc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_htiu_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_nbmisc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_pcie_enable_bits(struct device * dev, u32 reg_pos, u32 mask, u32 val); +void rs690_set_tom(struct device * nb_dev); void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); -void enable_pcie_bar3(device_t nb_dev); -void disable_pcie_bar3(device_t nb_dev); +void enable_pcie_bar3(struct device * nb_dev); +void disable_pcie_bar3(struct device * nb_dev); -void rs690_enable(device_t dev); -void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); -void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port); -void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); -void config_gpp_core(device_t nb_dev, device_t sb_dev); -void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); -u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); +void rs690_enable(struct device * dev); +void rs690_gpp_sb_init(struct device * nb_dev, struct device * dev, u32 port); +void rs690_gfx_init(struct device * nb_dev, struct device * dev, u32 port); +void avoid_lpc_dma_deadlock(struct device * nb_dev, struct device * sb_dev); +void config_gpp_core(struct device * nb_dev, struct device * sb_dev); +void PcieReleasePortTraining(struct device * nb_dev, struct device * dev, u32 port); +u8 PcieTrainPort(struct device * nb_dev, struct device * dev, u32 port); #endif /* RS690_H */ Modified: coreboot-v3/southbridge/amd/rs690/stage1.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/stage1.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/rs690/stage1.c 2008-10-06 17:12:38 UTC (rev 893) @@ -33,112 +33,112 @@ #define NBMISC_INDEX 0x60 #define NBMC_INDEX 0xE8 -static u32 nb_read_index(u32 dev, u32 index_reg, u32 index) +static u32 nb_bdf_read_index(u32 bdf, u32 index_reg, u32 index) { - pci_conf1_write_config32(dev, index_reg, index); - return pci_conf1_read_config32(dev, index_reg + 0x4); + pci_conf1_write_config32(bdf, index_reg, index); + return pci_conf1_read_config32(bdf, index_reg + 0x4); } -static void nb_write_index(u32 dev, u32 index_reg, u32 index, u32 data) +static void nb_bdf_write_index(u32 bdf, u32 index_reg, u32 index, u32 data) { - pci_conf1_write_config32(dev, index_reg, index /* | 0x80 */ ); - pci_conf1_write_config32(dev, index_reg + 0x4, data); + pci_conf1_write_config32(bdf, index_reg, index /* | 0x80 */ ); + pci_conf1_write_config32(bdf, index_reg + 0x4, data); } -static u32 nbmisc_read_index(u32 nb_dev, u32 index) +static u32 nbmisc_bdf_read_index(u32 nb_bdf, u32 index) { - return nb_read_index((nb_dev), NBMISC_INDEX, (index)); + return nb_bdf_read_index((nb_bdf), NBMISC_INDEX, (index)); } -static void nbmisc_write_index(u32 nb_dev, u32 index, u32 data) +static void nbmisc_bdf_write_index(u32 nb_bdf, u32 index, u32 data) { - nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); + nb_bdf_write_index((nb_bdf), NBMISC_INDEX, ((index) | 0x80), (data)); } -static u32 htiu_read_index(u32 nb_dev, u32 index) +static u32 htiu_bdf_read_index(u32 nb_bdf, u32 index) { - return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); + return nb_bdf_read_index((nb_bdf), NBHTIU_INDEX, (index)); } -static void htiu_write_index(u32 nb_dev, u32 index, u32 data) +static void htiu_bdf_write_index(u32 nb_bdf, u32 index, u32 data) { - nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); + nb_bdf_write_index((nb_bdf), NBHTIU_INDEX, ((index) | 0x100), (data)); } -static u32 nbmc_read_index(u32 nb_dev, u32 index) +static u32 nbmc_bdf_read_index(u32 nb_bdf, u32 index) { - return nb_read_index((nb_dev), NBMC_INDEX, (index)); + return nb_bdf_read_index((nb_bdf), NBMC_INDEX, (index)); } -static void nbmc_write_index(u32 nb_dev, u32 index, u32 data) +static void nbmc_bdf_write_index(u32 nb_bdf, u32 index, u32 data) { - nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); + nb_bdf_write_index((nb_bdf), NBMC_INDEX, ((index) | 1 << 9), (data)); } -static void set_htiu_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask, +static void set_htiu_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; - reg = reg_old = htiu_read_index(nb_dev, reg_pos); + reg = reg_old = htiu_bdf_read_index(nb_bdf, reg_pos); reg &= ~mask; reg |= val; if (reg != reg_old) { - htiu_write_index(nb_dev, reg_pos, reg); + htiu_bdf_write_index(nb_bdf, reg_pos, reg); } } -static void set_nbmisc_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask, +static void set_nbmisc_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; - reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); + reg = reg_old = nbmisc_bdf_read_index(nb_bdf, reg_pos); reg &= ~mask; reg |= val; if (reg != reg_old) { - nbmisc_write_index(nb_dev, reg_pos, reg); + nbmisc_bdf_write_index(nb_bdf, reg_pos, reg); } } -static void set_nbcfg_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask, +static void set_nbcfg_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; - reg = reg_old = pci_conf1_read_config32(nb_dev, reg_pos); + reg = reg_old = pci_conf1_read_config32(nb_bdf, reg_pos); reg &= ~mask; reg |= val; if (reg != reg_old) { - pci_conf1_write_config32(nb_dev, reg_pos, reg); + pci_conf1_write_config32(nb_bdf, reg_pos, reg); } } -static void set_nbcfg_enable_bits_8(u32 nb_dev, u32 reg_pos, u8 mask, +static void set_nbcfg_bdf_enable_bits_8(u32 nb_bdf, u32 reg_pos, u8 mask, u8 val) { u8 reg_old, reg; - reg = reg_old = pci_conf1_read_config8(nb_dev, reg_pos); + reg = reg_old = pci_conf1_read_config8(nb_bdf, reg_pos); reg &= ~mask; reg |= val; if (reg != reg_old) { - pci_conf1_write_config8(nb_dev, reg_pos, reg); + pci_conf1_write_config8(nb_bdf, reg_pos, reg); } } -static void set_nbmc_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask, +static void set_nbmc_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; - reg = reg_old = nbmc_read_index(nb_dev, reg_pos); + reg = reg_old = nbmc_bdf_read_index(nb_bdf, reg_pos); reg &= ~mask; reg |= val; if (reg != reg_old) { - nbmc_write_index(nb_dev, reg_pos, reg); + nbmc_bdf_write_index(nb_bdf, reg_pos, reg); } } /* * Compliant with CIM_33's ATINB_PrepareInit */ -static void get_cpu_rev() +static void get_cpu_rev(void) { u32 eax, ebx, ecx, edx; __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) @@ -162,13 +162,13 @@ printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } -static u8 get_nb_rev(u32 nb_dev) +static u8 get_nb_bdf_rev(u32 nb_bdf) { u32 reg; - reg = pci_conf1_read_config32(nb_dev, 0x00); + reg = pci_conf1_read_config32(nb_bdf, 0x00); if (0x7911 == (reg >> 16)) return 7; - reg = pci_conf1_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */ + reg = pci_conf1_read_config8(nb_bdf, 0x89); /* copy from CIM, can't find in doc */ if (reg & 0x2) /* check bit1 */ return 7; if (reg & 0x1) /* check bit0 */ @@ -181,7 +181,7 @@ * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ -static void rs690_htinit() +static void rs690_htinit(void) { /* * About HT, it has been done in enumerate_ht_chain(). @@ -190,7 +190,7 @@ u32 reg; u8 k8_ht_freq; - k8_f0 = PCI_DEV(0, 0x18, 0); + k8_f0 = PCI_BDF(0, 0x18, 0); /************************ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. @@ -213,7 +213,7 @@ * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. * The processor node is addressed by its Node ID on the HT link and can be -* accessed with a device number in the PCI configuration space on Bus0. +* accessed with a bdfice number in the PCI configuration space on Bus0. * The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped * to Device 25, and so on. * The processor implements configuration registers in PCI configuration @@ -223,22 +223,22 @@ * Function2: DRAM and HT technology Trace mode configuration * Function3: Miscellaneous configuration *******************************************************/ -static void k8_optimization() +static void k8_optimization(void) { u32 k8_f0, k8_f2, k8_f3; - msr_t msr; + struct msr msr; printk(BIOS_INFO, "k8_optimization()\n"); - k8_f0 = PCI_DEV(0, 0x18, 0); - k8_f2 = PCI_DEV(0, 0x18, 2); - k8_f3 = PCI_DEV(0, 0x18, 3); + k8_f0 = PCI_BDF(0, 0x18, 0); + k8_f2 = PCI_BDF(0, 0x18, 2); + k8_f3 = PCI_BDF(0, 0x18, 3); pci_conf1_write_config32(k8_f0, 0x90, 0x01700178); /* CIM NPT_Optimization */ - set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28); - set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27, + set_nbcfg_bdf_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28); + set_nbcfg_bdf_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27, 1 << 26 | 1 << 27); - set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11); - set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); /* TODO */ + set_nbcfg_bdf_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11); + set_nbcfg_bdf_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); /* TODO */ pci_conf1_write_config32(k8_f3, 0x70, 0x51320111); /* CIM NPT_Optimization */ pci_conf1_write_config32(k8_f3, 0x74, 0x50304021); @@ -247,13 +247,13 @@ pci_conf1_write_config32(k8_f3, 0x7C, 0x0000211B); /* dual core */ else pci_conf1_write_config32(k8_f3, 0x7C, 0x0000211C); /* single core */ - set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25); + set_nbcfg_bdf_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25); - set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); - set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24); - set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10); - set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); - set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); + set_nbcfg_bdf_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); + set_nbcfg_bdf_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24); + set_nbcfg_bdf_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10); + set_nbcfg_bdf_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); + set_nbcfg_bdf_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); msr = rdmsr(0xC001001F); msr.lo &= ~(1 << 9); @@ -264,80 +264,80 @@ /***************************************** * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE *****************************************/ -static void rs690_por_pcicfg_init(u32 nb_dev) +static void rs690_por_pcicfg_init(u32 nb_bdf) { /* enable PCI Memory Access */ - set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x04, (u8)(~0xFD), 0x02); /* Set RCRB Enable */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xFF), 0x1); /* allow decode of 640k-1MB */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xEF), 0x10); /* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xFF), 0x4); /* Power Management Register Enable */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xFF), 0x80); /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation * BMMsgEn */ - set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x4C, (u8)(~0x00), 0x42 | 1); /* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation. * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */ - set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x4E, (u8)(~0xFF), 0x05); /* Reg94h[4:0] = 0x0 P drive strength offset 0 * Reg94h[6:5] = 0x2 P drive strength additive adjust */ - set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x94, (u8)(~0x80), 0x40); /* Reg94h[20:16] = 0x0 N drive strength offset 0 * Reg94h[22:21] = 0x2 N drive strength additive adjust */ - set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x96, (u8)(~0x80), 0x40); /* Reg80h[4:0] = 0x0 Termination offset * Reg80h[6:5] = 0x2 Termination additive adjust */ - set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x80, (u8)(~0x80), 0x40); /* Reg80h[14] = 0x1 Enable receiver termination control */ - set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x81, (u8)(~0xFF), 0x40); /* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on * Reg94h[14] = 0x1 Enable drive strength control */ - set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x95, (u8)(~0x3F), 0xC4); /* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */ - set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x97, (u8)(~0x1F), 0xE0); /*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, * force this BAR as mem type in rs690_gfx.c */ - set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); + set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x8D, (u8)(~0xFF), 0x03); } /***************************************** * Compliant with CIM_33's ATINB_MCIndex_POR_TABLE *****************************************/ -static void rs690_por_mc_index_init(u32 nb_dev) +static void rs690_por_mc_index_init(u32 nb_bdf) { - set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); - set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); - set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060); - set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000); - set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000); - set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E); - set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E); + set_nbmc_bdf_enable_bits(nb_bdf, 0x7A, ~0xFFFFFF80, 0x0000005F); + set_nbmc_bdf_enable_bits(nb_bdf, 0xD8, ~0x00000000, 0x00600060); + set_nbmc_bdf_enable_bits(nb_bdf, 0xD9, ~0x00000000, 0x00600060); + set_nbmc_bdf_enable_bits(nb_bdf, 0xE0, ~0x00000000, 0x00000000); + set_nbmc_bdf_enable_bits(nb_bdf, 0xE1, ~0x00000000, 0x00000000); + set_nbmc_bdf_enable_bits(nb_bdf, 0xE8, ~0x00000000, 0x003E003E); + set_nbmc_bdf_enable_bits(nb_bdf, 0xE9, ~0x00000000, 0x003E003E); } /***************************************** * Compliant with CIM_33's ATINB_MISCIND_POR_TABLE * Compliant with CIM_33's MISC_INIT_TBL *****************************************/ -static void rs690_por_misc_index_init(u32 nb_dev) +static void rs690_por_misc_index_init(u32 nb_bdf) { /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL * Block non-snoop DMA request if PMArbDis is set. * Set BMSetDis */ - set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180); - set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x0B, ~0xFFFF0000, 0x00000180); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x01, ~0xFFFFFFFF, 0x00000040); /* NBCFG (NBMISCIND 0x0): NB_CNTL - * HIDE_NB_AGP_CAP ([0], default=1)HIDE @@ -346,51 +346,51 @@ * AGPMODE30 ([4], default=0)DISABLE * AGP30ENCHANCED ([5], default=0)DISABLE * HIDE_AGP_CAP ([8], default=1)ENABLE */ - set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */ + set_nbmisc_bdf_enable_bits(nb_bdf, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */ /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing - * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); + * set_nbmisc_bdf_enable_bits(nb_bdf, 0x6A, 0ffffffffh, 000010000); * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */ - set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x6A, ~0xffffffff, 0x00020000); /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */ - set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x40, ~0xffffffff, 0x00000500); /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */ - set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x0C, ~0xffffffff, 0x00002000); /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */ - set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x1F, ~0xffffffff, 0x00000008); /* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE * Enable access to DEV8 * Enable setPower message for all ports */ - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6); - set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x00, 1 << 6, 1 << 6); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x0b, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x51, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x53, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x55, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x57, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x59, 1 << 20, 1 << 20); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x5B, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x00, 1 << 7, 1 << 7); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x07, 0x000000f0, 0x30); /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ - set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180); + set_nbmisc_bdf_enable_bits(nb_bdf, 0x0B, 0xffffffff, 0x500180); } /***************************************** * Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE *****************************************/ -static void rs690_por_htiu_index_init(u32 nb_dev) +static void rs690_por_htiu_index_init(u32 nb_bdf) { /* 0xBC: * Enables GSM mode for C1e or C3 with pop-up * Prevents AllowLdtStop from being asserted during HT link recovery * Allows FID cycles to be serviced faster. Needed for RS690 A12. No harm in RS690 A11 */ - set_htiu_enable_bits(nb_dev, 0x05, ~0xffffffff, 0x0BC); + set_htiu_bdf_enable_bits(nb_bdf, 0x05, ~0xffffffff, 0x0BC); /* 0x4203A202: * Enables writes to pass in-progress reads * Enables streaming of CPU writes @@ -400,15 +400,15 @@ * Enables decoding of C1e/C3 and FID cycles * Enables HTIU-display handshake bypass. * Enables tagging fix */ - set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x4203A202); + set_htiu_bdf_enable_bits(nb_bdf, 0x06, ~0xFFFFFFFE, 0x4203A202); /* Enables byte-write optimization for IOC requests * Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used. * Disables upstream system-management delay */ - set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x001); + set_htiu_bdf_enable_bits(nb_bdf, 0x07, ~0xFFFFFFF9, 0x001); /* HTIUNBIND 0x16 [1] = 0x1 Enable crc decoding fix */ - set_htiu_enable_bits(nb_dev, 0x16, ~0xFFFFFFFF, 0x2); + set_htiu_bdf_enable_bits(nb_bdf, 0x16, ~0xFFFFFFFF, 0x2); } /***************************************** @@ -417,29 +417,29 @@ * POR: Power On Reset * RPR: Register Programming Requirements *****************************************/ -static void rs690_por_init(u32 nb_dev) +static void rs690_por_init(u32 nb_bdf) { printk(BIOS_INFO, "rs690_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */ - rs690_por_pcicfg_init(nb_dev); + rs690_por_pcicfg_init(nb_bdf); /* ATINB_MCIND_POR_TABLE */ - rs690_por_mc_index_init(nb_dev); + rs690_por_mc_index_init(nb_bdf); /* ATINB_MISCIND_POR_TABLE */ - rs690_por_misc_index_init(nb_dev); + rs690_por_misc_index_init(nb_bdf); /* ATINB_HTIUNBIND_POR_TABLE */ - rs690_por_htiu_index_init(nb_dev); + rs690_por_htiu_index_init(nb_bdf); /* ATINB_CLKCFG_PORT_TABLE */ /* rs690 A11 SB Link full swing? */ } /* enable CFG access to Dev8, which is the SB P2P Bridge */ -static void enable_rs690_dev8() +void enable_rs690_dev8(void) { - set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); + set_nbmisc_bdf_enable_bits(PCI_BDF(0, 0, 0), 0x00, 1 << 6, 1 << 6); } @@ -447,21 +447,21 @@ /* * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). */ -void rs690_before_pci_init() +void rs690_before_pci_init(void) { } /* * The calling sequence is same as CIM. */ -void rs690_early_setup() +void rs690_stage1(void) { - u32 nb_dev = PCI_DEV(0, 0, 0); + u32 nb_bdf = PCI_BDF(0, 0, 0); printk(BIOS_INFO, "rs690_early_setup()\n"); /*ATINB_PrepareInit */ get_cpu_rev(); - switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */ + switch (get_nb_bdf_rev(nb_bdf)) { /* PCIEMiscInit */ case 5: printk(BIOS_INFO, "NB Revision is A11.\n"); break; @@ -475,5 +475,5 @@ rs690_htinit(); k8_optimization(); - rs690_por_init(nb_dev); + rs690_por_init(nb_bdf); } Added: coreboot-v3/southbridge/amd/sb600/Makefile =================================================================== --- coreboot-v3/southbridge/amd/sb600/Makefile (rev 0) +++ coreboot-v3/southbridge/amd/sb600/Makefile 2008-10-06 17:12:38 UTC (rev 893) @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/sb600/sb600.c + +STAGE2_CHIPSET_SRC += \ + $(src)/southbridge/amd/sb600/ac97.c \ + $(src)/southbridge/amd/sb600/hda.c \ + $(src)/southbridge/amd/sb600/ide.c \ + $(src)/southbridge/amd/sb600/lpc.c \ + $(src)/southbridge/amd/sb600/pci.c \ + $(src)/southbridge/amd/sb600/sata.c \ + $(src)/southbridge/amd/sb600/sm.c \ + $(src)/southbridge/amd/sb600/usb.c + +STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/sb600/stage1.c \ + $(src)/southbridge/amd/sb600/stage1_reset.c \ + $(src)/southbridge/amd/sb600/stage1_smbus.c + +endif Modified: coreboot-v3/southbridge/amd/sb600/hda.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-06 17:12:38 UTC (rev 893) @@ -24,6 +24,7 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> +#include <io.h> #include <statictree.h> #include <config.h> #include "sb600.h" @@ -149,8 +150,7 @@ static unsigned find_verb(u32 viddid, u32 ** verb) { struct device * azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); - struct southbridge_amd_sb600_dts_config *cfg = - (struct southbridge_amd_sb600_config *)azalia_dev->chip_info; + struct southbridge_amd_sb600_hda_config *cfg = azalia_dev->device_configuration; printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev)); printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid); printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid); @@ -239,7 +239,7 @@ return; base = (u8 *) ((u32)res->base); - printk(BIOS_DEBUG, "base = %08x\n", base); + printk(BIOS_DEBUG, "base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { Modified: coreboot-v3/southbridge/amd/sb600/hda.dts =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.dts 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/hda.dts 2008-10-06 17:12:38 UTC (rev 893) @@ -20,4 +20,5 @@ { device_operations = "sb600_hda"; + hda_viddid = "0"; }; Modified: coreboot-v3/southbridge/amd/sb600/ide.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-06 17:12:38 UTC (rev 893) @@ -55,7 +55,7 @@ dword |= 1 << 2; pci_write_config16(dev, 0x4, dword); -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_OPTION_ROM_RUN == 1 pci_dev_init(dev); #endif Modified: coreboot-v3/southbridge/amd/sb600/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-06 17:12:38 UTC (rev 893) @@ -109,7 +109,7 @@ struct device * child; for (child = dev->link[link].children; child; child = child->sibling) { - enable_resources(child); + dev_phase5(child); if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { for (i = 0; i < child->resources; i++) { @@ -120,8 +120,7 @@ continue; base = res->base; end = resource_end(res); - printk_debug - ("sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ @@ -213,7 +212,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, - .phase3_scan_bus = scan_status_bus, + .phase3_scan = scan_static_bus, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/pci.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-06 17:12:38 UTC (rev 893) @@ -17,11 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/device.h> +#include <types.h> +#include <lib.h> +#include <console.h> #include <device/pci.h> +#include <msr.h> +#include <legacy.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> +#include <statictree.h> +#include <config.h> #include "sb600.h" static void pci_init(struct device *dev) Modified: coreboot-v3/southbridge/amd/sb600/sata.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-06 17:12:38 UTC (rev 893) @@ -24,6 +24,7 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> +#include <io.h> #include <statictree.h> #include <config.h> #include "sb600.h" @@ -69,7 +70,7 @@ printk(BIOS_DEBUG, "sata_bar2=%x\n", sata_bar2); /* 3040 */ printk(BIOS_DEBUG, "sata_bar3=%x\n", sata_bar3); /* 3080 */ printk(BIOS_DEBUG, "sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk(BIOS_DEBUG, "sata_bar5=%x\n", sata_bar5); /* e0309000 */ + printk(BIOS_DEBUG, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; @@ -197,4 +198,4 @@ .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, .ops_pci = &lops_pci -}; \ No newline at end of file +}; Modified: coreboot-v3/southbridge/amd/sb600/sb600.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-06 17:12:38 UTC (rev 893) @@ -24,6 +24,7 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> +#include <io.h> #include <statictree.h> #include <config.h> #include "sb600.h" @@ -36,8 +37,8 @@ if (!sm_dev) return sm_dev; - if ((sm_dev->vendor != PCI_VENDOR_ID_ATI) || - ((sm_dev->device != PCI_DEVICE_ID_ATI_SB600_SM))) { + if ((sm_dev->id.pci.vendor != PCI_VENDOR_ID_ATI) || + ((sm_dev->id.pci.device != PCI_DEVICE_ID_ATI_SB600_SM))) { u32 id; id = pci_read_config32(sm_dev, PCI_VENDOR_ID); if ((id != @@ -61,42 +62,13 @@ } } -static void pmio_write_index(unsigned long port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} +void pmio_write_index(unsigned long port_base, u8 reg, u8 value); +u8 pmio_read_index(unsigned long port_base, u8 reg); +u8 pm_ioread(u8 reg); +void pm_iowrite(u8 reg, u8 value); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); -static u8 pmio_read_index(unsigned long port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - unsigned long port_base = 0xcd6; - pmio_write_index(port_base, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - unsigned long port_base = 0xcd6; - return pmio_read_index(port_base, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - unsigned long port_base = 0xcd0; - pmio_write_index(port_base, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - unsigned long port_base = 0xcd0; - return pmio_read_index(port_base, reg); -} - static void set_pmio_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val) { @@ -140,17 +112,17 @@ * 0:14.5 ACI bit 0 of pm_io 0x59 : 0 - enable, default * 0:14.6 MCI bit 1 of pm_io 0x59 : 0 - enable, default */ - if (dev->device == 0x0000) { + if (dev->id.pci.device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; vendorid &= 0xffff; } else { - vendorid = dev->vendor; - deviceid = dev->device; + vendorid = dev->id.pci.vendor; + deviceid = dev->id.pci.device; } bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) && - (bus_dev->device == PCI_DEVICE_ID_ATI_SB600_PCI)) { + if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_ATI) && + (bus_dev->id.pci.device == PCI_DEVICE_ID_ATI_SB600_PCI)) { devfn = (bus_dev->path.pci.devfn) & ~7; sm_dev = find_sm_dev(bus_dev, devfn); if (!sm_dev) @@ -233,7 +205,7 @@ struct device_operations sb600 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = xz}}}, + .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_enable_disable = sb600_enable, Modified: coreboot-v3/southbridge/amd/sb600/sb600.h =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600.h 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/sb600.h 2008-10-06 17:12:38 UTC (rev 893) @@ -35,12 +35,12 @@ #define PCI_DEVICE_ID_ATI_SB600_USB_3 0x438A #define PCI_DEVICE_ID_ATI_SB600_USB_4 0x438B -extern void pm_iowrite(u8 reg, u8 value); -extern u8 pm_ioread(u8 reg); -extern void pm2_iowrite(u8 reg, u8 value); -extern u8 pm2_ioread(u8 reg); -extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); +void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val); -void sb600_enable(device_t dev); +void sb600_enable(struct device * dev); #endif /* SB600_H */ Modified: coreboot-v3/southbridge/amd/sb600/sb600_smbus.h =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600_smbus.h 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/sb600_smbus.h 2008-10-06 17:12:38 UTC (rev 893) @@ -58,5 +58,7 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */ + /*SIZE 0x40 */ #endif Modified: coreboot-v3/southbridge/amd/sb600/sm.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-06 17:12:38 UTC (rev 893) @@ -23,10 +23,15 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> +#include <device/smbus.h> +#include <cpu.h> +#include <lapic.h> +#include <io.h> #include <statictree.h> #include <config.h> +#include <mc146818rtc.h> #include "sb600.h" -#include "sb600_smbus.c" +#include "sb600_smbus.h" #define NMI_OFF 0 @@ -86,6 +91,18 @@ /* Be careful and don't write past the end... */ }; +void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr, + unsigned int mask, unsigned int val); +void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc, + unsigned int mask, unsigned int val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_read_byte(u32 smbus_io_base, u32 device, + u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, + u32 address, u8 val); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, + u8 val); + static void setup_ioapic(unsigned long ioapic_base) { int i; @@ -108,7 +125,7 @@ l[4] = a->value_high; value_high = l[4]; if ((i == 0) && (value_low == 0xffffffff)) { - printk_warning("IO APIC not responding.\n"); + printk(BIOS_WARNING, "IO APIC not responding.\n"); return; } } @@ -382,6 +399,6 @@ .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sm_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, -}; \ No newline at end of file +}; Modified: coreboot-v3/southbridge/amd/sb600/stage1.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/stage1.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/stage1.c 2008-10-06 17:12:38 UTC (rev 893) @@ -26,17 +26,49 @@ #include <statictree.h> #include <config.h> #include <io.h> -BORKED -#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */ - /*SIZE 0x40 */ +#include <cpu.h> +#include "sb600_smbus.h" -/* Get SB ASIC Revision.*/ -static u8 get_sb600_revision() + +void pmio_write_index(unsigned long port_base, u8 reg, u8 value) { + outb(reg, port_base); + outb(value, port_base + 1); +} + +u8 pmio_read_index(unsigned long port_base, u8 reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +void pm_iowrite(u8 reg, u8 value) +{ + unsigned long port_base = 0xcd6; + pmio_write_index(port_base, reg, value); +} + +u8 pm_ioread(u8 reg) +{ + unsigned long port_base = 0xcd6; + return pmio_read_index(port_base, reg); +} + +void pm2_iowrite(u8 reg, u8 value) +{ + unsigned long port_base = 0xcd0; + pmio_write_index(port_base, reg, value); +} + +u8 pm2_ioread(u8 reg) +{ + unsigned long port_base = 0xcd0; + return pmio_read_index(port_base, reg); +}/* Get SB ASIC Revision.*/ +static u8 get_sb600_revision(void) +{ u32 dev; - pci_conf1_find_device(0x1002, 0x4385, &dev); - - if (dev == PCI_DEV_INVALID) { + if (!pci_conf1_find_device(0x1002, 0x4385, &dev)){ die("SMBUS controller not found\r\n"); } return pci_conf1_read_config8(dev, 0x08); @@ -51,7 +83,7 @@ * LPC ROM size, * NOTE: Call me ASAP, because I will reset LPC ROM size! ***************************************/ -static void sb600_lpc_init(void) +void sb600_lpc_init(void) { u8 reg8; u32 reg32; @@ -89,7 +121,7 @@ } /* what is its usage? */ -static u32 get_sbdn(u32 bus) +u32 get_sbdn(u32 bus) { u32 dev; @@ -99,7 +131,7 @@ } -static u8 dual_core() +u8 dual_core(void) { if(((cpuid_eax(0x80000000) & ~0xff) >= 8)) { if(cpuid_ecx(0x80000008) & 1) @@ -112,80 +144,72 @@ SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default. RPR 2.3.3 C-state and VID/FID change for the K8 platform. */ -static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) +void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) { u8 byte; - byte = pmio_read(0x9a); + byte = pm_ioread(0x9a); byte &= ~0x34; if(dual_core()) byte |= 0x34; else byte |= 0x04; - pmio_write(0x9a, byte); + pm_iowrite(0x9a, byte); - byte = pmio_read(0x8f); + byte = pm_ioread(0x8f); byte &= ~0x30; byte |= 0x20; - pmio_write(0x8f, byte); + pm_iowrite(0x8f, byte); - pmio_write(0x8b, 0x01); - pmio_write(0x8a, 0x90); + pm_iowrite(0x8b, 0x01); + pm_iowrite(0x8a, 0x90); if(get_sb600_revision() > 0x13) - pmio_write(0x88, 0x10); + pm_iowrite(0x88, 0x10); else - pmio_write(0x88, 0x06); + pm_iowrite(0x88, 0x06); - byte = pmio_read(0x7c); + byte = pm_ioread(0x7c); byte &= ~0x01; byte |= 0x01; - pmio_write(0x7c, byte); + pm_iowrite(0x7c, byte); /*Must be 0 for K8 platform.*/ - byte = pmio_read(0x68); + byte = pm_ioread(0x68); byte &= ~0x01; - pmio_write(0x68, byte); + pm_iowrite(0x68, byte); /*Must be 0 for K8 platform.*/ - byte = pmio_read(0x8d); + byte = pm_ioread(0x8d); byte &= ~(1<<6); - pmio_write(0x8d, byte); + pm_iowrite(0x8d, byte); - byte = pmio_read(0x61); + byte = pm_ioread(0x61); byte &= ~0x04; - pmio_write(0x61, byte); + pm_iowrite(0x61, byte); - byte = pmio_read(0x42); + byte = pm_ioread(0x42); byte &= ~0x04; - pmio_write(0x42, byte); + pm_iowrite(0x42, byte); if(get_sb600_revision() == 0x14) { - pmio_write(0x89, 0x10); + pm_iowrite(0x89, 0x10); - byte = pmio_read(0x52); + byte = pm_ioread(0x52); byte |= 0x80; - pmio_write(0x52, byte); + pm_iowrite(0x52, byte); } } +void set_bios_reset(void); -static void hard_reset(void) +void soft_reset(void) { set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); /* link reset */ outb(0x06, 0x0cf9); } -static void sb600_pci_port80() +void sb600_pci_port80(void) { u8 byte; u32 dev; @@ -220,7 +244,7 @@ pci_conf1_write_config8(dev, 0x4A, byte); } -static void sb600_lpc_port80(void) +void sb600_lpc_port80(void) { u8 byte; u32 dev; @@ -241,17 +265,19 @@ /* sbDevicesPorInitTable */ -static void sb600_devices_por_init() +static void sb600_devices_por_init(void) { + void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr, + unsigned int mask, unsigned int val); + void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc, + unsigned int mask, unsigned int val); u32 dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); - pci_conf1_find_device(0x1002, 0x4385, &dev); - - if (dev == PCI_DEV_INVALID) { + if (!pci_conf1_find_device(0x1002, 0x4385, &dev)){ die("SMBUS controller not found\r\n"); } printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", @@ -436,94 +462,94 @@ * The index address is first programmed into IO reg 0xcd6. * Read or write values are accessed through IO reg 0xcd7. */ -static void sb600_pmio_por_init() +static void sb600_pmio_por_init(void) { u8 byte; printk(BIOS_INFO, "sb600_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ - byte = pmio_read(0x66); + byte = pm_ioread(0x66); byte |= 0x20; - pmio_write(0x66, byte); + pm_iowrite(0x66, byte); /* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */ - byte = pmio_read(0x52); + byte = pm_ioread(0x52); byte &= 0xc0; byte |= 0x08; - pmio_write(0x52, byte); + pm_iowrite(0x52, byte); /* C state enable and SLP enable in C states. */ - byte = pmio_read(0x67); + byte = pm_ioread(0x67); byte |= 0x6; - pmio_write(0x67, byte); + pm_iowrite(0x67, byte); /* CIM sets 0x0e, but bit2 is for P4 system. */ - byte = pmio_read(0x68); + byte = pm_ioread(0x68); byte &= 0xf0; byte |= 0x0c; - pmio_write(0x68, byte); + pm_iowrite(0x68, byte); /* Watch Dog Timer Control * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure. * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM. */ - pmio_write(0x6c, 0xf0); - pmio_write(0x6d, 0x00); - pmio_write(0x6e, 0xc0); - pmio_write(0x6f, 0xfe); + pm_iowrite(0x6c, 0xf0); + pm_iowrite(0x6d, 0x00); + pm_iowrite(0x6e, 0xc0); + pm_iowrite(0x6f, 0xfe); /* rpr2.14: Enables HPET periodical mode */ - byte = pmio_read(0x9a); + byte = pm_ioread(0x9a); byte |= 1 << 7; - pmio_write(0x9a, byte); - byte = pmio_read(0x9f); + pm_iowrite(0x9a, byte); + byte = pm_ioread(0x9f); byte |= 1 << 5; - pmio_write(0x9f, byte); - byte = pmio_read(0x9e); + pm_iowrite(0x9f, byte); + byte = pm_ioread(0x9e); byte |= (1 << 6) | (1 << 7); - pmio_write(0x9e, byte); + pm_iowrite(0x9e, byte); /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ - byte = pmio_read(0x55); + byte = pm_ioread(0x55); byte |= 1 << 7; - pmio_write(0x55, byte); + pm_iowrite(0x55, byte); /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ - byte = pmio_read(0x52); + byte = pm_ioread(0x52); byte |= 1 << 6; - pmio_write(0x52, byte); + pm_iowrite(0x52, byte); /* rpr2.22: PLL Reset */ - byte = pmio_read(0x86); + byte = pm_ioread(0x86); byte |= 1 << 7; - pmio_write(0x86, byte); + pm_iowrite(0x86, byte); /* rpr2.3.3 */ /* This provides 16us delay before the assertion of LDTSTP# when C3 is entered. * The delay will allow USB DMA to go on in a continuous manner */ - pmio_write(0x89, 0x10); + pm_iowrite(0x89, 0x10); /* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */ - byte = pmio_read(0x52); + byte = pm_ioread(0x52); byte |= 1 << 7; - pmio_write(0x52, byte); + pm_iowrite(0x52, byte); /* rpr2.15: ASF Remote Control Action */ - byte = pmio_read(0x9f); + byte = pm_ioread(0x9f); byte |= 1 << 6; - pmio_write(0x9f, byte); + pm_iowrite(0x9f, byte); /* rpr2.19: Enabling Spread Spectrum */ - byte = pmio_read(0x42); + byte = pm_ioread(0x42); byte |= 1 << 7; - pmio_write(0x42, byte); + pm_iowrite(0x42, byte); } /* * Compliant with CIM_48's sbPciCfg. * Add any south bridge setting. */ -static void sb600_pci_cfg() +static void sb600_pci_cfg(void) { u32 dev; u8 byte; @@ -546,19 +572,19 @@ /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) * generated PCIRST#. */ - byte = pmio_read(0x65); + byte = pm_ioread(0x65); byte |= (1 << 4); - pmio_write(0x65, byte); + pm_iowrite(0x65, byte); /*For A13 and above. */ if (get_sb600_revision() > 0x12) { /* rpr2.16 C-State Reset, PMIO 0x9f[7]. */ - byte = pmio_read(0x9f); + byte = pm_ioread(0x9f); byte |= (1 << 7); - pmio_write(0x9f, byte); + pm_iowrite(0x9f, byte); /* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */ - byte = pmio_read(0x53); + byte = pm_ioread(0x53); byte |= (1 << 7); - pmio_write(0x53, byte); + pm_iowrite(0x53, byte); } /* IDE Device, BDF:0-20-1 */ @@ -612,7 +638,7 @@ /* * Compliant with CIM_48's ATSBPowerOnResetInitJSP */ -static void sb600_por_init() +static void sb600_por_init(void) { /* sbDevicesPorInitTable + sbK8PorInitTable */ sb600_devices_por_init(); @@ -625,7 +651,7 @@ * Compliant with CIM_48's AtiSbBeforePciInit * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. */ -static void sb600_before_pci_init() +void sb600_before_pci_init(void) { sb600_pci_cfg(); } @@ -633,7 +659,7 @@ /* * This function should be called after enable_sb600_smbus(). */ -static void sb600_stage1(void) +void sb600_stage1(void) { printk(BIOS_INFO, "sb600_early_setup()\n"); sb600_por_init(); Modified: coreboot-v3/southbridge/amd/sb600/stage1_reset.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/stage1_reset.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/stage1_reset.c 2008-10-06 17:12:38 UTC (rev 893) @@ -19,6 +19,7 @@ #include <types.h> #include <lib.h> +#include <io.h> #include <console.h> #include <device/pci.h> #include <msr.h> @@ -29,6 +30,7 @@ void hard_reset(void) { + void set_bios_reset(void); set_bios_reset(); /* Try rebooting through port 0xcf9 */ /* Actually it is not a real hard_reset --- it only resets coherent link table, but Modified: coreboot-v3/southbridge/amd/sb600/usb.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-06 17:11:47 UTC (rev 892) +++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-06 17:12:38 UTC (rev 893) @@ -17,14 +17,22 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/device.h> +#include <types.h> +#include <lib.h> +#include <console.h> #include <device/pci.h> +#include <msr.h> +#include <legacy.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <usbdebug_direct.h> -#include <arch/io.h> +#include <device/smbus.h> +#include <cpu.h> +#include <lapic.h> +#include <io.h> +#include <statictree.h> +#include <config.h> +#include <mc146818rtc.h> #include "sb600.h" +#include "sb600.h" static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, @@ -94,7 +102,7 @@ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%x\n", usb2_bar0); + printk(BIOS_INFO, "usb2_bar0=%x\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00;

1 0

r892 - in coreboot-v3/mainboard/amd: . dbm690t
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: rminnich Date: 2008-10-06 19:11:47 +0200 (Mon, 06 Oct 2008) New Revision: 892 Added: coreboot-v3/mainboard/amd/dbm690t/ coreboot-v3/mainboard/amd/dbm690t/Makefile coreboot-v3/mainboard/amd/dbm690t/cmos.layout coreboot-v3/mainboard/amd/dbm690t/dts coreboot-v3/mainboard/amd/dbm690t/initram.c coreboot-v3/mainboard/amd/dbm690t/mainboard.h coreboot-v3/mainboard/amd/dbm690t/resourcemap.c coreboot-v3/mainboard/amd/dbm690t/stage1.c Log: This is a dbm690t that compiles. Stage0 is 23K, too large. dbe62 was tested and works i.e. this does no harm. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: coreboot-v3/mainboard/amd/dbm690t/Makefile =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/Makefile (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/Makefile 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + +STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ + $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(src)/arch/x86/stage1_mtrr.c \ + $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ + $(src)/northbridge/amd/k8/get_nodes.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ + $(src)/northbridge/amd/k8/libstage1.c \ + +INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/k8/raminit.c \ + $(src)/northbridge/amd/k8/dqs.c \ + $(src)/northbridge/amd/k8/reset_test.c \ + $(src)/northbridge/amd/k8/incoherent_ht.c \ + $(src)/arch/x86/pci_ops_conf1.c \ + $(src)/arch/x86/stage1_mtrr.c \ + $(src)/arch/x86/amd/model_fxx/dualcore.c \ + $(src)/arch/x86/amd/model_fxx/fidvid.c \ + $(src)/arch/x86/amd/model_fxx/init_cpus.c \ + $(src)/lib/clog2.c + + +STAGE2_MAINBOARD_SRC = mainboard.c + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Added: coreboot-v3/mainboard/amd/dbm690t/cmos.layout =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/cmos.layout (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/cmos.layout 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 1007 1008 + + Added: coreboot-v3/mainboard/amd/dbm690t/dts =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/dts (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/dts 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + device_operations="dbm690t"; + mainboard_vendor = "AMD"; + mainboard_name = "Serengeti"; + cpus { }; + apic@0 { + }; + domain@0 { + /config/("northbridge/amd/k8/domain"); + pci@1,0{ + }; + /* guesses; we need a real lspci */ + pci0@18,0 { + /config/("northbridge/amd/k8/pci"); + /* make sure that the ht device is first, as it controls many other things. */ + pci0 { + /config/("southbridge/amd/rs690/ht.dts"); + }; + pci1{ + /config/("southbridge/amd/rs690/gfx.dts"); + }; + pci2{ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + pci3{ + /config/("southbridge/amd/sb600/sb600.dts"); + }; + pci4{ + /config/("southbridge/amd/sb600/hda.dts"); + }; + pci5{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci6{ + /config/("southbridge/amd/sb600/usb2.dts"); + }; + }; + pci1@18,0 { + /config/("northbridge/amd/k8/pci"); + }; + pci2@18,0 { + /config/("northbridge/amd/k8/pci"); + /* just for illustrating link #2 */ + pci@2,0{ + }; + }; + pci@18,1 {}; + pci@18,2 {}; + pci@18,3 {}; + ioport@2e { + /config/("superio/ite/it8712f/dts"); + com1enable = "1"; + }; + }; +}; Added: coreboot-v3/mainboard/amd/dbm690t/initram.c =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/initram.c (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/initram.c 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <mainboard.h> +#include <config.h> +#include <types.h> +#include <lib.h> +#include <console.h> +#include <cpu.h> +#include <globalvars.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd/k8/k8.h> +#include <mc146818rtc.h> +#include <spd.h> + +#define RC0 ((1<<0)<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +/* this code is very mainboard dependent, sadly. */ +/** + * no op at present + */ +static void memreset_setup(void) +{ +} + +/** + * this is a no op on this platform. + */ +void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/** + * read a byte from spd. + * @param device device to read from + * @param address address in the spd ROM + * @return the value of the byte at that address. + */ +u8 spd_read_byte(u16 device, u8 address) +{ + int do_smbus_read_byte(u16 device, u16 address); + return do_smbus_read_byte(device, address); +} + +/** + * main for initram for the AMD DBM690T + * @param init_detected Used to indicate that we have been started via init + * @returns 0 on success + * The purpose of this code is to not only get ram going, but get any other cpus/cores going. + * The two activities are very tightly connected and not really seperable. + * + */ +/* + * init_detected is used to determine if we did a soft reset as required by a reprogramming of the + * hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR. + * That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset. + * This value is picked up in assembly, or it should be. + */ +int main(void) +{ + /* sure, we could put this in a .h. It's called precisely once, from this one + * place. And it only relates to the initram stage. I think I'll leave it here. + * That way we can see the definition without grepping the source tree. + */ +// void do_enable_smbus(void); + void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); + void soft_reset(void); + int cpu_init_detected(unsigned int nodeid); + void rs690_stage1(void); + void sb600_stage1(void); + void rs690_before_pci_init(void); + void sb600_before_pci_init(void); + + u32 init_detected; + static const u16 spd_addr[] = { + //first node + RC0 | DIMM0, + RC0 | DIMM1, + + }; + + struct sys_info *sysinfo; + int needs_reset; + unsigned bsp_apicid = 0; + struct msr msr; + struct node_core_id me; + + me = get_node_core_id(); + printk(BIOS_DEBUG, "Hi there from stage1, cpu%d, core%d\n", me.nodeid, me.coreid); + post_code(POST_START_OF_MAIN); + sysinfo = &(global_vars()->sys_info); + init_detected = cpu_init_detected(me.nodeid); + printk(BIOS_DEBUG, "init_detected: %d\n", init_detected); + /* well, here we are. For starters, we need to know if this is cpu0 core0. + * cpu0 core 0 will do all the DRAM setup. + */ + bsp_apicid = init_cpus(init_detected, sysinfo); + +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + + setup_coherent_ht_domain(); // routing table and start other core0 + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_all_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + + /* run _early_setup before soft-reset. */ + rs690_stage1(); + sb600_stage1(); + + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", + msr.hi, msr.lo); + + enable_fid_change(); + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + init_fidvid_bsp(bsp_apicid); + + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", + msr.hi, msr.lo); + +#if 1 + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\r\n"); +// soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + soft_reset(); + } +#endif + allow_all_aps_stop(bsp_apicid); + + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + +// do_enable_smbus(); + + memreset_setup(); + + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + +#if 0 + print_pci_devices(); +#endif + +#if 0 +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); + dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); +#endif + + rs690_before_pci_init(); + sb600_before_pci_init(); + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} Added: coreboot-v3/mainboard/amd/dbm690t/mainboard.h =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/mainboard.h (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/mainboard.h 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * Constants that are mainboard-defined and do not belong in Kconfig. + * We really do not want this stuff to be visible -- it will make it appear that they can be + * changed, and they can not. + * + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DIMM_SUPPORT 0x0204 //#DDR2 and REG, S1G1 + +#define DIMM_SOCKETS 2 +#define NODE_NUMS 2 +#define CPU_SOCKET_TYPE SOCKET_S1G1 +#define MEM_TRAIN_SEQ 0 /* for now */ +#define HW_MEM_HOLE_SIZE_AUTO_INC 0 +#define HW_MEM_HOLE_SIZEK 0x100000 +#define HT_CHAIN_UNITID_BASE 0x0 +#define HT_CHAIN_END_UNITID_BASE 0x6 +#define SB_HT_CHAIN_ON_BUS0 1 +#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 0 +#define ENABLE_APIC_EXT_ID 0 +#define LIFT_BSP_APIC_ID 1 +#define K8_SET_FIDVID 1 +/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, + * so may don't need to do twice */ +#define K8_SET_FIDVID_CORE0_ONLY 1 + +/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */ +/* preferably by asking the CPU, not be a DEFINE! */ +#define CPU_ADDR_BITS 40 + +/* graphics */ +#define CONFIG_GFXUMA 1 Added: coreboot-v3/mainboard/amd/dbm690t/resourcemap.c =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/resourcemap.c (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/resourcemap.c 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Linux NetworX + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <cpu.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <arch/x86/msr.h. + +/* updated from dbm690T */ +static const struct rmap register_values[] = { + + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCM(0, 0x18, 1, 0x44, 0x0000f8f8, 0x00000000), + PCM(0, 0x18, 1, 0x4C, 0x0000f8f8, 0x00000001), + PCM(0, 0x18, 1, 0x54, 0x0000f8f8, 0x00000002), + PCM(0, 0x18, 1, 0x5C, 0x0000f8f8, 0x00000003), + PCM(0, 0x18, 1, 0x64, 0x0000f8f8, 0x00000004), + PCM(0, 0x18, 1, 0x6C, 0x0000f8f8, 0x00000005), + PCM(0, 0x18, 1, 0x74, 0x0000f8f8, 0x00000006), + PCM(0, 0x18, 1, 0x7C, 0x0000f8f8, 0x00000007), + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCM(0, 0x18, 1, 0x40, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x48, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x50, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x58, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x60, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x68, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x70, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x78, 0x0000f8fc, 0x00000000), + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCM(0, 0x18, 1, 0x84, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x8C, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x94, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x9C, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xA4, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xAC, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xB4, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xBC, 0x00000048, 0x00ffff00), + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCM(0, 0x18, 1, 0x80, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x88, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x90, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x98, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA0, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA8, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB0, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB8, 0x000000f0, 0x00fc0003), + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCM(0, 0x18, 1, 0xC4, 0xFE000FC8, 0x01fff000), + PCM(0, 0x18, 1, 0xCC, 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xD4, 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xDC, 0xFE000FC8, 0x00000000), + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCM(0, 0x18, 1, 0xC0, 0xFE000FCC, 0x00000003), + PCM(0, 0x18, 1, 0xC8, 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD0, 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD8, 0xFE000FCC, 0x00000000), + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCM(0, 0x18, 1, 0xE0, 0x0000FC88, 0x08000003), + PCM(0, 0x18, 1, 0xE4, 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xE8, 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xEC, 0x0000FC88, 0x00000000), + }; Added: coreboot-v3/mainboard/amd/dbm690t/stage1.c =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/stage1.c (rev 0) +++ coreboot-v3/mainboard/amd/dbm690t/stage1.c 2008-10-06 17:11:47 UTC (rev 892) @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <mainboard.h> +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <cpu.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <arch/x86/msr.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> + +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + void enumerate_ht_chain(void); + void sb600_pci_port80(void); + void enable_rs690_dev8(void); + void sb600_lpc_init(void); + void it8712f_enable_serial(int unused, u16 iobase); +/* + int max; + printk(BIOS_ERR, "Stage1: enable rom ...\n"); + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); + */ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + enable_rs690_dev8(); + sb600_lpc_init(); + + /* it8712f_enable_serial does not use its 1st parameter. */ + it8712f_enable_serial(0, SERIAL_IOBASE); + printk(BIOS_ERR, "Done.\n"); + post_code(POST_START_OF_MAIN); + +} + +void mainboard_pre_payload(void) +{ + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +}

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r244 - buildrom-devel/bin
by svn＠coreboot.org 06 Oct '08

06 Oct '08

Author: jcrouse Date: 2008-10-06 18:23:52 +0200 (Mon, 06 Oct 2008) New Revision: 244 Modified: buildrom-devel/bin/construct-rom.sh Log: Set executable bit on the script. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Property changes on: buildrom-devel/bin/construct-rom.sh ___________________________________________________________________ Added: svn:executable + *

1 0

Intel Menlow platform again - is anybody working on this?
by Piotr Kempa 06 Oct '08

06 Oct '08

Hello, I have been wondering if anybody picked up the work on Intel Menlow platform (Silverthorne/Atom CPU & Poulsbo chipset)? I saw some past posts from people interested but I could not find anything further, so maybe this is a dead end right now. I'm a part of a small company (called SiGarden) that is in progress of designing a MID/UMPC device and we consider using coreboot as the BIOS (booting Linux). We just need a minimal system initialization, enough only to boot Linux (Ubuntu Mobile distro). I want to estimate the effort to adapt coreboot to our system. Now since we are the system designer, it should be a bit easier for us since we know what is inside and everything. I understand we still need Intel documentation on the chipset and CPU initialization and we are in contact with them although we haven't received anything of the sort yet and I understand it is going to be a tough battle to win :) Getting back to the subject: if anybody is working on Menlow/Poulsbo then it would be best if we joined efforts instead of working separate, I think. Please let me know! Thanks, Piotr Kempa SiGarden

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coreboot October 2008