coreboot October 2008

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add support for rs690 pci devices
by ron minnich 09 Oct '08

09 Oct '08

all 8 of them ron

1 0

r911 - in coreboot-v3/southbridge/amd: rs690 sb600
by svn＠coreboot.org 09 Oct '08

09 Oct '08

Author: rminnich Date: 2008-10-09 17:11:52 +0200 (Thu, 09 Oct 2008) New Revision: 911 Removed: coreboot-v3/southbridge/amd/sb600/sb600.dts Modified: coreboot-v3/southbridge/amd/rs690/gfx.c coreboot-v3/southbridge/amd/rs690/ht.c coreboot-v3/southbridge/amd/rs690/pcie.c coreboot-v3/southbridge/amd/sb600/ac97.c coreboot-v3/southbridge/amd/sb600/hda.c coreboot-v3/southbridge/amd/sb600/ide.c coreboot-v3/southbridge/amd/sb600/lpc.c coreboot-v3/southbridge/amd/sb600/sata.c coreboot-v3/southbridge/amd/sb600/sb600.c coreboot-v3/southbridge/amd/sb600/sm.c coreboot-v3/southbridge/amd/sb600/usb.c Log: Fix the sb600 and rs690 code in the same way we just fixed the amd8111. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/amd/rs690/gfx.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-09 15:11:52 UTC (rev 911) @@ -571,6 +571,7 @@ .constructor = default_device_constructor, .phase2_setup_scan_bus = rs690_internal_gfx_enable, .phase3_scan = 0, + .phase4_enable_disable = rs690_enable, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/rs690/ht.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-09 15:11:52 UTC (rev 911) @@ -87,6 +87,7 @@ .constructor = default_device_constructor, .phase2_setup_scan_bus = rs690_enable, .phase3_scan = 0, + .phase4_enable_disable = rs690_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-09 15:11:52 UTC (rev 911) @@ -399,6 +399,7 @@ .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, + .phase4_enable_disable = rs690_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-09 15:11:52 UTC (rev 911) @@ -38,6 +38,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, .constructor = default_device_constructor, .phase3_scan = 0, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -51,6 +52,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, .constructor = default_device_constructor, .phase3_scan = 0, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/hda.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-09 15:11:52 UTC (rev 911) @@ -279,6 +279,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, .constructor = default_device_constructor, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/ide.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-09 15:11:52 UTC (rev 911) @@ -70,6 +70,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, .constructor = default_device_constructor, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-09 15:11:52 UTC (rev 911) @@ -213,6 +213,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/sata.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-09 15:11:52 UTC (rev 911) @@ -193,6 +193,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, .constructor = default_device_constructor, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/sb600.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-09 15:11:52 UTC (rev 911) @@ -201,16 +201,3 @@ deviceid); } } - -struct device_operations sb600 = { - .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase6_init = NULL, - .ops_pci = &pci_dev_ops_pci, -}; Deleted: coreboot-v3/southbridge/amd/sb600/sb600.dts =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600.dts 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sb600.dts 2008-10-09 15:11:52 UTC (rev 911) @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -{ - device_operations = "sb600"; -}; Modified: coreboot-v3/southbridge/amd/sb600/sm.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-09 15:11:52 UTC (rev 911) @@ -395,6 +395,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, .constructor = default_device_constructor, .phase3_scan = 0, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = sb600_sm_read_resources, .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/usb.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-09 15:11:52 UTC (rev 911) @@ -205,6 +205,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources,

1 0

SeaBIOS and the Geode LX framebuffer
by Stephen Crocker 09 Oct '08

09 Oct '08

Is there a way of getting VGA support with SeaBIOS on the AMD Geode LX framebuffer? I have successfully built and tested a BIOS image that appears to boot into DOS but the lack of display means that it is of little use. Is there a VGA ROM image that I can include?

6 18

r910 - in coreboot-v3: arch/x86 mainboard/amd/dbm690t mainboard/amd/serengeti southbridge/amd/amd8111
by svn＠coreboot.org 09 Oct '08

09 Oct '08

Author: rminnich Date: 2008-10-09 16:54:29 +0200 (Thu, 09 Oct 2008) New Revision: 910 Removed: coreboot-v3/southbridge/amd/amd8111/amd8111.dts Modified: coreboot-v3/arch/x86/Makefile coreboot-v3/mainboard/amd/dbm690t/Makefile coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/southbridge/amd/amd8111/amd8111.c coreboot-v3/southbridge/amd/amd8111/pci.dts coreboot-v3/southbridge/amd/amd8111/usb.c Log: This gets us to etherboot again, but this time devices are set up correctly on bus 1 --- i.e., the scan of the 8111 bridge works. It even tries to find the vga rom to run it, which we did not get before. the pci bus map built by coreboot matches simnow. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/arch/x86/Makefile 2008-10-09 14:54:29 UTC (rev 910) @@ -103,7 +103,7 @@ vsprintf.c console.c string.c $(DECOMPRESSORS) STAGE0_ARCH_X86_SRC = stage1.c serial.c \ udelay_io.c mc146818rtc.c post_code.c \ - pci_ops_conf1.c resourcemap.c + pci_ops_conf1.c # speaker.c \ ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y) Modified: coreboot-v3/mainboard/amd/dbm690t/Makefile =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/Makefile 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/mainboard/amd/dbm690t/Makefile 2008-10-09 14:54:29 UTC (rev 910) @@ -34,6 +34,7 @@ $(src)/northbridge/amd/k8/reset_test.c \ $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/northbridge/amd/k8/incoherent_ht.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/arch/x86/pci_ops_conf1.c \ $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore.c \ Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-09 14:54:29 UTC (rev 910) @@ -26,6 +26,7 @@ $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/stage1.c \ + $(src)/arch/x86/resourcemap.c \ $(src)/northbridge/amd/k8/get_nodes.c \ $(src)/northbridge/amd/k8/libstage1.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/mainboard/amd/serengeti/dts 2008-10-09 14:54:29 UTC (rev 910) @@ -32,14 +32,38 @@ pci0@18,0 { /config/("northbridge/amd/k8/pci"); pci@0,0 { - /config/("southbridge/amd/amd8111/amd8111.dts"); + /config/("southbridge/amd/amd8111/pci.dts"); + pci@1,0{ + /config/("southbridge/amd/amd8111/nic.dts"); + }; + pci@0,0{ + /config/("southbridge/amd/amd8111/usb.dts"); + }; + pci@0,1{ + /config/("southbridge/amd/amd8111/usb.dts"); + }; + pci@0,2{ + /config/("southbridge/amd/amd8111/usb2.dts"); + }; }; - pci@4,0 { + pci@7,0 { + /config/("southbridge/amd/amd8111/lpc.dts"); + }; + pci@7,1 { /config/("southbridge/amd/amd8111/ide.dts"); }; - pci@5,0 { - /config/("southbridge/amd/amd8111/nic.dts"); + pci@7,2 { + /config/("southbridge/amd/amd8111/smbus.dts"); }; + pci@7,3 { + /config/("southbridge/amd/amd8111/acpi.dts"); + }; + pci@7,5 { + /config/("southbridge/amd/amd8111/ac97audio.dts"); + }; + pci@7,6 { + /config/("southbridge/amd/amd8111/ac97modem.dts"); + }; }; pci1@18,0 { /config/("northbridge/amd/k8/pci"); Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-10-09 14:54:29 UTC (rev 910) @@ -92,15 +92,3 @@ } } -struct device_operations amd8111 = { - .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase6_init = NULL, - .ops_pci = &pci_dev_ops_pci, -}; Deleted: coreboot-v3/southbridge/amd/amd8111/amd8111.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.dts 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.dts 2008-10-09 14:54:29 UTC (rev 910) @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -{ - device_operations = "amd8111"; -}; Modified: coreboot-v3/southbridge/amd/amd8111/pci.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/pci.dts 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/southbridge/amd/amd8111/pci.dts 2008-10-09 14:54:29 UTC (rev 910) @@ -20,4 +20,5 @@ { device_operations = "amd8111_pci"; + bridge; }; Modified: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-08 16:12:32 UTC (rev 909) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-09 14:54:29 UTC (rev 910) @@ -50,6 +50,7 @@ .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, + .phase4_enable_disable = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,

1 0

[RFC] v3: keep global variables in BSP stack only
by Carl-Daniel Hailfinger 09 Oct '08

09 Oct '08

Currently v3 allocates a global variable struct on the stack for each processor in stage1_main(). We only have 1k AP stack size for Fam10, but struct global_vars is ~3.6k, so all AP stacks will smash each other. Bad. The idea is to have a special stage1_main_bsp() which allocates struct global_vars and initializes it. The BSP calls stage1_main_bsp() from stage0, all APs call stage1_main(). stage1_main_bsp() will call stage1_main(), so all processors end up in stage1_main() eventually. The following snippet illustrates the changes to arch/x86/stage1.c and the changes for an UP configuration of i586/stage0.S. Index: arch/x86/i586/stage0.S =================================================================== --- arch/x86/i586/stage0.S (Revision 909) +++ arch/x86/i586/stage0.S (Arbeitskopie) @@ -345,7 +345,7 @@ pushl $0 /* First parameter: bist */ pushl %eax - call stage1_main + call stage1_main_bsp /* We will not go back. */ fixed_mtrr_msr: Index: arch/x86/stage1.c =================================================================== --- arch/x86/stage1.c (Revision 909) +++ arch/x86/stage1.c (Arbeitskopie) @@ -143,6 +143,20 @@ return ret; } +void __attribute__((stdcall)) stage1_main(u32 bist, u32 init_detected); + +void __attribute__((stdcall)) stage1_main_bsp(u32 bist, u32 init_detected) +{ + struct global_vars globvars; + + /* Initialize global variables before we can think of using them. + */ + global_vars_init(&globvars); + globvars.init_detected = init_detected; + + stage1_main(bist, init_detected); +} + /** * This function is called from assembler code with its argument on the * stack. Force the compiler to generate always correct code for this case. @@ -156,7 +170,6 @@ */ void __attribute__((stdcall)) stage1_main(u32 bist, u32 init_detected) { - struct global_vars globvars; int ret; struct mem_file archive; void *entry; @@ -185,11 +198,6 @@ */ stop_ap(); - /* Initialize global variables before we can think of using them. - */ - global_vars_init(&globvars); - globvars.init_detected = init_detected; - hardware_stage1(); // -- http://www.hailfinger.org/

1 0

AMD64 Embedded Processors and Chipset Linux Support web page
by Marc Jones 08 Oct '08

08 Oct '08

The AMD64 Embedded Processors and Chipset Linux Support web page is open for business. http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_233… This page has links to AMD supported open source projects like coreboot and it also links to the public documents. I have updated AMD public documents coreboot wiki page with the new links. http://www.coreboot.org/AMD_Public_Documents Please let me know if you have any questions, complaints, etc. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

3 3

AMD Serengeti Cheetah devices
by Myles Watson 08 Oct '08

08 Oct '08

I'm trying to undertand dts better, and found this. This patch removes extra devices from the v2 Config.lb file for serengeti cheetah. The only change without these devices is that now these lines are missing from the log: Disabling static device: PCI: 00:19.0 Disabling static device: PCI: 00:19.1 Disabling static device: PCI: 00:19.2 Disabling static device: PCI: 00:19.3 Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 15

[PATCH] Fix v3 GeodeLX stack and global variable pointer corruption
by Carl-Daniel Hailfinger 08 Oct '08

08 Oct '08

Fix v3 GeodeLX stack and global variable pointer corruption. We had a jump instead of a call to stage1_main in geodelx/stage0.S. That means all accesses to bist and init_detected were off by 8 bytes and collided with accesses to the global variable pointer. Found during my cleanup runs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-arch_x86_cleanup/arch/x86/geodelx/stage0.S =================================================================== --- corebootv3-arch_x86_cleanup/arch/x86/geodelx/stage0.S (Revision 907) +++ corebootv3-arch_x86_cleanup/arch/x86/geodelx/stage0.S (Arbeitskopie) @@ -376,7 +376,7 @@ pushl $0 /* First parameter: bist */ pushl %eax - jmp stage1_main + call stage1_main /* We will not go back. */ /* Reset vector. */ -- http://www.hailfinger.org/

3 6

r909 - coreboot-v3/arch/x86/geodelx
by svn＠coreboot.org 08 Oct '08

08 Oct '08

Author: hailfinger Date: 2008-10-08 18:12:32 +0200 (Wed, 08 Oct 2008) New Revision: 909 Modified: coreboot-v3/arch/x86/geodelx/stage0.S Log: Fix v3 GeodeLX stack and global variable pointer corruption. We had a jump instead of a call to stage1_main in geodelx/stage0.S. That means all accesses to bist and init_detected were off by 8 bytes and collided with accesses to the global variable pointer. Found during my cleanup runs. This bug had the following effects: 1.) If gcc had decided to reload bist from stack after initializing the global variable pointer, bist would have been nonzero, an indicator for processor failure. 2.) If gcc had decided to use the stack location of bist as a scratch register (and it probably is free to do so as long as the contents are restored before returning), it would have clobbered the global variable pointer, leading to NULL pointer dereferences. 3.) Any accesses to init_detected would have resulted in accessing 4 bytes above the top of stack (0x87ffc-0x87fff), something the rest of the code deliberately avoids. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/geodelx/stage0.S =================================================================== --- coreboot-v3/arch/x86/geodelx/stage0.S 2008-10-08 16:07:29 UTC (rev 908) +++ coreboot-v3/arch/x86/geodelx/stage0.S 2008-10-08 16:12:32 UTC (rev 909) @@ -271,7 +271,7 @@ pushl $0 /* First parameter: bist */ pushl %eax - jmp stage1_main + call stage1_main /* We will not go back. */ #include "../stage0_common.S"

1 0

[PATCH] v3: factor out common stage0 code
by Carl-Daniel Hailfinger 08 Oct '08

08 Oct '08

We have lots of bit-for-bit identical code in the various stage0 implementations. Factor out the 16 bit code with associated protected mode activation. I'm open to moving even more common code out, but this is a well-defined start. If you think the stage0_common.S name is bad/evil/dumb, you're welcome to suggest an alternative. No problem from my side. This cleanup has been prepared for by r902, r905 and r907. Boot tested on qemu. Build tested on i586, geodelx, k8. The diffstat is most enlightening: amd/stage0.S | 145 --------------------------------------------- geodelx/stage0.S | 145 --------------------------------------------- i586/stage0.S | 145 --------------------------------------------- stage0_common.S | 145 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 148 insertions(+), 432 deletions(-) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-arch_x86_cleanup/arch/x86/geodelx/stage0.S =================================================================== --- corebootv3-arch_x86_cleanup/arch/x86/geodelx/stage0.S (Revision 907) +++ corebootv3-arch_x86_cleanup/arch/x86/geodelx/stage0.S (Arbeitskopie) @@ -28,112 +28,7 @@ #include <macros.h> #include <amd_geodelx.h> - .code16 - .globl _stage0 -_stage0: - cli - /* Save the BIST result. */ - movl %eax, %ebp; - - /* thanks to kmliu(a)sis.com.tw for this TLB fix */ - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. - */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB. */ - - /* Switch to protected mode. */ - - /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) - * using BFD version 2.15.94.0.2.2 20041220 this works fine without all - * the ld hackery and other things. So leave it as is with this comment. - */ - - data32 lgdt %cs:gdtptr - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST result. */ - movl %ebp, %eax - - // port80_post(0x23) - - /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 - - /* I am leaving this weird jump in here in the event that future gas - * bugs force it to be used. - */ - /* .byte 0x66 */ - .code32 - /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - - /* .code16 */ - .align 4 - .globl gdt16 -gdt16 = . - _stage0 -gdt16x: - .word gdt16xend - gdt16x -1 /* Compute the table limit. */ - .long gdt16x - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt16xend: - - /* From now on we are 32 bit. */ - .code32 - - /* We have two gdts where we could have one. That is ok. - * - * Let's not worry about this -- optimizing gdt is pointless since - * we're only in it for a little bit. - * - * Btw. note the trick below: The GDT points to ITSELF, and the first - * good descriptor is at offset 8. So you word-align the table, and - * then because you chose 8, you get a nice 64-bit aligned GDT entry, - * which is good as this is the size of the entry. - * Just in case you ever wonder why people do this. - */ - .align 4 - .globl gdtptr - .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ - -gdt: -gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - - /* selgdt 0x18, flat code segment for CAR */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x20, flat data segment for CAR */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt_end: - /* When we come here we are in protected mode. We expand the stack * and copy the data segment from ROM to the memory. * @@ -379,42 +274,4 @@ jmp stage1_main /* We will not go back. */ -/* Reset vector. */ - -/* - * RVECTOR: Size of reset vector, default is 0x10. - * RESRVED: Size of vpd code, default is 0xf0. - * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). - */ - -SEGMENT_SIZE = 0x10000 -RVECTOR = 0x00010 - -/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. - * I think we should leave it this way forever, as the bugs come and - * go -- and come again. - * - * .code16 - * .section ".rom.text" - */ -.section ".reset", "ax" - .globl _resetjump -_resetjump: - /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ - /* jmp _stage0 */ - .byte 0xe9 - .int _stage0 - ( . + 2 ) - - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 bytes are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32 bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ -.byte 0 - -/* Date? ID string? We might want to put something else in here. */ -.ascii DATE - -/* Checksum. */ -/* .word 0 */ +#include "../stage0_common.S" Index: corebootv3-arch_x86_cleanup/arch/x86/i586/stage0.S =================================================================== --- corebootv3-arch_x86_cleanup/arch/x86/i586/stage0.S (Revision 907) +++ corebootv3-arch_x86_cleanup/arch/x86/i586/stage0.S (Arbeitskopie) @@ -32,112 +32,7 @@ #define CACHE_RAM_CODE_SEG 0x18 #define CACHE_RAM_DATA_SEG 0x20 - .code16 - .globl _stage0 -_stage0: - cli - /* Save the BIST result. */ - movl %eax, %ebp; - - /* thanks to kmliu(a)sis.com.tw for this TLB fix */ - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. - */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB. */ - - /* Switch to protected mode. */ - - /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) - * using BFD version 2.15.94.0.2.2 20041220 this works fine without all - * the ld hackery and other things. So leave it as is with this comment. - */ - - data32 lgdt %cs:gdtptr - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST result. */ - movl %ebp, %eax - - // port80_post(0x23) - - /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 - - /* I am leaving this weird jump in here in the event that future gas - * bugs force it to be used. - */ - /* .byte 0x66 */ - .code32 - /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - - /* .code16 */ - .align 4 - .globl gdt16 -gdt16 = . - _stage0 -gdt16x: - .word gdt16xend - gdt16x -1 /* Compute the table limit. */ - .long gdt16x - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt16xend: - - /* From now on we are 32 bit. */ - .code32 - - /* We have two gdts where we could have one. That is ok. - * - * Let's not worry about this -- optimizing gdt is pointless since - * we're only in it for a little bit. - * - * Btw. note the trick below: The GDT points to ITSELF, and the first - * good descriptor is at offset 8. So you word-align the table, and - * then because you chose 8, you get a nice 64-bit aligned GDT entry, - * which is good as this is the size of the entry. - * Just in case you ever wonder why people do this. - */ - .align 4 - .globl gdtptr - .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ - -gdt: -gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - - /* selgdt 0x18, flat code segment for CAR */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x20, flat data segment for CAR */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt_end: - /* When we come here we are in protected mode. We expand the stack * and copy the data segment from ROM to the memory. * @@ -465,42 +360,4 @@ .long 0x20C, 0x20D, 0x20E, 0x20F .long 0x000 /* NULL, end of table */ -/* Reset vector. */ - -/* - * RVECTOR: Size of reset vector, default is 0x10. - * RESRVED: Size of vpd code, default is 0xf0. - * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). - */ - -SEGMENT_SIZE = 0x10000 -RVECTOR = 0x00010 - -/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. - * I think we should leave it this way forever, as the bugs come and - * go -- and come again. - * - * .code16 - * .section ".rom.text" - */ -.section ".reset", "ax" - .globl _resetjump -_resetjump: - /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ - /* jmp _stage0 */ - .byte 0xe9 - .int _stage0 - ( . + 2 ) - - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 bytes are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32 bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ -.byte 0 - -/* Date? ID string? We might want to put something else in here. */ -.ascii DATE - -/* Checksum. */ -/* .word 0 */ +#include "../stage0_common.S" Index: corebootv3-arch_x86_cleanup/arch/x86/stage0_common.S =================================================================== --- corebootv3-arch_x86_cleanup/arch/x86/stage0_common.S (Revision 0) +++ corebootv3-arch_x86_cleanup/arch/x86/stage0_common.S (Revision 0) @@ -0,0 +1,145 @@ + .code16 + .globl _stage0 +_stage0: + cli + + /* Save the BIST result. */ + movl %eax, %ebp; + + /* thanks to kmliu(a)sis.com.tw for this TLB fix */ + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before + * executing any further code. Even though paging is disabled we + * could still get false address translations due to the TLB if we + * didn't invalidate it. + */ + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB. */ + + /* Switch to protected mode. */ + + /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) + * using BFD version 2.15.94.0.2.2 20041220 this works fine without all + * the ld hackery and other things. So leave it as is with this comment. + */ + + data32 lgdt %cs:gdtptr + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + /* Restore BIST result. */ + movl %ebp, %eax + + // port80_post(0x23) + + /* Now we are in protected mode. Jump to a 32 bit code segment. */ + data32 ljmp $ROM_CODE_SEG, $protected_stage0 + + /* I am leaving this weird jump in here in the event that future gas + * bugs force it to be used. + */ + /* .byte 0x66 */ + .code32 + /* ljmp $ROM_CODE_SEG, $protected_stage0 */ + + /* .code16 */ + .align 4 + .globl gdt16 +gdt16 = . - _stage0 +gdt16x: + .word gdt16xend - gdt16x -1 /* Compute the table limit. */ + .long gdt16x + .word 0 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 +gdt16xend: + + /* From now on we are 32 bit. */ + .code32 + + /* We have two gdts where we could have one. That is ok. + * + * Let's not worry about this -- optimizing gdt is pointless since + * we're only in it for a little bit. + * + * Btw. note the trick below: The GDT points to ITSELF, and the first + * good descriptor is at offset 8. So you word-align the table, and + * then because you chose 8, you get a nice 64-bit aligned GDT entry, + * which is good as this is the size of the entry. + * Just in case you ever wonder why people do this. + */ + .align 4 + .globl gdtptr + .globl gdt_limit +gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ + +gdt: +gdtptr: + .word gdt_end - gdt -1 /* Compute the table limit. */ + .long gdt /* We know the offset. */ + .word 0 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + + /* selgdt 0x18, flat code segment for CAR */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x20, flat data segment for CAR */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 +gdt_end: + +/* Reset vector. */ + +/* + * RVECTOR: Size of reset vector, default is 0x10. + * RESRVED: Size of vpd code, default is 0xf0. + * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). + */ + +SEGMENT_SIZE = 0x10000 +RVECTOR = 0x00010 + +/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. + * I think we should leave it this way forever, as the bugs come and + * go -- and come again. + * + * .code16 + * .section ".rom.text" + */ +.section ".reset", "ax" + .globl _resetjump +_resetjump: + /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ + /* jmp _stage0 */ + .byte 0xe9 + .int _stage0 - ( . + 2 ) + + /* Note: The above jump is hand coded to work around bugs in binutils. + * 5 bytes are used for a 3 byte instruction. This works because x86 + * is little endian and allows us to use supported 32 bit relocations + * instead of the weird 16 bit relocations that binutils does not + * handle consistenly between versions because they are used so rarely. + */ +.byte 0 + +/* Date? ID string? We might want to put something else in here. */ +.ascii DATE + +/* Checksum. */ +/* .word 0 */ Index: corebootv3-arch_x86_cleanup/arch/x86/amd/stage0.S =================================================================== --- corebootv3-arch_x86_cleanup/arch/x86/amd/stage0.S (Revision 907) +++ corebootv3-arch_x86_cleanup/arch/x86/amd/stage0.S (Arbeitskopie) @@ -38,112 +38,7 @@ #define CacheSizeAPStack 0x400 /* 1K */ #endif - .code16 - .globl _stage0 -_stage0: - cli - /* Save the BIST result. */ - movl %eax, %ebp; - - /* thanks to kmliu(a)sis.com.tw for this TLB fix */ - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. - */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB. */ - - /* Switch to protected mode. */ - - /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) - * using BFD version 2.15.94.0.2.2 20041220 this works fine without all - * the ld hackery and other things. So leave it as is with this comment. - */ - - data32 lgdt %cs:gdtptr - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST result. */ - movl %ebp, %eax - - // port80_post(0x23) - - /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 - - /* I am leaving this weird jump in here in the event that future gas - * bugs force it to be used. - */ - /* .byte 0x66 */ - .code32 - /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - - /* .code16 */ - .align 4 - .globl gdt16 -gdt16 = . - _stage0 -gdt16x: - .word gdt16xend - gdt16x -1 /* Compute the table limit. */ - .long gdt16x - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt16xend: - - /* From now on we are 32 bit. */ - .code32 - - /* We have two gdts where we could have one. That is ok. - * - * Let's not worry about this -- optimizing gdt is pointless since - * we're only in it for a little bit. - * - * Btw. note the trick below: The GDT points to ITSELF, and the first - * good descriptor is at offset 8. So you word-align the table, and - * then because you chose 8, you get a nice 64-bit aligned GDT entry, - * which is good as this is the size of the entry. - * Just in case you ever wonder why people do this. - */ - .align 4 - .globl gdtptr - .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ - -gdt: -gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - - /* selgdt 0x18, flat code segment for CAR */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x20, flat data segment for CAR */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt_end: - /* When we come here we are in protected mode. We expand the stack * and copy the data segment from ROM to the memory. * @@ -468,42 +363,4 @@ .long 0xC001001A, 0xC001001D .long 0x000 /* NULL, end of table */ -/* Reset vector. */ - -/* - * RVECTOR: Size of reset vector, default is 0x10. - * RESRVED: Size of vpd code, default is 0xf0. - * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). - */ - -SEGMENT_SIZE = 0x10000 -RVECTOR = 0x00010 - -/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. - * I think we should leave it this way forever, as the bugs come and - * go -- and come again. - * - * .code16 - * .section ".rom.text" - */ -.section ".reset", "ax" - .globl _resetjump -_resetjump: - /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ - /* jmp _stage0 */ - .byte 0xe9 - .int _stage0 - ( . + 2 ) - - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 bytes are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32 bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ -.byte 0 - -/* Date? ID string? We might want to put something else in here. */ -.ascii DATE - -/* Checksum. */ -/* .word 0 */ +#include "../stage0_common.S" -- http://www.hailfinger.org/

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coreboot October 2008