coreboot January 2008

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[LinuxBIOS] r3032 - trunk/util/flashrom
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: hailfinger Date: 2008-01-04 17:22:09 +0100 (Fri, 04 Jan 2008) New Revision: 3032 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: Print at least the vendor for SPI flash chips if the exact chip ID is unknown. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2007-12-31 14:05:08 UTC (rev 3031) +++ trunk/util/flashrom/flash.h 2008-01-04 16:22:09 UTC (rev 3032) @@ -59,10 +59,13 @@ * entry of each section should be the manufacturer ID, followed by the * list of devices from that manufacturer (sorted by device IDs). * - * All LPC/FWH parts (parallel flash) have 8-bit device IDs. + * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no + * continuation code. * All SPI parts have 16-bit device IDs. */ +#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ + #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2007-12-31 14:05:08 UTC (rev 3031) +++ trunk/util/flashrom/flashchips.c 2008-01-04 16:22:09 UTC (rev 3032) @@ -185,5 +185,13 @@ probe_jedec, erase_chip_jedec, write_49f002}, {"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, + {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, + {"SST unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, + {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, {NULL,} }; Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2007-12-31 14:05:08 UTC (rev 3031) +++ trunk/util/flashrom/spi.c 2008-01-04 16:22:09 UTC (rev 3032) @@ -262,14 +262,19 @@ manuf_id = readarr[0]; model_id = (readarr[1] << 8) | readarr[2]; printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); - if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { - /* Print the status register before erase to tell the + if (manuf_id == flash->manufacture_id && + model_id == flash->model_id) { + /* Print the status register to tell the * user about possible write protection. */ generic_spi_prettyprint_status_register(flash); return 1; } + /* Test if this is a pure vendor match. */ + if (manuf_id == flash->manufacture_id && + GENERIC_DEVICE_ID == flash->model_id) + return 1; } return 0;

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[LinuxBIOS] [Patch] Fix CONFIG_CONSOLE_VGA handling in default pci_dev_init.
by Luc Verhaegen 04 Jan '08

04 Jan '08

The CONFIG_CONSOLE_VGA and CONFIG_PCI_ROM_RUN logic in src/devices/pci_device.c:pci_dev_init is messed up. First of all, pci_dev_init should only do anything when the pci rom should be run. Secondly, vga_inited should only be set when the rom has been run, and never otherwise as this should be done by the relevant init function of possible (future) VGA setup drivers. Signed-off-by: Luc Verhaegen <libv(a)skynet.be>

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[LinuxBIOS] patch: move defines from a .S to a .h
by ron minnich 04 Jan '08

04 Jan '08

This is so we can attempt to return from disable_car: we need these definitions in C. Besides, they make more sense in a .h I think. ron

2 1

[LinuxBIOS] r543 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: hailfinger Date: 2008-01-04 13:53:09 +0100 (Fri, 04 Jan 2008) New Revision: 543 Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: Move AMD Geode LX defines for CAR from a .S to a .h so they are available to C. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/stage0.S 2007-12-11 01:24:52 UTC (rev 542) +++ LinuxBIOSv3/arch/x86/geodelx/stage0.S 2008-01-04 12:53:09 UTC (rev 543) @@ -28,24 +28,6 @@ #include "../macros.h" #include <amd_geodelx.h> -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) - -#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ -#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) -#define CR0_CD 0x40000000 /* Bit 30 = Cache Disable */ -#define CR0_NW 0x20000000 /* Bit 29 = Not Write Through */ - -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 - -#define CACHE_RAM_CODE_SEG 0x18 -#define CACHE_RAM_DATA_SEG 0x20 - .code16 .globl _stage0 _stage0: Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h =================================================================== --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-12-11 01:24:52 UTC (rev 542) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 12:53:09 UTC (rev 543) @@ -567,7 +567,24 @@ /* ------------------------ */ #define DCACHE_RAM_SIZE 0x08000 #define DCACHE_RAM_BASE 0xc8000 +/* This is where the DCache will be mapped and be used as stack. It would be + * cool if it was the same base as LinuxBIOS normal stack. + */ +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) +#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ +#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ +#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* Bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* Bit 29 = Not Write Through */ + +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + /* POST CODES */ /* standard AMD post definitions -- might as well use them. */

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[LinuxBIOS] another try at the lib/console patch in v3
by ron minnich 04 Jan '08

04 Jan '08

I have changed banner so it makes a uniform width message. It is now more complex. ron

1 0

[LinuxBIOS] april meeting in denver
by ron minnich 04 Jan '08

04 Jan '08

I've got some questions from people pending re: the meeting in Denver. Most of the US of A seems to still be on vacation, I am not getting answers from the organizers about the denver meeting. I hope to have more info next week. thanks ron

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[LinuxBIOS] RESEND: v3 patch for console functions, and mods to lib/lar.c to support a void * parameter for running functions.
by ron minnich 04 Jan '08

04 Jan '08

attached. I need an ack, we have discussed these already. ron

3 9

Re: [LinuxBIOS] VGA help under QEMU
by Myles Watson 03 Jan '08

03 Jan '08

On Jan 3, 2008 12:51 PM, Myles Watson <mylesgw(a)gmail.com> wrote: > > On Jan 3, 2008 10:24 AM, ron minnich <rminnich(a)gmail.com> wrote: > > attached are: > > output from boot > > bios > > .config > > all .bin files qemu might have used. > > > > I ran this with: > > qemu -serial stdio -L . -kernel linux-2.6.15-bochs/vmlinux -hdc hda > > -hda hda | tee out > > > > thanks > > ron > > > > Thanks. The difference is indeed the vga bios. The one I have > attached is the latest one distributed with qemu. It works with v2, > but not v3. Yours works with v2 and v3. > > The obvious work-around for me is to use your vga bios, but it's a > pain to keep the old one around for everyone. > > I tried changing the emulator, but it didn't make a difference whether > I used x86emu or vm86. > > Do you have any suggestions? > > Myles > It turns out that LinuxBIOSv3 doesn't play well with the new vgabios-cirrus.bin from qemu. I've attached both versions so that people can play with them. LinuxBIOSv2 works with either one. Myles

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[LinuxBIOS] Kino LX800 AMD Geode based board
by markw 03 Jan '08

03 Jan '08

Ok, talking to guys on IRC and they said to post up here. I've been challenged to see if I can come up with a system that boots in sub 10 seconds to a command prompt with networking. I'm sitting on a few Kino LX800 boards that we use for other projects, but I'm willing to sacrifice one for this. The board has sata onboard using an ALI M5281 controller. It also uses the geode CS5536 ide controller, so the sata stuff may not be an issue. >From reading/talking to people, this board should be minimal prompt at around 7 seconds. I've got access to device programmers and 2m repair stuff, so flashing isn't a huge issue. Would this be a good board for a proof of concept, or should I look at something else. The board is a Kino LX800, AMD GEODE 500mhz, sata/pata, onboard amd video, onboard realtek 8139 ethernet. I'd like to to LB and kernel in flash, but if the hardware won't suppor a 16mbit flash, then I'll do lb/filo and boot from CF over the standard ide channel. The board currently has a 49fl004 socketed flash. Plan on using a stripped down debian install, since that's the only one I can reliably shrink. Thanks, Mark Here's all the specs: http://tinyurl.com/3ajv9l Here's the output of lspci. 00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31) 00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block 00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) 00:10.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:11.0 Mass storage controller: ALi Corporation ALi M5281 Serial ATA / RAID Host Controller (rev a4) 00:11.1 Mass storage controller: ALi Corporation M5228 ALi ATA/RAID Controller (rev c6) 00:12.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) Here's the more verbose lspci output recommend by the guys on irc. 00:01.0 0600: 1022:2080 (rev 31) Subsystem: 1022:2080 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 248, Cache Line Size: 32 bytes Region 0: I/O ports at ac1c [size=4] Region 1: I/O ports at 9e00 [size=8] 00: 22 10 80 20 05 00 20 02 31 00 00 06 08 f8 80 00 10: 1d ac 00 00 01 9e 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 0300: 1022:2081 Subsystem: 1022:2081 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at ee000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at efff4000 (32-bit, non-prefetchable) [size=16K] Region 2: Memory at efff0000 (32-bit, non-prefetchable) [size=16K] Region 3: Memory at effec000 (32-bit, non-prefetchable) [size=16K] Region 4: Memory at effe8000 (32-bit, non-prefetchable) [size=16K] 00: 22 10 81 20 07 00 20 02 00 00 00 03 08 00 00 00 10: 00 00 00 ee 00 40 ff ef 00 00 ff ef 00 c0 fe ef 20: 00 80 fe ef 00 00 00 00 00 00 00 00 22 10 81 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:01.2 1010: 1022:2082 Subsystem: 1022:2082 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at effe4000 (32-bit, non-prefetchable) [size=16K] 00: 22 10 82 20 06 00 a0 02 00 00 10 10 08 00 00 00 10: 00 40 fe ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 82 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:0e.0 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at f200 [size=256] Region 1: Memory at effff000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 81 07 00 90 82 10 00 00 02 00 20 00 00 10: 01 f2 00 00 00 f0 ff ef 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40 00:0f.0 0601: 1022:2090 (rev 03) Subsystem: 1022:2090 Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: I/O ports at 6000 [size=8] Region 1: I/O ports at 6100 [size=256] Region 2: I/O ports at 6200 [size=64] Region 3: I/O ports at 1000 [size=32] Region 4: I/O ports at 9d00 [size=128] Region 5: I/O ports at 9c00 [size=64] 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 10: 01 60 00 00 01 61 00 00 01 62 00 00 01 10 00 00 20: 01 9d 00 00 01 9c 00 00 00 00 00 00 22 10 90 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.2 0101: 1022:209a (rev 01) (prog-if 80) Subsystem: 1022:209a Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 248, Cache Line Size: 32 bytes Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at ff00 [size=16] 00: 22 10 9a 20 05 00 a0 02 01 80 01 01 08 f8 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 ff 00 00 00 00 00 00 00 00 00 00 22 10 9a 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.3 0401: 1022:2093 (rev 01) Subsystem: 1022:2093 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 11 Region 0: I/O ports at fe00 [size=128] 00: 22 10 93 20 05 00 a0 02 01 00 01 04 08 00 00 00 10: 01 fe 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 93 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 00 00:0f.4 0c03: 1022:2094 (rev 02) (prog-if 10) Subsystem: 1022:2094 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at efffe000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 94 20 06 00 30 02 02 10 03 0c 08 00 00 00 10: 00 e0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 94 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 00 00 00:0f.5 0c03: 1022:2095 (rev 02) (prog-if 20) Subsystem: 1022:2095 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at efffd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 95 20 06 00 30 02 02 20 03 0c 08 00 00 00 10: 00 d0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 95 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 00 00 00:10.0 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at f000 [size=256] Region 1: Memory at efffc000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 f0 00 00 00 c0 ff ef 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40 00:11.0 0180: 10b9:5281 (rev a4) (prog-if 85) Subsystem: 10b9:5281 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 128, Cache Line Size: 512 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at fd00 [size=8] Region 1: I/O ports at fc00 [size=4] Region 2: I/O ports at fb00 [size=8] Region 3: I/O ports at fa00 [size=4] Region 4: I/O ports at f900 [size=16] [virtual] Expansion ROM at 20000000 [disabled] [size=64K] 00: b9 10 81 52 05 00 a0 02 a4 85 80 01 80 80 80 00 10: 01 fd 00 00 01 fc 00 00 01 fb 00 00 01 fa 00 00 20: 01 f9 00 00 00 00 00 00 00 00 00 00 b9 10 81 52 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:11.1 0180: 10b9:5228 (rev c6) (prog-if 85) Subsystem: 10b9:5281 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 128 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at f800 [size=8] Region 1: I/O ports at f700 [size=4] Region 2: I/O ports at f600 [size=8] Region 3: I/O ports at f500 [size=4] Region 4: I/O ports at f400 [size=16] 00: b9 10 28 52 05 00 a0 02 c6 85 80 01 00 80 80 00 10: 01 f8 00 00 01 f7 00 00 01 f6 00 00 01 f5 00 00 20: 01 f4 00 00 00 00 00 00 a0 00 00 00 b9 10 81 52 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:12.0 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at ee00 [size=256] Region 1: Memory at efffb000 (32-bit, non-prefetchable) [size=256] [virtual] Expansion ROM at 20010000 [disabled] [size=64K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 ee 00 00 00 b0 ff ef 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40

4 5

[LinuxBIOS] [lbv2][patch]Support i18n'd GCCs
by Patrick Georgi 03 Jan '08

03 Jan '08

Hi, attached patch fixes build on i18n'd GCCs which might not emit "install:" as expected. Regards, Patrick Georgi

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coreboot January 2008