coreboot January 2008

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[LinuxBIOS] r547 - LinuxBIOSv3/include/arch/x86
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: hailfinger Date: 2008-01-05 02:33:28 +0100 (Sat, 05 Jan 2008) New Revision: 547 Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: include/arch/x86/amd_geodelx.h had duplicated #defines by accident in r546. Remove them again. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h =================================================================== --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev 546) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-05 01:33:28 UTC (rev 547) @@ -572,11 +572,6 @@ */ #define LX_STACK_BASE DCACHE_RAM_BASE #define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) #define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ #define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */

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[LinuxBIOS] r546 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: hailfinger Date: 2008-01-05 00:19:49 +0100 (Sat, 05 Jan 2008) New Revision: 546 Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: These changes implement a fixed Geode LX Cache As Ram that allows a return from disable_car. - Move the cache as ram memory to 0x80000 instead of 0xc8000, as the C range is really tricky to get right :-) - Modify the geode disable_car to ensure the cache is flushed to ram on the wbinvd. With these changes, I get a payload loaded. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:14:10 UTC (rev 545) +++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:19:49 UTC (rev 546) @@ -22,6 +22,7 @@ #include <lib.h> #include <msr.h> #include <amd_geodelx.h> +#include <console.h> static const struct msrinit msr_table[] = { /* Setup access to cache under 1MB. */ @@ -59,5 +60,12 @@ for (i = 0; i < ARRAY_SIZE(msr_table); i++) wrmsr(msr_table[i].msrnum, msr_table[i].msr); - __asm__("wbinvd\n"); + /* OK, here is the theory: we should be able to copy + * the data back over itself, and the wbinvd should then + * flush to memory. Let's see. + */ + __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); + __asm__ __volatile__ ("wbinvd\n"); + banner(BIOS_DEBUG, "Disable_car: done wbinvd"); + banner(BIOS_DEBUG, "disable_car: done"); } Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h =================================================================== --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:14:10 UTC (rev 545) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev 546) @@ -566,12 +566,17 @@ /* ------------------------ */ #define DCACHE_RAM_SIZE 0x08000 -#define DCACHE_RAM_BASE 0xc8000 +#define DCACHE_RAM_BASE 0x80000 /* This is where the DCache will be mapped and be used as stack. It would be * cool if it was the same base as LinuxBIOS normal stack. */ #define LX_STACK_BASE DCACHE_RAM_BASE #define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) +/* This is where the DCache will be mapped and be used as stack. It would be + * cool if it was the same base as LinuxBIOS normal stack. + */ +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) #define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ #define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */

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[LinuxBIOS] r545 - LinuxBIOSv3/lib
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: hailfinger Date: 2008-01-05 00:14:10 +0100 (Sat, 05 Jan 2008) New Revision: 545 Modified: LinuxBIOSv3/lib/console.c Log: Change die() to make it JTAG friendly. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: LinuxBIOSv3/lib/console.c =================================================================== --- LinuxBIOSv3/lib/console.c 2008-01-04 23:12:22 UTC (rev 544) +++ LinuxBIOSv3/lib/console.c 2008-01-04 23:14:10 UTC (rev 545) @@ -82,9 +82,31 @@ printk(BIOS_INFO, console_test); } +/** + * Halt and loop due to a fatal error. + * There have been several iterations of this function. + * The first simply did a hlt(). Doing a hlt() can make jtag debugging + * very difficult as one can not break into a hlt instruction on some CPUs. + * Second was to do a console_tx_byte of a NULL character. + * A number of concerns were raised about doing this idea. + * Third idea was to do an inb from port 0x80, the POST port. That design + * makes us very CPU-specific. + * The fourth idea was just POSTING the same + * code over and over. That would erase the most recent POST code, + * hindering diagnosis. + * + * For now, for lack of a good alternative, + * we will continue to call console_tx_byte. We call with a NULL since + * it will clear any FIFOs in the path and won't clutter up the output, + * since NULL doesn't print a visible character on most terminal + * emulators. + * + * @param str A string to print for the error + * + */ void die(const char *str) { printk(BIOS_EMERG, str); while (1) - hlt(); + console_tx_byte(0, (void *)0); }

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[LinuxBIOS] r544 - in LinuxBIOSv3: include lib northbridge/amd/geodelx
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: hailfinger Date: 2008-01-05 00:12:22 +0100 (Sat, 05 Jan 2008) New Revision: 544 Modified: LinuxBIOSv3/include/console.h LinuxBIOSv3/lib/console.c LinuxBIOSv3/northbridge/amd/geodelx/raminit.c Log: Add a banner function to lib/console.c that is SHARED so all code can use it. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: LinuxBIOSv3/include/console.h =================================================================== --- LinuxBIOSv3/include/console.h 2008-01-04 12:53:09 UTC (rev 543) +++ LinuxBIOSv3/include/console.h 2008-01-04 23:12:22 UTC (rev 544) @@ -48,5 +48,6 @@ SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))), int msg_level, const char *fmt, ...); +SHARED(banner, void, int msg_level, const char *msg); #endif /* CONSOLE_H */ Modified: LinuxBIOSv3/lib/console.c =================================================================== --- LinuxBIOSv3/lib/console.c 2008-01-04 12:53:09 UTC (rev 543) +++ LinuxBIOSv3/lib/console.c 2008-01-04 23:12:22 UTC (rev 544) @@ -46,6 +46,29 @@ return i; } +/** + * Print a nice banner so we know what step we died on. + * + * @param level The printk level (e.g. BIOS_EMERG) + * @param s String to put in the middle of the banner + */ + +void banner(int level, const char *s) +{ + int i; + /* 10 = signs and a space. */ + printk(level, "========== "); + for(i = 11; *s; i++, s++) + printk(level, "%c", *s); + /* trailing space */ + printk(level, " "); + i++; + /* fill it up to 80 columns */ + for(; i < 80; i++) + printk(level, "="); + printk(level, "\n"); +} + void console_init(void) { static const char console_test[] = Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2008-01-04 12:53:09 UTC (rev 543) +++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2008-01-04 23:12:22 UTC (rev 544) @@ -36,19 +36,6 @@ u8 spd_read_byte(u16 device, u8 address); /** - * Print a nice banner so we know what step we died on. - * - * @param s String to put in the middle of the banner - */ - -void banner(char *s) -{ - printk(BIOS_DEBUG, "==========================="); - printk(BIOS_DEBUG, s); - printk(BIOS_DEBUG, "======================================\n"); -} - -/** * Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port, * to ensure the message is visible. * @@ -83,14 +70,14 @@ dimm_setting = 0; - banner("Check present"); + banner(BIOS_DEBUG, "Check present"); /* Check that we have a DIMM. */ if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) return; /* Field: Module Banks per DIMM */ /* EEPROM byte usage: (5) Number of DIMM Banks */ - banner("MODBANKS"); + banner(BIOS_DEBUG, "MODBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { printk(BIOS_EMERG, "Number of module banks not compatible\n"); @@ -101,7 +88,7 @@ /* Field: Banks per SDRAM device */ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ - banner("FIELDBANKS"); + banner(BIOS_DEBUG, "FIELDBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { printk(BIOS_EMERG, "Number of device banks not compatible\n"); @@ -117,7 +104,7 @@ *; (31) Module Bank Density *; Size = Module Density * Module Banks */ - banner("SPDNUMROWS"); + banner(BIOS_DEBUG, "SPDNUMROWS"); if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { @@ -127,7 +114,7 @@ } /* Size = Module Density * Module Banks */ - banner("SPDBANKDENSITY"); + banner(BIOS_DEBUG, "SPDBANKDENSITY"); dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY); /* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc @@ -143,9 +130,9 @@ /* Module Density * Module Banks */ /* Shift to multiply by the number of DIMM banks. */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; - banner("BEFORT CTZ"); + banner(BIOS_DEBUG, "BEFORT CTZ"); dimm_size = __builtin_ctz(dimm_size); - banner("TEST DIMM SIZE>8"); + banner(BIOS_DEBUG, "TEST DIMM SIZE>8"); if (dimm_size > 8) { /* 8 is 1 GB only support 1 GB per DIMM */ printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); @@ -177,9 +164,9 @@ * example, #col_addr_bits = 7 (06h), it adds 3 to get 10, then does * 2^10=1K. Get it? */ - banner("PAGESIZE"); + banner(BIOS_DEBUG, "PAGESIZE"); spd_byte = num_col_addr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; - banner("MAXCOLADDR"); + banner(BIOS_DEBUG, "MAXCOLADDR"); if (spd_byte > MAX_COL_ADDR) { printk(BIOS_EMERG, "DIMM page size not compatible\n"); post_code(ERROR_SET_PAGE); @@ -193,9 +180,9 @@ /* 0 = 1k, 1 = 2k, 2 = 4k, etc. */ dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; - banner("RDMSR CF07"); + banner(BIOS_DEBUG, "RDMSR CF07"); msr = rdmsr(MC_CF07_DATA); - banner("WRMSR CF07"); + banner(BIOS_DEBUG, "WRMSR CF07"); if (dimm == dimm0) { msr.hi &= 0xFFFF0000; msr.hi |= dimm_setting; @@ -203,7 +190,7 @@ msr.hi &= 0x0000FFFF; msr.hi |= dimm_setting << 16; } - banner("ALL DONE"); + banner(BIOS_DEBUG, "ALL DONE"); wrmsr(MC_CF07_DATA, msr); }

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[LinuxBIOS] r3033 build service
by LinuxBIOS information 04 Jan '08

04 Jan '08

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 3033 to the LinuxBIOS source repository and caused the following changes: Change Log: Add board enable for the gigabyte ga_2761gxdk board Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3033&device=serengeti_che… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] fiddly MSRs on lx
by ron minnich 04 Jan '08

04 Jan '08

attached are two files: a list of all the LX settings and MSRs and their values, and the program I used to generate them (which is just the .h files all mashed into C code). This is a lifesaver when you're trying to figure out "which the @@@@ MSR IS THAT ANYWAY?" thanks ron

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[LinuxBIOS] patch: enable ga_2761gxdk flash enable
by ron minnich 04 Jan '08

04 Jan '08

This is to enable flashrom on the ga_2761gxdk. I have tested it and it works. ron

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[LinuxBIOS] r3033 - trunk/util/flashrom
by svn＠openbios.org 04 Jan '08

04 Jan '08

Author: rminnich Date: 2008-01-04 18:22:44 +0100 (Fri, 04 Jan 2008) New Revision: 3033 Modified: trunk/util/flashrom/board_enable.c Log: Add board enable for the gigabyte ga_2761gxdk board Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-01-04 16:22:09 UTC (rev 3032) +++ trunk/util/flashrom/board_enable.c 2008-01-04 17:22:44 UTC (rev 3033) @@ -381,6 +381,8 @@ "gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash}, + {0x1039, 0x0761, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + "gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK", it87xx_probe_spi_flash}, {0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e}, {0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,

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[LinuxBIOS] r3032 build service
by LinuxBIOS information 04 Jan '08

04 Jan '08

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 3032 to the LinuxBIOS source repository and caused the following changes: Change Log: Print at least the vendor for SPI flash chips if the exact chip ID is unknown. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3032&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] [PATCH] flashrom: add generic vendor ID printing for SPI chips
by Carl-Daniel Hailfinger 04 Jan '08

04 Jan '08

Print at least the vendor for SPI flash chips if the exact chip ID is unknown. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-generic/flash.h =================================================================== --- flashrom-generic/flash.h (Revision 3031) +++ flashrom-generic/flash.h (Arbeitskopie) @@ -59,10 +59,13 @@ * entry of each section should be the manufacturer ID, followed by the * list of devices from that manufacturer (sorted by device IDs). * - * All LPC/FWH parts (parallel flash) have 8-bit device IDs. + * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no + * continuation code. * All SPI parts have 16-bit device IDs. */ +#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ + #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ Index: flashrom-generic/flashchips.c =================================================================== --- flashrom-generic/flashchips.c (Revision 3031) +++ flashrom-generic/flashchips.c (Arbeitskopie) @@ -185,5 +185,13 @@ probe_jedec, erase_chip_jedec, write_49f002}, {"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, + {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, + {"SST unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, + {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, + probe_spi, NULL, NULL}, {NULL,} }; Index: flashrom-generic/spi.c =================================================================== --- flashrom-generic/spi.c (Revision 3031) +++ flashrom-generic/spi.c (Arbeitskopie) @@ -263,13 +263,16 @@ model_id = (readarr[1] << 8) | readarr[2]; printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { - /* Print the status register before erase to tell the + /* Print the status register to tell the * user about possible write protection. */ generic_spi_prettyprint_status_register(flash); return 1; } + /* Test if this is a pure vendor match. */ + if (manuf_id == flash->manufacture_id && GENERIC_DEVICE_ID == flash->model_id) + return 1; } return 0;

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coreboot January 2008