coreboot January 2008

coreboot@coreboot.org

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[LinuxBIOS] AMD RS690 Register Reference Guide released
by Carl-Daniel Hailfinger 07 Jan '08

07 Jan '08

Hi, I was made aware of the following doc release: AMD RS690 Register Reference Guide http://www.x.org/docs/AMD/43372_rs690_rrg_3.00o.pdf While the public SB600 documentation is still missing a Register Reference Guide, at least we have some way to start a port to the RS690 or make ourselves familiar with it. Regards, Carl-Daniel

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[LinuxBIOS] [PATCH] v3: use #define for POST codes
by Carl-Daniel Hailfinger 07 Jan '08

07 Jan '08

The current parameter situation of post_code() is rather mixed between numeric constants and #defines for such constants. Since grepping the tree shouldn't be necessary to find a POST code and we already have too many duplicated POST codes, gather almost all of them in a common header file. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-postcode/include/post_code.h =================================================================== --- LinuxBIOSv3-postcode/include/post_code.h (Revision 548) +++ LinuxBIOSv3-postcode/include/post_code.h (Arbeitskopie) @@ -25,6 +25,41 @@ SHARED(post_code, void, u8 value); -#define POST_START_OF_MAIN 0x01 +/* This is a collection of existing POST values used by post_code(). + * port80_post() and Geode specific codes are not (yet?) listed here. + * FIXME: Conflicts remain. + */ +#define POST_START_OF_MAIN 0x01 +#define POST_KBD_EMPTY_INPUT_BUFFER 0x00 +#define POST_KBD_EMPTY_OUTPUT_BUFFER 0x00 +#define POST_STAGE1_STOP_AP 0xf0 +#define POST_STAGE1_ENABLE_ROM 0xf2 +#define POST_STAGE1_MAIN 0x02 +#define POST_STAGE2_BEGIN 0x20 +#define POST_STAGE2_PHASE1_START 0x30 +#define POST_STAGE2_PHASE1_ENTER 0x31 +#define POST_STAGE2_PHASE1_DONE 0x3e +#define POST_STAGE2_PHASE1_EXIT 0x3f +#define POST_STAGE2_PHASE2_PCI_SET_METHOD 0x5f +#define POST_STAGE2_PHASE2_START 0x40 +#define POST_STAGE2_PHASE2_ENTER 0x41 +#define POST_STAGE2_PHASE2_DONE 0x4e +#define POST_STAGE2_PHASE2_EXIT 0x4f +#define POST_STAGE2_PHASE3_START 0x30 +#define POST_STAGE2_PHASE3_MIDDLE 0x41 +#define POST_STAGE2_PHASE3_SCAN_ENTER 0x42 +#define POST_STAGE2_PHASE3_SCAN_EXIT 0x4e +#define POST_STAGE2_PHASE4_START 0x40 +#define POST_STAGE2_PHASE5_START 0x50 +#define POST_STAGE2_PHASE6_START 0x60 +#define POST_STAGE2_WRITE_TABLES 0x70 +#define POST_STAGE2_ARCH_WRITE_TABLES_ENTER 0x9a +#define POST_STAGE2_ARCH_WRITE_TABLES_MIDDLE 0x96 +#define POST_STAGE2_PCISCANBUS_ENTER 0x24 +#define POST_STAGE2_PCISCANBUS_DONEFORLOOP 0x25 +#define POST_STAGE2_PCISCANBUS_EXIT 0x55 +#define POST_ELFBOOT_JUMPING_TO_BOOTCODE 0xfe +#define POST_ELFBOOT_LOADER_STARTED 0xf8 +#define POST_ELFBOOT_LOADER_IMAGE_FAILED 0xff #endif /* POST_CODE_H */ Index: LinuxBIOSv3-postcode/device/device.c =================================================================== --- LinuxBIOSv3-postcode/device/device.c (Revision 548) +++ LinuxBIOSv3-postcode/device/device.c (Arbeitskopie) @@ -698,16 +698,16 @@ { struct device *dev; - post_code(0x31); + post_code(POST_STAGE2_PHASE1_ENTER); printk(BIOS_DEBUG, "Phase 1: Very early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->phase1_set_device_operations) { dev->ops->phase1_set_device_operations(dev); } } - post_code(0x3e); + post_code(POST_STAGE2_PHASE1_DONE); printk(BIOS_DEBUG, "Phase 1: done\n"); - post_code(0x3f); + post_code(POST_STAGE2_PHASE1_EXIT); } /** @@ -721,7 +721,7 @@ { struct device *dev; - post_code(0x41); + post_code(POST_STAGE2_PHASE2_ENTER); printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname); @@ -734,9 +734,9 @@ printk(BIOS_SPEW, "\n"); } - post_code(0x4e); + post_code(POST_STAGE2_PHASE2_DONE); printk(BIOS_DEBUG, "Phase 2: Done.\n"); - post_code(0x4f); + post_code(POST_STAGE2_PHASE2_EXIT); } /** @@ -754,7 +754,7 @@ { unsigned int new_max; int do_phase3; - post_code(0x42); + post_code(POST_STAGE2_PHASE3_SCAN_ENTER); if (!busdevice || !busdevice->enabled || !busdevice->ops || !busdevice->ops->phase3_scan) { printk(BIOS_INFO, "%s: %s: busdevice %p enabled %d ops %p\n", @@ -786,7 +786,7 @@ } } } - post_code(0x4e); + post_code(POST_STAGE2_PHASE3_SCAN_EXIT); printk(BIOS_INFO, "%s: returning %d\n", __FUNCTION__, max); return new_max; } @@ -825,7 +825,7 @@ if (root->ops && root->ops->phase3_enable_scan) { root->ops->phase3_enable_scan(root); } - post_code(0x41); + post_code(POST_STAGE2_PHASE3_MIDDLE); if (!root->ops) { printk(BIOS_ERR, "dev_root_phase3 missing 'ops' initialization\nPhase 3: Failed.\n"); Index: LinuxBIOSv3-postcode/device/pci_device.c =================================================================== --- LinuxBIOSv3-postcode/device/pci_device.c (Revision 548) +++ LinuxBIOSv3-postcode/device/pci_device.c (Arbeitskopie) @@ -1096,7 +1096,7 @@ __func__, old_devices, bus->dev, bus->dev->dtsname); bus->children = 0; - post_code(0x24); + post_code(POST_STAGE2_PCISCANBUS_ENTER); printk(BIOS_SPEW, "PCI: scan devfn 0x%x to 0x%x\n", min_devfn, max_devfn); /* Probe all devices/functions on this bus with some optimization for @@ -1129,7 +1129,7 @@ } } printk(BIOS_SPEW, "PCI: Done for loop\n"); - post_code(0x25); + post_code(POST_STAGE2_PCISCANBUS_DONEFORLOOP); /* Die if any leftover static devices are are found. * There's probably a problem in the Config.lb. @@ -1155,7 +1155,7 @@ * Return how far we've got finding sub-buses. */ printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max); - post_code(0x55); + post_code(POST_STAGE2_PCISCANBUS_EXIT); return max; } Index: LinuxBIOSv3-postcode/lib/stage2.c =================================================================== --- LinuxBIOSv3-postcode/lib/stage2.c (Revision 548) +++ LinuxBIOSv3-postcode/lib/stage2.c (Arbeitskopie) @@ -46,13 +46,13 @@ /* TODO: Add comment. */ void show_all_devs(void); - post_code(0x20); + post_code(POST_STAGE2_BEGIN); dev_init(); /* Phase 1 was console init and making printk work. Both functions are * now performed by stage 1 code. Phase 1 is now without purpose. */ - post_code(0x30); + post_code(POST_STAGE2_PHASE1_START); dev_phase1(); show_all_devs(); @@ -60,34 +60,34 @@ * done. This is for ANYTHING that might have to happen before * device enumeration but that needs a printk. */ - post_code(0x40); + post_code(POST_STAGE2_PHASE2_START); dev_phase2(); show_all_devs(); /* Walk physical devices and add any dynamic devices to the * device tree. */ - post_code(0x30); + post_code(POST_STAGE2_PHASE3_START); dev_root_phase3(); show_all_devs(); /* Compute and assign the bus resources. */ - post_code(0x40); + post_code(POST_STAGE2_PHASE4_START); dev_phase4(); show_all_devs(); /* Now actually enable devices on the bus. */ - post_code(0x50); + post_code(POST_STAGE2_PHASE5_START); dev_root_phase5(); show_all_devs(); /* Initialize devices on the bus. */ - post_code(0x60); + post_code(POST_STAGE2_PHASE6_START); dev_phase6(); show_all_devs(); /* TODO: Add comment. */ - post_code(0x70); + post_code(POST_STAGE2_WRITE_TABLES); write_tables(); show_all_devs(); Index: LinuxBIOSv3-postcode/lib/elfboot.c =================================================================== --- LinuxBIOSv3-postcode/lib/elfboot.c (Revision 548) +++ LinuxBIOSv3-postcode/lib/elfboot.c (Arbeitskopie) @@ -146,7 +146,7 @@ //boot_successful(); printk(BIOS_DEBUG, "Jumping to boot code at %p\n", entry); - post_code(0xfe); + post_code(POST_ELFBOOT_JUMPING_TO_BOOTCODE); /* Jump to kernel */ /* most of the time, jmp_to_elf_entry is just a call. But this hook gives us @@ -169,7 +169,7 @@ result = 0; printk(BIOS_INFO, "ELF loader started.\n"); - post_code(0xf8); + post_code(POST_ELFBOOT_LOADER_STARTED); /* Scan for an elf header */ header_offset = -1; @@ -209,7 +209,7 @@ printk(BIOS_ERR, "Cannot load ELF image\n"); - post_code(0xff); + post_code(POST_ELFBOOT_LOADER_IMAGE_FAILED); } return 0; } Index: LinuxBIOSv3-postcode/arch/x86/keyboard.c =================================================================== --- LinuxBIOSv3-postcode/arch/x86/keyboard.c (Revision 548) +++ LinuxBIOSv3-postcode/arch/x86/keyboard.c (Arbeitskopie) @@ -7,7 +7,7 @@ { unsigned long timeout; for(timeout = 1000000; timeout && (inb(0x64) & 0x02); timeout--) { - post_code(0); + post_code(POST_KBD_EMPTY_INPUT_BUFFER); } return !!timeout; } @@ -16,7 +16,7 @@ { unsigned long timeout; for(timeout = 1000000; timeout && ((inb(0x64) & 0x01) == 0); timeout--) { - post_code(0); + post_code(POST_KBD_EMPTY_OUTPUT_BUFFER); } return !!timeout; } Index: LinuxBIOSv3-postcode/arch/x86/archtables.c =================================================================== --- LinuxBIOSv3-postcode/arch/x86/archtables.c (Revision 548) +++ LinuxBIOSv3-postcode/arch/x86/archtables.c (Arbeitskopie) @@ -77,7 +77,7 @@ low_table_start = 0; low_table_end = 16; - post_code(0x9a); + post_code(POST_STAGE2_ARCH_WRITE_TABLES_ENTER); /* This table must be betweeen 0xf0000 & 0x100000 */ // rom_table_end = write_pirq_routing_table(rom_table_end); @@ -92,7 +92,7 @@ // rom_table_end = (rom_table_end+1023) & ~1023; /* copy the smp block to address 0 */ - post_code(0x96); + post_code(POST_STAGE2_ARCH_WRITE_TABLES_MIDDLE); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ // new_low_table_end = write_smp_table(low_table_end); Index: LinuxBIOSv3-postcode/arch/x86/pci_ops_auto.c =================================================================== --- LinuxBIOSv3-postcode/arch/x86/pci_ops_auto.c (Revision 548) +++ LinuxBIOSv3-postcode/arch/x86/pci_ops_auto.c (Arbeitskopie) @@ -88,5 +88,5 @@ { printk(BIOS_INFO, "Finding PCI configuration type.\n"); dev->ops->ops_pci_bus = pci_check_direct(); - post_code(0x5f); + post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD); } Index: LinuxBIOSv3-postcode/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3-postcode/arch/x86/stage1.c (Revision 548) +++ LinuxBIOSv3-postcode/arch/x86/stage1.c (Arbeitskopie) @@ -41,13 +41,13 @@ static void stop_ap(void) { // nothing yet - post_code(0xf0); + post_code(POST_STAGE1_STOP_AP); } static void enable_rom(void) { // nothing here yet - post_code(0xf2); + post_code(POST_STAGE1_ENABLE_ROM); } @@ -90,7 +90,7 @@ mem->map[0].type = LB_MEM_RAM; - post_code(0x02); + post_code(POST_STAGE1_MAIN); // before we do anything, we want to stop if we dont run // on the bootstrap processor.

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[LinuxBIOS] r549 - in LinuxBIOSv3: arch/x86 device include lib
by svn＠openbios.org 07 Jan '08

07 Jan '08

Author: hailfinger Date: 2008-01-07 17:34:34 +0100 (Mon, 07 Jan 2008) New Revision: 549 Modified: LinuxBIOSv3/arch/x86/archtables.c LinuxBIOSv3/arch/x86/keyboard.c LinuxBIOSv3/arch/x86/pci_ops_auto.c LinuxBIOSv3/arch/x86/stage1.c LinuxBIOSv3/device/device.c LinuxBIOSv3/device/pci_device.c LinuxBIOSv3/include/post_code.h LinuxBIOSv3/lib/elfboot.c LinuxBIOSv3/lib/stage2.c Log: The current parameter situation of post_code() is rather mixed between numeric constants and #defines for such constants. Since grepping the tree shouldn't be necessary to find a POST code and we already have too many duplicated POST codes, gather almost all of them in a common header file. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/arch/x86/archtables.c =================================================================== --- LinuxBIOSv3/arch/x86/archtables.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/arch/x86/archtables.c 2008-01-07 16:34:34 UTC (rev 549) @@ -77,7 +77,7 @@ low_table_start = 0; low_table_end = 16; - post_code(0x9a); + post_code(POST_STAGE2_ARCH_WRITE_TABLES_ENTER); /* This table must be betweeen 0xf0000 & 0x100000 */ // rom_table_end = write_pirq_routing_table(rom_table_end); @@ -92,7 +92,7 @@ // rom_table_end = (rom_table_end+1023) & ~1023; /* copy the smp block to address 0 */ - post_code(0x96); + post_code(POST_STAGE2_ARCH_WRITE_TABLES_MIDDLE); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ // new_low_table_end = write_smp_table(low_table_end); Modified: LinuxBIOSv3/arch/x86/keyboard.c =================================================================== --- LinuxBIOSv3/arch/x86/keyboard.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/arch/x86/keyboard.c 2008-01-07 16:34:34 UTC (rev 549) @@ -7,7 +7,7 @@ { unsigned long timeout; for(timeout = 1000000; timeout && (inb(0x64) & 0x02); timeout--) { - post_code(0); + post_code(POST_KBD_EMPTY_INPUT_BUFFER); } return !!timeout; } @@ -16,7 +16,7 @@ { unsigned long timeout; for(timeout = 1000000; timeout && ((inb(0x64) & 0x01) == 0); timeout--) { - post_code(0); + post_code(POST_KBD_EMPTY_OUTPUT_BUFFER); } return !!timeout; } Modified: LinuxBIOSv3/arch/x86/pci_ops_auto.c =================================================================== --- LinuxBIOSv3/arch/x86/pci_ops_auto.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/arch/x86/pci_ops_auto.c 2008-01-07 16:34:34 UTC (rev 549) @@ -88,5 +88,5 @@ { printk(BIOS_INFO, "Finding PCI configuration type.\n"); dev->ops->ops_pci_bus = pci_check_direct(); - post_code(0x5f); + post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD); } Modified: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/arch/x86/stage1.c 2008-01-07 16:34:34 UTC (rev 549) @@ -41,13 +41,13 @@ static void stop_ap(void) { // nothing yet - post_code(0xf0); + post_code(POST_STAGE1_STOP_AP); } static void enable_rom(void) { // nothing here yet - post_code(0xf2); + post_code(POST_STAGE1_ENABLE_ROM); } @@ -90,7 +90,7 @@ mem->map[0].type = LB_MEM_RAM; - post_code(0x02); + post_code(POST_STAGE1_MAIN); // before we do anything, we want to stop if we dont run // on the bootstrap processor. Modified: LinuxBIOSv3/device/device.c =================================================================== --- LinuxBIOSv3/device/device.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/device/device.c 2008-01-07 16:34:34 UTC (rev 549) @@ -698,16 +698,16 @@ { struct device *dev; - post_code(0x31); + post_code(POST_STAGE2_PHASE1_ENTER); printk(BIOS_DEBUG, "Phase 1: Very early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->phase1_set_device_operations) { dev->ops->phase1_set_device_operations(dev); } } - post_code(0x3e); + post_code(POST_STAGE2_PHASE1_DONE); printk(BIOS_DEBUG, "Phase 1: done\n"); - post_code(0x3f); + post_code(POST_STAGE2_PHASE1_EXIT); } /** @@ -721,7 +721,7 @@ { struct device *dev; - post_code(0x41); + post_code(POST_STAGE2_PHASE2_ENTER); printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname); @@ -734,9 +734,9 @@ printk(BIOS_SPEW, "\n"); } - post_code(0x4e); + post_code(POST_STAGE2_PHASE2_DONE); printk(BIOS_DEBUG, "Phase 2: Done.\n"); - post_code(0x4f); + post_code(POST_STAGE2_PHASE2_EXIT); } /** @@ -754,7 +754,7 @@ { unsigned int new_max; int do_phase3; - post_code(0x42); + post_code(POST_STAGE2_PHASE3_SCAN_ENTER); if (!busdevice || !busdevice->enabled || !busdevice->ops || !busdevice->ops->phase3_scan) { printk(BIOS_INFO, "%s: %s: busdevice %p enabled %d ops %p\n", @@ -786,7 +786,7 @@ } } } - post_code(0x4e); + post_code(POST_STAGE2_PHASE3_SCAN_EXIT); printk(BIOS_INFO, "%s: returning %d\n", __FUNCTION__, max); return new_max; } @@ -825,7 +825,7 @@ if (root->ops && root->ops->phase3_enable_scan) { root->ops->phase3_enable_scan(root); } - post_code(0x41); + post_code(POST_STAGE2_PHASE3_MIDDLE); if (!root->ops) { printk(BIOS_ERR, "dev_root_phase3 missing 'ops' initialization\nPhase 3: Failed.\n"); Modified: LinuxBIOSv3/device/pci_device.c =================================================================== --- LinuxBIOSv3/device/pci_device.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/device/pci_device.c 2008-01-07 16:34:34 UTC (rev 549) @@ -1096,7 +1096,7 @@ __func__, old_devices, bus->dev, bus->dev->dtsname); bus->children = 0; - post_code(0x24); + post_code(POST_STAGE2_PCISCANBUS_ENTER); printk(BIOS_SPEW, "PCI: scan devfn 0x%x to 0x%x\n", min_devfn, max_devfn); /* Probe all devices/functions on this bus with some optimization for @@ -1129,7 +1129,7 @@ } } printk(BIOS_SPEW, "PCI: Done for loop\n"); - post_code(0x25); + post_code(POST_STAGE2_PCISCANBUS_DONEFORLOOP); /* Die if any leftover static devices are are found. * There's probably a problem in the Config.lb. @@ -1155,7 +1155,7 @@ * Return how far we've got finding sub-buses. */ printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max); - post_code(0x55); + post_code(POST_STAGE2_PCISCANBUS_EXIT); return max; } Modified: LinuxBIOSv3/include/post_code.h =================================================================== --- LinuxBIOSv3/include/post_code.h 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/include/post_code.h 2008-01-07 16:34:34 UTC (rev 549) @@ -25,6 +25,41 @@ SHARED(post_code, void, u8 value); -#define POST_START_OF_MAIN 0x01 +/* This is a collection of existing POST values used by post_code(). + * port80_post() and Geode specific codes are not (yet?) listed here. + * FIXME: Conflicts remain. + */ +#define POST_START_OF_MAIN 0x01 +#define POST_KBD_EMPTY_INPUT_BUFFER 0x00 +#define POST_KBD_EMPTY_OUTPUT_BUFFER 0x00 +#define POST_STAGE1_STOP_AP 0xf0 +#define POST_STAGE1_ENABLE_ROM 0xf2 +#define POST_STAGE1_MAIN 0x02 +#define POST_STAGE2_BEGIN 0x20 +#define POST_STAGE2_PHASE1_START 0x30 +#define POST_STAGE2_PHASE1_ENTER 0x31 +#define POST_STAGE2_PHASE1_DONE 0x3e +#define POST_STAGE2_PHASE1_EXIT 0x3f +#define POST_STAGE2_PHASE2_PCI_SET_METHOD 0x5f +#define POST_STAGE2_PHASE2_START 0x40 +#define POST_STAGE2_PHASE2_ENTER 0x41 +#define POST_STAGE2_PHASE2_DONE 0x4e +#define POST_STAGE2_PHASE2_EXIT 0x4f +#define POST_STAGE2_PHASE3_START 0x30 +#define POST_STAGE2_PHASE3_MIDDLE 0x41 +#define POST_STAGE2_PHASE3_SCAN_ENTER 0x42 +#define POST_STAGE2_PHASE3_SCAN_EXIT 0x4e +#define POST_STAGE2_PHASE4_START 0x40 +#define POST_STAGE2_PHASE5_START 0x50 +#define POST_STAGE2_PHASE6_START 0x60 +#define POST_STAGE2_WRITE_TABLES 0x70 +#define POST_STAGE2_ARCH_WRITE_TABLES_ENTER 0x9a +#define POST_STAGE2_ARCH_WRITE_TABLES_MIDDLE 0x96 +#define POST_STAGE2_PCISCANBUS_ENTER 0x24 +#define POST_STAGE2_PCISCANBUS_DONEFORLOOP 0x25 +#define POST_STAGE2_PCISCANBUS_EXIT 0x55 +#define POST_ELFBOOT_JUMPING_TO_BOOTCODE 0xfe +#define POST_ELFBOOT_LOADER_STARTED 0xf8 +#define POST_ELFBOOT_LOADER_IMAGE_FAILED 0xff #endif /* POST_CODE_H */ Modified: LinuxBIOSv3/lib/elfboot.c =================================================================== --- LinuxBIOSv3/lib/elfboot.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/lib/elfboot.c 2008-01-07 16:34:34 UTC (rev 549) @@ -146,7 +146,7 @@ //boot_successful(); printk(BIOS_DEBUG, "Jumping to boot code at %p\n", entry); - post_code(0xfe); + post_code(POST_ELFBOOT_JUMPING_TO_BOOTCODE); /* Jump to kernel */ /* most of the time, jmp_to_elf_entry is just a call. But this hook gives us @@ -169,7 +169,7 @@ result = 0; printk(BIOS_INFO, "ELF loader started.\n"); - post_code(0xf8); + post_code(POST_ELFBOOT_LOADER_STARTED); /* Scan for an elf header */ header_offset = -1; @@ -209,7 +209,7 @@ printk(BIOS_ERR, "Cannot load ELF image\n"); - post_code(0xff); + post_code(POST_ELFBOOT_LOADER_IMAGE_FAILED); } return 0; } Modified: LinuxBIOSv3/lib/stage2.c =================================================================== --- LinuxBIOSv3/lib/stage2.c 2008-01-05 01:35:57 UTC (rev 548) +++ LinuxBIOSv3/lib/stage2.c 2008-01-07 16:34:34 UTC (rev 549) @@ -46,13 +46,13 @@ /* TODO: Add comment. */ void show_all_devs(void); - post_code(0x20); + post_code(POST_STAGE2_BEGIN); dev_init(); /* Phase 1 was console init and making printk work. Both functions are * now performed by stage 1 code. Phase 1 is now without purpose. */ - post_code(0x30); + post_code(POST_STAGE2_PHASE1_START); dev_phase1(); show_all_devs(); @@ -60,34 +60,34 @@ * done. This is for ANYTHING that might have to happen before * device enumeration but that needs a printk. */ - post_code(0x40); + post_code(POST_STAGE2_PHASE2_START); dev_phase2(); show_all_devs(); /* Walk physical devices and add any dynamic devices to the * device tree. */ - post_code(0x30); + post_code(POST_STAGE2_PHASE3_START); dev_root_phase3(); show_all_devs(); /* Compute and assign the bus resources. */ - post_code(0x40); + post_code(POST_STAGE2_PHASE4_START); dev_phase4(); show_all_devs(); /* Now actually enable devices on the bus. */ - post_code(0x50); + post_code(POST_STAGE2_PHASE5_START); dev_root_phase5(); show_all_devs(); /* Initialize devices on the bus. */ - post_code(0x60); + post_code(POST_STAGE2_PHASE6_START); dev_phase6(); show_all_devs(); /* TODO: Add comment. */ - post_code(0x70); + post_code(POST_STAGE2_WRITE_TABLES); write_tables(); show_all_devs();

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[LinuxBIOS] Sponsor for day 3 of linuxbios summit?
by ron minnich 07 Jan '08

07 Jan '08

Calling all commercial LinuxBIOS users: I am hoping some of you can rise to the occasion and kick in some money :-) Here is the issue. Day 3 will have $7500 in costs, and it is a headache for the conference manager to collect that extra money. So, they have asked me: "Is there is a sponsor we could contact to contribute to the Linux Bios meeting to help cover costs for the extra day....they get credit for sponsoring entire summit but in particular the extra costs. We would rather not collect a separate registration fee from those staying for Saturday.?" If anyone out there can help, please contact me privately. Thanks ron

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[LinuxBIOS] r3036 build service
by LinuxBIOS information 07 Jan '08

07 Jan '08

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 3036 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for the SST25VF040B 4 Mbit SPI flash chip. Straight from the data sheet, not tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3036&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] [PATCH] flashrom: SST25VF040B support
by Carl-Daniel Hailfinger 07 Jan '08

07 Jan '08

Add support for the SST25VF040B 4 Mbit SPI flash chip. Straight from the data sheet, not tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ron/flashchips.c =================================================================== --- flashrom-ron/flashchips.c (Revision 3031) +++ flashrom-ron/flashchips.c (Arbeitskopie) @@ -52,6 +52,8 @@ probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,

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[LinuxBIOS] r3036 - trunk/util/flashrom
by svn＠openbios.org 07 Jan '08

07 Jan '08

Author: hailfinger Date: 2008-01-07 14:48:51 +0100 (Mon, 07 Jan 2008) New Revision: 3036 Modified: trunk/util/flashrom/flashchips.c Log: Add support for the SST25VF040B 4 Mbit SPI flash chip. Straight from the data sheet, not tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-01-07 11:13:16 UTC (rev 3035) +++ trunk/util/flashrom/flashchips.c 2008-01-07 13:48:51 UTC (rev 3036) @@ -52,6 +52,8 @@ probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,

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[LinuxBIOS] r3035 build service
by LinuxBIOS information 07 Jan '08

07 Jan '08

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "duwe" checked in revision 3035 to the LinuxBIOS source repository and caused the following changes: Change Log: Improve readability and remove redundancy by wrapping similar smp_write_intsrc calls in preprocessor macros. Also add some comments about the actual devices the INTs belong to. Signed-off-by: Torsten Duwe <duwe(a)lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3035&device=serengeti_che… If something broke during this checkin please be a pain in duwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r3035 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
by svn＠openbios.org 07 Jan '08

07 Jan '08

Author: duwe Date: 2008-01-07 12:13:16 +0100 (Mon, 07 Jan 2008) New Revision: 3035 Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c Log: Improve readability and remove redundancy by wrapping similar smp_write_intsrc calls in preprocessor macros. Also add some comments about the actual devices the INTs belong to. Signed-off-by: Torsten Duwe <duwe(a)lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2008-01-06 01:10:54 UTC (rev 3034) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2008-01-07 11:13:16 UTC (rev 3035) @@ -98,46 +98,60 @@ } } -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_mcp55, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_mcp55, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_mcp55, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_mcp55, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_mcp55, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_mcp55, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_mcp55, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_mcp55, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_mcp55, 0xf); + /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa); +/* ISA ints are edge-triggered, and usually originate from the ISA bus, + * or its remainings. + */ +#define ISA_INT(intr, pin)\ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_mcp55, (pin)) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22 + ISA_INT(1,1); + ISA_INT(0,2); + ISA_INT(3,3); + ISA_INT(4,4); + ISA_INT(6,6); + ISA_INT(7,7); + ISA_INT(8,8); + ISA_INT(12,12); + ISA_INT(13,13); + ISA_INT(14,14); + ISA_INT(15,15); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23 +/* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin)) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23 + PCI_INT(0,sbdn+1,1, 10); /* SMBus */ + PCI_INT(0,sbdn+2,0, 22); /* USB */ + PCI_INT(0,sbdn+2,1, 23); /* USB */ + PCI_INT(0,sbdn+6,1, 23); /* HD Audio */ + PCI_INT(0,sbdn+5,0, 20); /* SATA */ + PCI_INT(0,sbdn+5,1, 23); /* SATA */ + PCI_INT(0,sbdn+5,2, 21); /* SATA */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21 + PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 - + /* The PCIe slots, each on its own bus */ for(j=7; j>=2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (1+j+i)%4); + for(i=0;i<4;i++) { /* map all functions */ + PCI_INT(j,0,i, 16+(1+j+i)%4); } } - for(j=0; j<2; j++) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x07+j)<<2)|i, apicid_mcp55, 0x10 + (3+i+j)%4); + /* On bus 1: the physical PCI bus slots... */ + for(j=0; j<2; j++) /* on a Rev 1.x board, they are devs 7 and 8 */ + for(i=0;i<4;i++) { /* map all functions */ + PCI_INT(1,7+j,i, 16+(3+i+j)%4); } - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x0a)<<2)|0, apicid_mcp55, 0x12); + /* ... and OB FireWire */ + PCI_INT(1,0x0a,0, 18); + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);

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Re: [LinuxBIOS] #69: Fix mptable util so the output will compile
by LinuxBIOS 07 Jan '08

07 Jan '08

#69: Fix mptable util so the output will compile ------------------------------------------------------+--------------------- Reporter: Jon Dufresne <jon.dufresne(a)gmail.com> | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: patch needs review ------------------------------------------------------+--------------------- Comment (by cozzie): The current mptable output doesn't compile, and with this patch, it does. That's not to say that the output is perfect, but it's one step closer ;) Unless there's some reason not to fix this: Acked-by: Corey Osgood <corey dot osgood at gmail dot com> I'll let someone else do the commit, just in case there's some reason not to do this, but I can't think of any. Thanks for the patches Jon, sorry they've sat here in limbo for so long. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/69#comment:1> LinuxBIOS <http://www.linuxbios.org/>

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coreboot January 2008