coreboot January 2008

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[LinuxBIOS] r3043 - trunk/LinuxBIOSv2/src/cpu/amd/car
by svn＠openbios.org 10 Jan '08

10 Jan '08

Author: hailfinger Date: 2008-01-10 18:48:25 +0100 (Thu, 10 Jan 2008) New Revision: 3043 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: This patch introduces 4k CAR size granularity for the AMD x86 CAR code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Benefits: * a nice code size reduction * less #ifdef clutter for Family 10h * paranoid checks for CAR size * clear abstractions This has been tested by Marc Jones and Jordan Crouse. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 13:27:22 UTC (rev 3042) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:48:25 UTC (rev 3043) @@ -2,6 +2,7 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -120,82 +121,70 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x10000 - /* enable caching for 64K using fixed mtrr */ - movl $0x268, %ecx /* fix4k_c0000*/ - #if CAR_FAM10 == 1 - movl $0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl $0x06060606, %edx /* WB IO type */ - #endif - - movl %edx, %eax - wrmsr - movl $0x269, %ecx - wrmsr +/* 0x06 is the WB IO type for a given 4k segment. + * 0x1e is the MEM IO type for a given 4k segment (K10 and above). + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution + * of this macro, %eax and %edx are cleared. Later invocations of this + * macro will have a monotonically increasing segs parameter. + */ + xorl \reg, \reg +#if CAR_FAM10 == 1 +.elseif \segs == 1 + movl $0x1e000000, \reg /* WB MEM type */ +.elseif \segs == 2 + movl $0x1e1e0000, \reg /* WB MEM type */ +.elseif \segs == 3 + movl $0x1e1e1e00, \reg /* WB MEM type */ +.elseif \segs >= 4 + movl $0x1e1e1e1e, \reg /* WB MEM type */ +#else +.elseif \segs == 1 + movl $0x06000000, \reg /* WB IO type */ +.elseif \segs == 2 + movl $0x06060000, \reg /* WB IO type */ +.elseif \segs == 3 + movl $0x06060600, \reg /* WB IO type */ +.elseif \segs >= 4 + movl $0x06060606, \reg /* WB IO type */ #endif +.endif +.endm -#if CacheSize == 0xc000 - /* enable caching for 16K using fixed mtrr */ - movl $0x268, %ecx /* fix4k_c4000*/ - #if CAR_FAM10 == 1 - movl $0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl $0x06060606, %edx /* WB IO type */ - #endif - xorl %eax, %eax - wrmsr - /* enable caching for 32K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_c8000*/ - #if CAR_FAM10 == 1 - movl $0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl $0x06060606, %edx /* WB IO type */ - #endif - movl %edx, %eax - wrmsr +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x10000 +#error Invalid CAR size, must be at most 64k. #endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif - -#if CacheSize == 0x8000 - /* enable caching for 32K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_c8000*/ - #if CAR_FAM10 == 1 - movl $0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl $0x06060606, %edx /* WB IO type */ - #endif - movl %edx, %eax - wrmsr +#if CacheSize > 0x8000 + /* enable caching for 32K-64K using fixed mtrr */ + movl $0x268, %ecx /* fix4k_c0000*/ + simplemask CacheSize, 0x8000 + wrmsr #endif -#if CacheSize < 0x8000 - /* enable caching for 16K/8K/4K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_cc000*/ - #if CacheSize == 0x4000 - #if CAR_FAM10 == 1 - movl $0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl $0x06060606, %edx /* WB IO type */ - #endif - #endif - #if CacheSize == 0x2000 - #if CAR_FAM10 == 1 - movl $0x1e1e0000, %edx /* WB MEM type */ - #else - movl $0x06060000, %edx /* WB IO type */ - #endif - #endif - #if CacheSize == 0x1000 - #if CAR_FAM10 == 1 - movl $0x1e000000, %edx /* WB MEM type */ - #else - movl $0x06000000, %edx /* WB IO type */ - #endif - #endif - xorl %eax, %eax + /* enable caching for 0-32K using fixed mtrr */ + movl $0x269, %ecx /* fix4k_c8000*/ + simplemask CacheSize, 0 wrmsr -#endif /* enable memory access for first MBs using top_mem */ movl $TOP_MEM, %ecx

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[LinuxBIOS] v3 status
by ron minnich 10 Jan '08

10 Jan '08

v3 loads and runs on an alix1c. So far, the only payload that works is a RET. Even a simple OUTB followed by a RET fails. Any ideas on this? I'm flummoxed. Could it be the stack location? Stack is at 0x8fxxx. Also, I have to run at < 1 MB, the memory above 1 MB reads back as all ffffffff. that's all for today. First payload is a good day. fixing disable_car is even better :-) we're getting there. ron

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[LinuxBIOS] Fwd: Possible stack protect solutions (RESEND)
by ron minnich 10 Jan '08

10 Jan '08

This patch will enable setting distro variables such as -fno_stack_protector as needed. It is a simple patch to buildtarget and can be extended for other uses. If this patch is acceptable then we can fix the various makefiles to include the variable. The only remaining question is the name -- is CPU_OPT really appropriate? Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> ---------- Forwarded message ---------- From: ron minnich <rminnich(a)gmail.com> Date: Dec 20, 2007 11:24 AM Subject: Re: [LinuxBIOS] Possible stack protect solutions To: Jordan Crouse <jordan.crouse(a)amd.com> Cc: linuxbios(a)linuxbios.org Try this. This patch to buildtarget 1. sets up cpu opt for the no stack protector thing 2. sets up the makefiles for the target 3. the target builds But it's not picking up CPU_OPT. So we MUST have the other patch that ALWAYS includes CPU_OPT. That said, I'd rather make the variable DISTRO_CC_OPT or some such. Thanks ron

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[LinuxBIOS] PCI device memory resource
by Baski 10 Jan '08

10 Jan '08

For a PCI device to request memory resource of ,say 1MB, should it have onboard memory of 1MB ? TIA -- People wielding power and authority always desire to destroy the sources which gave them that power. Or, is it the other way round? --------------------------------- Never miss a thing. Make Yahoo your homepage.

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[LinuxBIOS] r3042 build service
by LinuxBIOS information 10 Jan '08

10 Jan '08

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 3042 to the LinuxBIOS source repository and caused the following changes: Change Log: Enable MX25L8005 support in flashrom. The #defines were already there. Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3042&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] svn question
by joe＠smittys.pointclark.net 10 Jan '08

10 Jan '08

Dumb question, but I can't seem to find any real good docs on svn. How to I commit a patch to my local LinuxBIOSV2 copy?? Thanks - Joe

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[LinuxBIOS] r3042 - trunk/util/flashrom
by svn＠openbios.org 10 Jan '08

10 Jan '08

Author: hailfinger Date: 2008-01-10 14:27:22 +0100 (Thu, 10 Jan 2008) New Revision: 3042 Modified: trunk/util/flashrom/flashchips.c Log: Enable MX25L8005 support in flashrom. The #defines were already there. Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-01-09 11:37:58 UTC (rev 3041) +++ trunk/util/flashrom/flashchips.c 2008-01-10 13:27:22 UTC (rev 3042) @@ -52,6 +52,8 @@ probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"MX25L8005", MX_ID, MX_25L8005, 1024, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,

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[LinuxBIOS] [PATCH] Gigabyte GA-2761GXDK readability improvements
by Carl-Daniel Hailfinger 10 Jan '08

10 Jan '08

Dear Morgan, please check the patch below to make LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c interrupt routing code easier to understand. If it is possible, lspci -nnvv of the board would be great to improve documentation. Regards, Carl-Daniel Use macros to improve readability of the device-to-pin IRQ assignments in GA-2761GXDK mptables.c. Thanks to Torsten Duwe for initial code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-smpwriteintsrc/src/mainboard/gigabyte/ga_2761gxdk/mptable.c =================================================================== --- LinuxBIOSv2-smpwriteintsrc/src/mainboard/gigabyte/ga_2761gxdk/mptable.c (Revision 3036) +++ LinuxBIOSv2-smpwriteintsrc/src/mainboard/gigabyte/ga_2761gxdk/mptable.c (Arbeitskopie) @@ -100,44 +100,52 @@ } } -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sis966, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sis966, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sis966, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sis966, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sis966, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sis966, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sis966, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sis966, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sis966, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sis966, 0xf); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+1)<<2)|1, apicid_sis966, 0xa); +/* ISA ints are edge-triggered, and usually originate from the ISA bus, + * or its remainings. + */ +#define ISA_INT(intr, pin)\ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sis966,(pin)) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+2)<<2)|0, apicid_sis966, 0x16); // 22 + ISA_INT(0x1, 0x1); + ISA_INT(0x0, 0x2); + ISA_INT(0x3, 0x3); + ISA_INT(0x4, 0x4); + ISA_INT(0x6, 0x6); + ISA_INT(0x7, 0x7); + ISA_INT(0x8, 0x8); + ISA_INT(0xc, 0xc); + ISA_INT(0xd, 0xd); + ISA_INT(0xe, 0xe); + ISA_INT(0xf, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+2)<<2)|1, apicid_sis966, 0x17); // 23 +/* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin)) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+6)<<2)|1, apicid_sis966, 0x17); // 23 + PCI_INT(0, sbdn+1, 1, 0xa); + PCI_INT(0, sbdn+2, 0, 0x16); // 22 + PCI_INT(0, sbdn+2, 1, 0x17); // 23 + PCI_INT(0, sbdn+6, 1, 0x17); // 23 + PCI_INT(0, sbdn+5, 0, 0x14); // 20 + PCI_INT(0, sbdn+5, 1, 0x17); // 23 + PCI_INT(0, sbdn+5, 2, 0x15); // 21 + PCI_INT(0, sbdn+8, 0, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+5)<<2)|0, apicid_sis966, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+5)<<2)|1, apicid_sis966, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+5)<<2)|2, apicid_sis966, 0x15); // 21 - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+8)<<2)|0, apicid_sis966, 0x16); // 22 - for(j=7; j>=2; j--) { if(!bus_sis966[j]) continue; for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[j], (0x00<<2)|i, apicid_sis966, 0x10 + (2+j+i+4-sbdn%4)%4); + PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j=0; j<2; j++) for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[1], ((0x06+j)<<2)|i, apicid_sis966, 0x10 + (2+i+j)%4); + PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/

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[LinuxBIOS] Question about disassembler for byte stream
by Andon Tschauschev 10 Jan '08

10 Jan '08

Hi, Is there such thing like disassembler for byte streams? For example: I extract some memory through /dev/mem: 'dd if=/dev/mem of=./dump_1.dat bs=1 count=708K' Then I can look at the extracted memory using hexdump: 'hexdump -vC dump_1.dat | less' But reading machine code is not very comfortable... With the mentioned disassembler I would be able to do: 'streamdisass -i dump_1.dat -o dump_1.asm' and then enjoy the asm-representation of the dump? Thanks Andon ____________________________________________________________________________________ Looking for last minute shopping deals? Find them fast with Yahoo! Search. http://tools.search.yahoo.com/newsearch/category.php?category=shopping

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[LinuxBIOS] [PATCH] v3: rewrite generic x86 CAR code
by Carl-Daniel Hailfinger 09 Jan '08

09 Jan '08

This patch is an attempt at introducing 4k CAR size granularity for the generic x86 code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. The patch is identical (except one build fix) to what was committed in r3038 to v2. Since the patch is identical, I'm tempted to steal Marc's ack from r3038. Acked-by: Marc Jones <marc.jones(a)amd.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-CAR/arch/x86/stage0_i586.S =================================================================== --- LinuxBIOSv3-CAR/arch/x86/stage0_i586.S (Revision 549) +++ LinuxBIOSv3-CAR/arch/x86/stage0_i586.S (Arbeitskopie) @@ -301,38 +301,59 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x10000 - /* enable caching for 64K using fixed mtrr */ +/* 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution + * of this macro, %eax and %edx are cleared. Later invocations of this + * macro will have a monotonically increasing segs parameter. + */ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x06000000, \reg +.elseif \segs == 2 + movl $0x06060000, \reg +.elseif \segs == 3 + movl $0x06060600, \reg +.elseif \segs >= 4 + movl $0x06060606, \reg +.endif +.endm + +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x10000 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 + /* enable caching for 32K-64K using fixed mtrr */ movl $0x268, %ecx /* fix4k_c0000*/ - movl $0x06060606, %eax /* WB IO type */ - movl %eax, %edx + simplemask CacheSize, 0x8000 wrmsr - movl $0x269, %ecx - wrmsr #endif -#if CacheSize == 0x8000 - /* enable caching for 32K using fixed mtrr */ + /* enable caching for 0-32K using fixed mtrr */ movl $0x269, %ecx /* fix4k_c8000*/ - movl $0x06060606, %eax /* WB IO type */ - movl %eax, %edx + simplemask CacheSize, 0 wrmsr -#endif - /* enable caching for 16K/8K/4K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 - movl $0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 - movl $0x06060000, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 - movl $0x06000000, %edx /* WB IO type */ -#endif - xorl %eax, %eax - wrmsr - #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom.

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coreboot January 2008