coreboot January 2008

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347 discussions

r555 - in coreboot-v3: mainboard/pcengines/alix1c northbridge/amd/geodelx
by svn＠openbios.org 17 Jan '08

17 Jan '08

Author: rminnich Date: 2008-01-17 06:37:41 +0100 (Thu, 17 Jan 2008) New Revision: 555 Added: coreboot-v3/northbridge/amd/geodelx/dts Modified: coreboot-v3/mainboard/pcengines/alix1c/dts Log: This change adds a dts file for the amd geodelx northbridge. The northbridge has several constructors, so it is required, if these constructors are to be compiled in to the running image, that a dts be provided. To use the dts, one must add a /config/ line to the components that use it, hence the change to the mainboard dts . This change does not produce a working bios as far as I can tell. But it is still important to have it in. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-01-16 16:18:32 UTC (rev 554) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-01-17 05:37:41 UTC (rev 555) @@ -26,6 +26,7 @@ enabled; }; domain0 { + /config/("northbridge/amd/geodelx"); enabled; pcidomain = "0"; device0,0 { Added: coreboot-v3/northbridge/amd/geodelx/dts =================================================================== --- coreboot-v3/northbridge/amd/geodelx/dts (rev 0) +++ coreboot-v3/northbridge/amd/geodelx/dts 2008-01-17 05:37:41 UTC (rev 555) @@ -0,0 +1,24 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + constructor = "geodelx_north_constructors"; +}; +

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Add some Winbond SPI chips to flashrom (patch).
by Ronald Hoogenboom 17 Jan '08

17 Jan '08

Hi, On my m57sli-rev.2 board, there is a winbond 25X40 SPI flash bios chip, which flashrom didn't have support for, so I added it (and the relatives). Patch below: Index: flash.h =================================================================== --- flash.h (revision 3051) +++ flash.h (working copy) @@ -247,6 +247,12 @@ #define W_49V002A 0xB0 #define W_49V002FA 0x32 +#define WINBOND_SPI_ID 0xEF /* Winbond serial flash devices */ +#define W_25X10 0x3011 +#define W_25X20 0x3012 +#define W_25X40 0x3013 +#define W_25X80 0x3014 + /* udelay.c */ void myusec_delay(int time); void myusec_calibrate_delay(); Index: flashchips.c =================================================================== --- flashchips.c (revision 3051) +++ flashchips.c (working copy) @@ -122,6 +122,14 @@ probe_jedec, erase_chip_jedec, write_39sf020}, {"W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, + {"W25x10", WINBOND_SPI_ID, W_25X10, 128, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"W25x20", WINBOND_SPI_ID, W_25X20, 256, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"W25x40", WINBOND_SPI_ID, W_25X40, 512, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"W25x80", WINBOND_SPI_ID, W_25X80, 1024, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024,

3 2

LAR walking madness
by Carl-Daniel Hailfinger 16 Jan '08

16 Jan '08

Hi, Stefan and I spoke about various v3 stuff yesterday and it seems we have a slightly hackish solution which will avoid full LAR walks completely by changing the header format. Basically, to avoid a full walk, you have to avoid requesting a nonexistant file. How? We have two sources of for such requests and they are easy to fix: - Looking for "normal/initram" when we should have looked for "fallback/initram". Simply make sure check_normal_boot_flag() returns a value matching the files you stored in the LAR. - Looking for "stage2" and "payload" segments which are not there. We can either add a "number of segments" field to the LAR header or we restrict the number of segments to 2. Incremental caching of lookups can still save some time, but avoiding the full walk completely is going to save more time than anything else. I will not be able to write any new code before the end of February (my thesis simply eats up all my time), but both points above should be really reasy to fix. Regards, Carl-Daniel

4 6

PIRQ Tables
by Cimino Vittorio 16 Jan '08

16 Jan '08

HI, What choice i must disable into the config kernel file for testing properly my $PIR table? TNX

3 4

AMD Family 0Fh CAR and L1 cache tags
by Carl-Daniel Hailfinger 16 Jan '08

16 Jan '08

Hi! The BKDG rev. 3.08 for AMD Family 0Fh states that it is possible to use a CAR area with a size of 64K in section 13.16 "Cache Initialization For General Storage During Boot". It also says that during DRAM training CAR size must be reduced. For DDR training, 256 cache lines with L1 cache tag indexes 00h-FFh are reserved and must not be used as CAR. The text then refers to the AMD64 Arch Programmers Manual Vol. 2 for more details on L1 function. However, I couldn't find any explanation why L1 cache tag indexes 00h-FFh correspond to address space C0000h-C3FFFh when fixed size MTRRs are active. Explanations would be very welcome. Regards, Carl-Daniel

5 9

CN700 with a KVR533D2N4/512 memory module
by Urbez Santana Roma 16 Jan '08

16 Jan '08

If you have read my last message, i comment that memory works if i change the values of do_ram_command functions in sdram_enable() written by Corey Osgood for the CN700 with a C7 CPU. When is used with KVR533D2N4/512 module, the memory not works, but i have finally, changing the values that works fine, with execution of branch instructions if i use the values: ..... part of src/northbrigde/cn700/raminit.c ..... // 6. Mode register set. PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); //safe value for now, BL=8, WR=5, CAS=5 /* (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ // do_ram_command( RAM_COMMAND_MRS, 0x0022d8);//by Corey do_ram_command( RAM_COMMAND_MRS, 0x1022d8);//With the 20 bit ON. // 7. Mode register set. PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); // do_ram_command( RAM_COMMAND_MRS, 0x21c20);//default OCD calibration by Corey do_ram_command( RAM_COMMAND_MRS, 0x121c20);//With the 20 bit ON. // do_ram_command( RAM_COMMAND_MRS, 0x20020);//exit calibration mode do_ram_command( RAM_COMMAND_MRS, 0x120020);//With the 20 bit ON. // 8. Normal operation PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); do_ram_command( RAM_COMMAND_NORMAL, 0); .....end part of src/borthbrigde/cn700/raminit.c.....

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Re: [LinuxBIOS] AMD SimNOW question
by Marc Karasek 16 Jan '08

16 Jan '08

Is there anyway under SimNow to send the console output to a log file. I have linuxbios up and running :-) but the Linux kernel I have as a boot loader is crashing.. I have tried to stop it at the point when it starts dmping the same message to the screen but it is nearly impossible to time it right. /********************* Marc Karasek MTS Sun Microsystems mailto:marc.karasek@sun.com ph:770.360.6415 *********************/ Myles Watson wrote: > Marc, > > I sent the wrong one for serengeti-cheetah last time. Sorry. > > Myles > > On Jan 11, 2008 11:49 AM, Marc Karasek <Marc.Karasek(a)sun.com> wrote: > >> I have managed to cobble together a build structure that tries to build. >> >> It gets to the point of building the linuxbios image and it chokes >> because the image is to large for the romsize. >> >> Can someone shed some light on what Config.lb should be set to to get >> this to compile. >> >> The payload buildrom is generating is 790,000+ bytes big. >> >> /********************* >> Marc Karasek >> MTS >> Sun Microsystems >> mailto:marc.karasek@sun.com >> ph:770.360.6415 >> *********************/ >> >> >> >> >> ron minnich wrote: >> >>> On Jan 8, 2008 2:38 PM, Marc Karasek <Marc.Karasek(a)sun.com> wrote: >>> >>> >>>> I have found the main problem with svn. It looks like if you use svn co >>>> http:// it will use the proxy settings under servers. If you do a svn >>>> co svn:// it tries to do a dns lookup, which fails behind a proxy server >>>> :-(. I have not been able to find any info on setting svn up to use a >>>> proxy when doing svn:// type checkouts. >>>> >>>> >>> There is a way to do it, maybe: http://subversion.tigris.org/faq.html#proxy >>> >>> ron >>> >>>

4 7

CN700 with a KVR533D2N4/512 memory module.
by Urbez Santana Roma 16 Jan '08

16 Jan '08

I have the same module DRAM as more people that have written in the list that not work with the initialization, and have tested the code of Corey (1000 thanks Corey), and have the same results, but have found a aproximation to the solution: This DDR2 module works with Corey memory initialization with a little change with another values that another mainboard finds with the same DDR2 module, and then works, with the C7/CN700 but y not known what are the bits that differ with the Corey version. The changes for /src/northbridge/via/cn700/raminit.c (marked with a //by another mainboard) ......chunk of sdram_enable()...... /* (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ // do_ram_command( RAM_COMMAND_MRS, 0x0022d8);//by Corey do_ram_command( RAM_COMMAND_MRS, 0x101258);//by another mainboard // do_ram_command( RAM_COMMAND_MRS, 0x2258);//a second mainboard // 7. Mode register set. PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); // do_ram_command( RAM_COMMAND_MRS, 0x21c20);//default OCD calibration by do_ram_command( RAM_COMMAND_MRS, 0x121c20);//By another mainboard // do_ram_command( RAM_COMMAND_MRS, 0x20020);//exit calibration mode do_ram_command( RAM_COMMAND_MRS, 0x120020);//by another mainboard // 8. Normal operation PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); do_ram_command( RAM_COMMAND_NORMAL, 0); ......chunk of sdram_enable()...... Only have a problem with these values. The RAM works correctly all 511MB, i can write memory and then test it... but when i jumps to a program loaded in memory, hangs with the first Branch instruction, for example "je". I not wise, if the C7/CN700 can have a optimization system with branches, that requires a feature with SDRAM activated. If the code loaded not have branches, it works. Is for me absurd.... El vie, 21-12-2007 a las 02:44 +0100, linuxbios-request(a)linuxbios.org escribió: > KVR533D2N4/512,

1 0

r3051 - in trunk: . coreboot-v1 coreboot-v2
by svn＠coreboot.org 16 Jan '08

16 Jan '08

Author: stepan Date: 2008-01-16 17:25:13 +0100 (Wed, 16 Jan 2008) New Revision: 3051 Added: trunk/coreboot-v1/ trunk/coreboot-v2/ Removed: trunk/LinuxBIOSv1/ trunk/LinuxBIOSv2/ Log: rename linuxbios to coreboot Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Property changes on: trunk/coreboot-v1 ___________________________________________________________________ Name: svn:ignore + COPYING INSTALL install-sh missing mkinstalldirs aclocal.m4 Makefile.in configure config.log config.cache config.status Makefile Name: svn:mergeinfo + Property changes on: trunk/coreboot-v2 ___________________________________________________________________ Name: svn:mergeinfo +

1 0

r554 - / coreboot-v3
by svn＠openbios.org 16 Jan '08

16 Jan '08

Author: stepan Date: 2008-01-16 17:18:32 +0100 (Wed, 16 Jan 2008) New Revision: 554 Added: coreboot-v3/ Removed: LinuxBIOSv3/ Log: rename repository from LinuxBIOSv3 to coreboot-v3 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Property changes on: coreboot-v3 ___________________________________________________________________ Name: svn:ignore + .kconfig.d .config .tmpconfig.h .xcompile build .config.old Name: svn:mergeinfo +

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coreboot January 2008