coreboot January 2008

coreboot@coreboot.org

79 participants
347 discussions

[PATCH] Support for the MSI MS-6119
by Uwe Hermann 15 Jan '08

15 Jan '08

Here's an implementation for the MSI MS-6119 board, information provided in another thread by Maarten van Eeuwijk <mechno(a)gmail.com>. More info on the board: http://global.msi.com.tw/index.php?func=proddesc&prod_no=332&maincat_no=1 Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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MTRR question
by aaron lwe 15 Jan '08

15 Jan '08

> Why do we use a variable MTRR to map the bios code > instead of the fixed ones? > I've been trying to integrate a VGA bios alongside the normal > and fallback images, but that 2 ^ XIP size requirement is > making things very difficult. > So far I have only managed to include the VGA bios code blob > if I disable the normal image in the config.lb > Is there anything preventing me from using the fixed size MTRR > descriptors for the bios area instead of a variable one? No, I think it's ok to only use fixed range mtrr for bios area. The intel manuals said for the first 1MB area, if fixed mtrrs are enabled, the processor uses the memory type stored for the appropriate fixed-range mtrr.

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lspci -tvnn, superiotool -dV, flashrom -V, for the MSI 6119 mainboard.
by Maarten van Eeuwijk 15 Jan '08

15 Jan '08

Hi all, A few day's ago I asked Uwe for a little help on my MS6119 board from MSI. He adviced me to post the results of lspci -tvnn, superiotool -dV and flashrom -V to the mailing list, for the sake of archiving. So, after some creative wiring I got a LiveCD going and ran the pieces of software mentioned above. The tests are done with minimal hardware, all the PCI slots were empty. The only slots filled were the CPU slot and the AGP slot. For the ones who think they recognize a Asus p2b here, you're almost dead on. The MS6119 has the same hardware and similair layout but the wiring is likely to be different. Here are the results: *lspci -tvnn:* -[0000:00]-+-00.0 8086:7190 +-01.0-[0000:01]----00.0 1002:4742 +-07.0 8086:7110 +-07.1 8086:7111 +-07.2 8086:7112 \-07.3 8086:7113 *superiotool -dV:* superiotool r3011 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Found Winbond W83977TF (id=0x97, rev=0x73) at 0x3f0 Register dump: idx 20 21 22 23 24 25 26 28 2a 2b 2c 2d 2e 2f val 97 73 ff fe 84 00 00 00 00 00 00 00 00 ff def 97 73 ff fe MM 00 MM 00 00 00 00 RR RR RR LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 01 03 78 07 03 00 def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard / mouse) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 00 42 def 01 00 60 00 64 01 0c 83 LDN 0x07 (GPIO 1) idx 30 60 61 62 63 64 65 70 72 e0 e1 e2 e3 e4 e5 e6 e7 f1 val 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 00 def 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 00 LDN 0x08 (GPIO 2) idx 30 60 61 70 72 e8 e9 ea eb ec ed ee f0 f1 f2 f3 f4 val 01 00 00 00 00 10 01 01 01 01 08 01 00 ff 00 00 00 def 00 00 00 00 00 01 01 01 01 01 01 01 00 RR 00 00 00 LDN 0x09 (GPIO 3) idx 30 60 61 62 63 64 65 70 72 e0 e1 e2 e3 e4 e5 e6 e7 f1 val 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 00 def 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 00 LDN 0x0a (ACPI) idx 30 60 61 62 63 64 65 70 e0 e1 02 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 fe ff val 00 00 00 00 00 00 00 00 00 00 ff 07 00 00 00 0f 07 00 00 00 00 00 00 def 00 00 00 00 00 00 00 00 00 00 NA MM RR 00 00 00 00 00 00 00 00 RR RR Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff *flashrom -V:* Calibrating delay loop... 100M loops per second. OK. No LinuxBIOS table found. Found chipset "PIIX4/PIIX4E/PIIX4M", enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x7f, id2 0x3f Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x7f, id2 0x3f Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for At29C040A, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for At29C020, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for At49F002(N), 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for At49F002(N)T, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for EN29F002(A)(N)T, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for EN29F002(A)(N)B, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x7f, id2 0x3f Probing for MX29F002, 256 KB probe_29f002: id1 0xda, id2 0x45 Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L8005, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF040B, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST28SF040A, 512 KB probe_28sf040: id1 0x7f, id2 0x3f Probing for SST39SF010A, 128 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST39SF020A, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST39SF040, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST39VF020, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF040B, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF040, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF020A, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xda, id2 0x45 Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0x7f, id2 0x3f Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0x7f, id2 0x3f Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0xda, id2 0x45 Probing for Pm49FL004, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for W29C011, 128 KB probe_jedec: id1 0xda, id2 0x45 Probing for W29C040P, 512 KB probe_jedec: id1 0xda, id2 0x45 Probing for W29C020C, 256 KB probe_jedec: id1 0xda, id2 0x45 W29C020C found at physical address 0xfffc0000. Flash part is W29C020C (256 KB). No operations were specified. That's it. Uwe told me he could help me with hacking up a MS6119 target file with this info. Once the bios works, I 'll use it to make a router of that board utilizing coreboot, m0n0wall, a few ethernet NIC's and a Compact flash card. Once that works I will demonstrate it at school. Perhaps I 'll put it against a Cisco router in a VS showdown on troughput. Might be cool to beat a 800+ bucks Cisco machine with an old piece of hardware I found in a trashbox. tnx for your time, Maarten "merethan"

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[LinuxBIOS] Messing with CAR in a big way
by Carl-Daniel Hailfinger 14 Jan '08

14 Jan '08

Hi, I'm currently considering to completely ignore what the BKDG says about CAR and change the AMD CAR code to 64k size at an *arbitrary* address. Right. Any address of your choice as long as it is below 1 MB. A few rules, though: If you want the CAR area to reside below 0x80000 (512k), you have to respect a 64k alignment. Between 0x80000 and 0xC0000 (768k) the alignment is 16k and between 0xC0000 and and 0x100000 (1M) the alignment is 4k. Ron, where would you like to have the CAR area to avoid copying the stack around in v2? Any places where stack location is hardcoded without using the usual #define? Regards, Carl-Daniel

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Re: [coreboot] r554 - /
by Carl-Daniel Hailfinger 14 Jan '08

14 Jan '08

On 14.01.2008 19:10, svn(a)openbios.org wrote: > Author: stepan > Date: 2008-01-14 19:10:22 +0100 (Mon, 14 Jan 2008) > New Revision: 554 > > Added: > coreboot-v3/ > Log: > > rename to coreboot > This changeset disables "svn up". Latest revision I can update to in my v3 trees is r553. Regards, Carl-Daniel

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r554 - /
by svn＠openbios.org 14 Jan '08

14 Jan '08

Author: stepan Date: 2008-01-14 19:10:22 +0100 (Mon, 14 Jan 2008) New Revision: 554 Added: coreboot-v3/ Log: rename to coreboot Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de>

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Adding information about the console(s) to lbtable
by Patrick Georgi 14 Jan '08

14 Jan '08

Hi, I work on adding information about the console to the lbtable, so that the payload can parse it to figure out where it might find a user. Right now, I only store TTYS0_BASE (that config variable) in a special lbtable record (LB_TAG_SERIAL) and let the payload assume it should use the serial port. Before I go on, I have a couple of questions: - Do we want to store more information than coreboot itself uses? (eg. serial ports that aren't used, but known to exist) - if so, what kind of information: io ports, irqs, memory areas, ... - how should this information be mapped to devices? - our own naming scheme (serial0, ...) - adopting an existing one (com1, ttyS0, cua0, ..) - How flexible should the console routing be? - multiple target consoles - multiple targets of the same type (eg. both COM1 and COM2) I don't want to design a too flexible system (that no-one uses and is only partially implemented by payloads), but I don't want to force payloads to adapt to an ever-changing interface either. I also don't want to work on this and scrap everything on pre-commit time, because the consensus is that the design sucks, which is why I ask for opinions. :-) Once this is settled, I'll implement it for lbv2 and lbv3 and add support to the various utilities (lxbios and whoever else dumps the table). Regards, Patrick

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Flash is not happening on SST49LF004B flashrom
by malatesh 14 Jan '08

14 Jan '08

Hi everybody........We are working on Linux Bios.Initially we read the Bios (Pm49FL004 ) content that is present in the K8Upgrade-VM800Motherboard in to a file (jan14),then we removed the Bios chip and inserted the new flashrom (SST49LF004B) and tried to write the contents on to the new flashrom but flash is not happening properly and Bios is not written to the Bios chip......why it is  not happening please guide us .........I included all the steps clearly ........  [root@turtle9 flashrom]# flashrom Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). No operations were specified. Reading the original Bios content in to the file jan14: [root@turtle9 flashrom]# flashrom -r jan14 Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Reading Flash...done [root@turtle9 flashrom]# flashrom -v jan14 Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. ***Then we removed the original Bios chip and insearted the new flashrom SST49LF004B and tried to write the content present in the file jan14 ,but finally we got the result as bellow ........ Writing on to the new Bios chip:  [root@turtle9 flashrom]# flashrom -w jan14 Calibrating delay loop... OK. No LinuxBIOS table found. Found chipset "VT8237", enabling flash write... OK. generic_spi_command called, but no SPI chipset detected SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 With regards Malatesh....

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[LinuxBIOS] abit be6
by Jouni Mettälä 14 Jan '08

14 Jan '08

LinuxBios booted to filo. Motherboard is abit be6. This is azza/pt-6ibd/ config using http://coreboot.org/AZZA_PT-6IBD_Build_Tutorial. filo config was also from it. Config was modified to use just fallback image with 128k chip. I don't have spare 256k chip now. Flashing needed uniflash.

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Re: [coreboot] [LinuxBIOS] Welcome to coreboot.
by Carl-Daniel Hailfinger 14 Jan '08

14 Jan '08

On 14.01.2008 14:37, Lars Randers wrote: > On 1/14/08, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> On 12.01.2008 02:43, ron minnich wrote: >> >>> Welcome to coreboot! >>> >>> [...] >>> >>> >>> We will make the changes slowly and with a lot of preparation. You >>> have already seen >>> the IRC channel change, and host names change over to coreboot.org. At >>> some point in >>> the next three months you will see a change in the svn repository >>> name. We're going to >>> be very careful to ensure nothing breaks. >>> >>> >> For svn repository moving, it would be nice to have a few people test it >> in all of its glory before it is done. >> > > Would it be too bold to suggest moving to a GIT repository? > I love the search capabilities of that thing... > While git is a nice revision control system and I also work with it for stuff besides coreboot, I fear it does not play well with our current process. Our current committer base is rather small and that makes it easy to use subversion. A few nice advantages of subversion over git are: - easy merging with upstream without cluttering history with "merge xy" changesets - extremely fast checkout - low storage requirements - ability to have subtrees in different repositories. Some of these points might become git features sometime in the future (or already are), but right now I prefer subversion for coreboot. Regards, Carl-Daniel

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coreboot January 2008