coreboot April 2007

coreboot@coreboot.org

76 participants
281 discussions

[LinuxBIOS] Options.lb File
by roger 20 Apr '07

20 Apr '07

If I'm not mistake, this file contains the default options for a mainboard target correct? But if I specify a conflicting option within the Config.lb file, shouldn't the Config.lb file take precedence? Btw, is there some documentation on LinuxBios besides scanning through the comments within the source? -- Roger http://www.eskimo.com/~roger/index.html Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61 Thu Apr 19 17:10:14 PDT 2007

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[LinuxBIOS] Guru, help: need advice on CMOS layout values
by Alexei I. Adamovich 20 Apr '07

20 Apr '07

Hi! So far I suspect I have problems loading Normal image because of WRONG CMOS LAYOUT. 1. Is this possible? The only difference I can see between Normal & Fallback images in targets/iwill/dk8_htx/Config.lb is the payload. 2. Is there more substantial difference behind the scene? Following is the "lxbios -a" output I'm getting ("[lxb]" is citation prefix): [lxb] boot_option = Normal [lxb] last_boot = Fallback [lxb] ECC_memory = Enable [lxb] baud_rate = 1200 [lxb] hw_scrubber = Enable [lxb] interleave_chip_selects = Enable [lxb] max_mem_clock = 200Mhz [lxb] dual_core = Disable [lxb] power_on_after_fail = Disable [lxb] debug_level = Spew [lxb] boot_first = HDD [lxb] boot_second = Fallback_HDD [lxb] boot_third = Fallback_HDD [lxb] boot_index = 0xf [lxb] boot_countdown = 0x3 [lxb] slow_cpu = off [lxb] nmi = Disable [lxb] iommu = Disable [lxb] lxbios: Can not read LinuxBIOS parameter user_data because layout info [lxb] specifies CMOS area that is too wide. In this state machine doesn't boot; after several resets Fallback image is being loaded--with no substantial problems I can see. So far, several more questions 3. Is the "max_mem_clock = 200Mhz" assignment normal for DDR400 mem? 4. What is the meaning of the "baud_rate" value? Is this serial console setting? (I have 115200 specified in the Config). 6. Are there some other suspicious settings there? 5. As to "user_data" parameter (last two lines): what can be done to give it the correct value? Should I clear all the CMOS and then start assigning all the values by hand? 7. What is the CMOS "layout info", where it resides and what are the correct values for it. Please, reply if you can give my any advice, pointer to related info or answer to any of these questions. Thanks in advance, Alexei I. Adamovich

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[LinuxBIOS] List of supported mainboards in the wiki
by Uwe Hermann 20 Apr '07

20 Apr '07

Hi, I've reworked the list of supported mainboards in the wiki quite a bit recently. The most notable change is that the boards are now sorted into categories. http://linuxbios.org/Supported_Motherboards For now we have these categories: * Desktops / Workstations * Servers * Laptops * Embedded / SBC / PC/104 * Mini-ITX * Set-top-boxes / Thin clients * Devel/Eval Boards * Miscellaneous Please have a look at all the mainbaords and let me know whether they're in the correct category, and/or if we need more categories etc. (the distinction between "desktop" and "server" is often quite subjective, thus I used whatever the vendor used; if the board is marked as "server solution" or such it goes into the server categrory) Please also check the "Status" fields, some are still marked "?" and we should mark them either as "OK" or "Broken/WIP"... Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] VGA on iwill:dk8_htx: a reqest and a question?
by Alexei I. Adamovich 19 Apr '07

19 Apr '07

Hi! Got LB release 2587 running on iwill:dk8_htx at last. Have a request and a question I. Request Please, change the section heading (and the corresponding sentence in its contents) from Append VGA BIOS to Prepend VGA BIOS and use "cat" to concat the two images to use "cat" to prepend VGA BIOS image to linuxbios.rom image in the "DK8HTX Build Tutorial". Seems this change can save a lot of time and effort to a LB newbie. :) BTW, here special thanks to Randall Philipson! His "Push pins" idea is incredible! II. Question Had anybody got onboard VGA working on DK8-HTX? IMHO I have done all the steps mentioned in DK8HTX Build Tutorial--config diff attached. But output goes only to the serial console, no sign of life on VGA (to clarify, there is a change to get flashrom working--#63, fix still isn't merged to the trunk?,--but VGA doesn't live without it also). VGA BIOS got as said (size=32K) and prepended to linuxbios.rom, its contents starts from 55AA. Flashrom worked fine, LB -> etherboot runs fine, Linux loaded and flying (still haven't tried HTX card). Maybe, I am missing something? Have anybody any clue? Serial console boot log attached also. Thanks in advance, Alexei I. Adamovich

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[LinuxBIOS] Intel Southbridge ROM Protection mechanism
by Darmawan Salihun 19 Apr '07

19 Apr '07

Hi all, I'm new in this community. My name is darmawan from Indonesia. Ok, right to the matter, does Intel ICH5 southbridge (or other newer Inte southbridge) still protects (probably mirrors) the last 8KB block (bootblock) in the BIOS chip even when the protection bits in Block Locking Registers (BLRs) has been disabled? I experienced weird results between several flashing attempts using flashrom in Linux. SOme succeeded, some retain the original values. Anyone has an explanation on the issue? Regards, Darmawan

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Re: [LinuxBIOS] List of supported mainboards in the wiki
by Uwe Hermann 19 Apr '07

19 Apr '07

[Please always reply to the mailing list, not individual developers] On Thu, Apr 19, 2007 at 07:29:44AM -0600, Myles Watson wrote: > If you really want a desktop section, then you could make desktop separate > and combine workstation/server (That's where the fuzziness comes in, not > desktop/server). I guess that would make the desktop section pretty short, > but more accurately reflect the current situation. Hm, where do you see a difference between "Desktop" and "Workstation"? Personally, I use them as synonyms, but maybe I'm missing something. Also, what would be the criteria to differ between desktop and workstation/server then? Maybe we should just add a small note saying that the desktop/server categories can be pretty similar and you should check both? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] Help: IWILL DK8-HTX: Normal image doesn't run, POST code 0x80
by Alexei I. Adamovich 19 Apr '07

19 Apr '07

Hi,all! After some inspection of the serial console output, I've found that I never got the Normal image running, only the Fallback one. With lxbios I have changed boot_option value to the "Normal" value , then stopped the system. After turning the power on no serial console output was seen. The POST card displays the "80" (seems, the sequence was "00" -> "10" -> "80") Hardware reset changes nothing, but the POST sequence from 00 to 80 was repeated. After switching the power first off and then on, the Fallback image was loaded successfully. As to me, I thought that the only difference between the images is a payload contents. But clearly this Normal image hangs far before any payload is touched. What could be the problem? BTW, does anybody know the most recent LinuxBIOS release, that is confirmed working on iwill:dk8_htx witout problems? Thanks in advance, Alexei I. Adamovich

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Re: [LinuxBIOS] VGA on iwill:dk8_htx: a reqest and a question?
by Alexei I. Adamovich 19 Apr '07

19 Apr '07

Hi! Resending the message, since it was sent from different machine and it is "being held until the list moderator can review it for approval". On Thu, Apr 19, 2007 at 01:16:06AM -0700, Perry Wang wrote: > Once you have the VGA BIOS prepended properly, you can just uncomment these > lines in Config.lb > > chip drivers/pci/onboard > device pci 6.0 on end > register "rom_address" = "0xfff80000" > end > > that did the trick for me > I have done this before writing the initial message (is it in attached diff?). With no effect. :-( Please, share your positive experience: 1. What was LB release number? 2. From which stage LB has started writing to the console? 3. Have you done any other config changes? 4. Have you used the lxbios to change any LB CMOS settings. Could you please--if it possible for you--let me get the (gzipped?) version of videobios you have used with LinuxBIOS (I suspect, I missed something). BTW, do you have any card in the HTX slot installed? Alexei I. Adamovich

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Re: [LinuxBIOS] VGA on iwill:dk8_htx: a reqest and a question?
by Alexey I. Adamovich 19 Apr '07

19 Apr '07

Hi! On Thu, Apr 19, 2007 at 01:16:06AM -0700, Perry Wang wrote: > Once you have the VGA BIOS prepended properly, you can just uncomment these > lines in Config.lb > > chip drivers/pci/onboard > device pci 6.0 on end > register "rom_address" = "0xfff80000" > end > > that did the trick for me > Have done this before writing the initial message (is it in attached diff?. Please, share your experience. What was LB release number? >From which stage LB has started writing to the console? Have you done any other config changes? Is it possible for you to send me (gzipped?) the version of videobios you used (I suspect, I missed something). BTW, do you have any card in the HTX slot installed? Alexei I. Adamovich

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Re: [LinuxBIOS] AMD K8 + K8T890 + VT8237 + Asus A8V-E SE
by Rudolf Marek 19 Apr '07

19 Apr '07

> That looks ok, still. Can you post a complete log to the list? Yes here it goes. >> I guess something is wrong with the PCIe setup... Any ideas what might be wrong? >> In the meanwhile I will check the regs of KT890 to see what is set up >> differently in other functions. > > not necessarily. Maybe heap is just too tight. Try using twice as much > heap. I did 256K of heap now. Gets further, but this seems wrong.... Attached the log. Thanks, Rudolf LinuxBIOS-2.0.0_Normal Ne dub 15 07:56:48 CEST 2007 starting... core0 started: SBLink=00 NC node|link=00 ht reset - Ram1.00 Ram2.00 Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 44 SMBus Timout 40Device Error Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion NB CAP REG:00000119 Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion 200Mhz Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion Waiting until smbus ready Waiting until smbus ready smbus_error: 42 SMBus Timout 40Interrupt/SMI# was Successful Completion DIVISOR: 000a RDPREAMBLE: 000e Ram3 Initializing memory: done Ram4 v_esp=000ceeb8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Copying LinuxBIOS to RAM. src=fffa0000 dst=00004000 linxbios_ram.nrv2b length = 0000c335 linxbios_ram.bin length = 0001e420 Jumping to LinuxBIOS. LinuxBIOS-2.0.0_Normal Ne dub 15 07:56:48 CEST 2007 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=0 Found Rev E or Rev F later single core CPU: APIC: 00 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled In vt8237r_enable 1106 0238. Dumping NB XX: 06 11 38 02 06 00 30 22 00 00 00 06 00 00 00 00 XX: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 XX: bf 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 00 XX: 01 60 02 00 00 00 00 00 08 00 01 80 00 00 00 00 XX: 08 58 60 00 20 00 11 11 d0 00 00 00 22 06 75 00 XX: 02 00 00 00 00 00 00 00 00 00 00 00 0f 00 00 00 XX: 02 50 35 00 07 02 00 1f 00 00 00 00 28 00 00 00 XX: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Dumping NB done PCI: 00:00.0 [1106/0238] enabled PCI: 00:00.0 [1106/0238] enabled next_unitid: 0012 PCI: pci_scan_bus for bus 00 In vt8237r_enable 1106 0238. Dumping NB XX: 06 11 38 02 06 00 30 22 00 00 00 06 00 00 80 00 XX: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 XX: 7f db 10 b9 00 00 00 00 01 00 1f c4 00 0c 00 01 XX: 01 60 02 00 00 00 00 00 08 00 01 80 00 00 00 00 XX: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 XX: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 XX: 02 50 30 00 07 02 00 1f 00 00 00 00 28 00 00 00 XX: 80 00 00 00 20 0f 01 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 40 00 00 06 08 00 80 XX: 05 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 XX: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Dumping NB done PCI: 00:00.0 [1106/0238] enabled PCI: 00:00.1 [1106/1238] enabled PCI: 00:00.2 [1106/2238] enabled PCI: 00:00.3 [1106/3238] enabled PCI: 00:00.4 [1106/4238] enabled PCI: 00:00.5 [1106/5238] enabled PCI: 00:00.7 [1106/7238] enabled PCI: 00:01.0 [1106/b188] enabled PCI: 00:02.0 subbordinate bus PCI Express PCI: 00:02.0 [1106/a238] enabled PCI: 00:03.0 subbordinate bus PCI Express PCI: 00:03.0 [1106/c238] enabled PCI: 00:03.1 subbordinate bus PCI Express PCI: 00:03.1 [1106/d238] enabled PCI: 00:03.2 subbordinate bus PCI Express PCI: 00:03.2 [1106/e238] enabled PCI: 00:03.3 subbordinate bus PCI Express PCI: 00:03.3 [1106/f238] enabled PCI: 00:0b.0 [10ec/8139] enabled PCI: 00:0f.0 [1106/3149] enabled PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] enabled PCI: 00:10.5 [1106/d104] enabled In vt8237r_enable 1106 3227. Initialising Devices PCI: 00:11.0 [1106/3227] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:11.6 [1106/3068] enabled PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [1002/5b60] enabled PCI: 02:00.1 [1002/5b70] enabled PCI: 02:01.0 [1002/5b60] enabled PCI: 02:01.1 [1002/5b70] enabled PCI: 02:02.0 [1002/5b60] enabled PCI: 02:02.1 [1002/5b70] enabled PCI: 02:03.0 [1002/5b60] enabled PCI: 02:03.1 [1002/5b70] enabled PCI: 02:04.0 [1002/5b60] enabled PCI: 02:04.1 [1002/5b70] enabled PCI: 02:05.0 [1002/5b60] enabled PCI: 02:05.1 [1002/5b70] enabled PCI: 02:06.0 [1002/5b60] enabled PCI: 02:06.1 [1002/5b70] enabled PCI: 02:07.0 [1002/5b60] enabled PCI: 02:07.1 [1002/5b70] enabled PCI: 02:08.0 [1002/5b60] enabled PCI: 02:08.1 [1002/5b70] enabled PCI: 02:09.0 [1002/5b60] enabled PCI: 02:09.1 [1002/5b70] enabled PCI: 02:0a.0 [1002/5b60] enabled PCI: 02:0a.1 [1002/5b70] enabled PCI: 02:0b.0 [1002/5b60] enabled PCI: 02:0b.1 [1002/5b70] enabled PCI: 02:0c.0 [1002/5b60] enabled PCI: 02:0c.1 [1002/5b70] enabled PCI: 02:0d.0 [1002/5b60] enabled PCI: 02:0d.1 [1002/5b70] enabled PCI: 02:0e.0 [1002/5b60] enabled PCI: 02:0e.1 [1002/5b70] enabled PCI: 02:0f.0 [1002/5b60] enabled PCI: 02:0f.1 [1002/5b70] enabled PCI: 02:10.0 [1002/5b60] enabled PCI: 02:10.1 [1002/5b70] enabled PCI: 02:11.0 [1002/5b60] enabled PCI: 02:11.1 [1002/5b70] enabled PCI: 02:12.0 [1002/5b60] enabled PCI: 02:12.1 [1002/5b70] enabled PCI: 02:13.0 [1002/5b60] enabled PCI: 02:13.1 [1002/5b70] enabled PCI: 02:14.0 [1002/5b60] enabled PCI: 02:14.1 [1002/5b70] enabled PCI: 02:15.0 [1002/5b60] enabled PCI: 02:15.1 [1002/5b70] enabled PCI: 02:16.0 [1002/5b60] enabled PCI: 02:16.1 [1002/5b70] enabled PCI: 02:17.0 [1002/5b60] enabled PCI: 02:17.1 [1002/5b70] enabled PCI: 02:18.0 [1002/5b60] enabled PCI: 02:18.1 [1002/5b70] enabled PCI: 02:19.0 [1002/5b60] enabled PCI: 02:19.1 [1002/5b70] enabled PCI: 02:1a.0 [1002/5b60] enabled PCI: 02:1a.1 [1002/5b70] enabled PCI: 02:1b.0 [1002/5b60] enabled PCI: 02:1b.1 [1002/5b70] enabled PCI: 02:1c.0 [1002/5b60] enabled PCI: 02:1c.1 [1002/5b70] enabled PCI: 02:1d.0 [1002/5b60] enabled PCI: 02:1d.1 [1002/5b70] enabled PCI: 02:1e.0 [1002/5b60] enabled PCI: 02:1e.1 [1002/5b70] enabled PCI: 02:1f.0 [1002/5b60] enabled PCI: 02:1f.1 [1002/5b70] enabled PCI: pci_scan_bus returning with max=002 PCIEXP: tunning PCI: 02:00.0 PCIEXP: tunning PCI: 02:00.1 PCIEXP: tunning PCI: 02:01.0 PCIEXP: tunning PCI: 02:01.1 PCIEXP: tunning PCI: 02:02.0 PCIEXP: tunning PCI: 02:02.1 PCIEXP: tunning PCI: 02:03.0 PCIEXP: tunning PCI: 02:03.1 PCIEXP: tunning PCI: 02:04.0 PCIEXP: tunning PCI: 02:04.1 PCIEXP: tunning PCI: 02:05.0 PCIEXP: tunning PCI: 02:05.1 PCIEXP: tunning PCI: 02:06.0 PCIEXP: tunning PCI: 02:06.1 PCIEXP: tunning PCI: 02:07.0 PCIEXP: tunning PCI: 02:07.1 PCIEXP: tunning PCI: 02:08.0 PCIEXP: tunning PCI: 02:08.1 PCIEXP: tunning PCI: 02:09.0 PCIEXP: tunning PCI: 02:09.1 PCIEXP: tunning PCI: 02:0a.0 PCIEXP: tunning PCI: 02:0a.1 PCIEXP: tunning PCI: 02:0b.0 PCIEXP: tunning PCI: 02:0b.1 PCIEXP: tunning PCI: 02:0c.0 PCIEXP: tunning PCI: 02:0c.1 PCIEXP: tunning PCI: 02:0d.0 PCIEXP: tunning PCI: 02:0d.1 PCIEXP: tunning PCI: 02:0e.0 PCIEXP: tunning PCI: 02:0e.1 PCIEXP: tunning PCI: 02:0f.0 PCIEXP: tunning PCI: 02:0f.1 PCIEXP: tunning PCI: 02:10.0 PCIEXP: tunning PCI: 02:10.1 PCIEXP: tunning PCI: 02:11.0 PCIEXP: tunning PCI: 02:11.1 PCIEXP: tunning PCI: 02:12.0 PCIEXP: tunning PCI: 02:12.1 PCIEXP: tunning PCI: 02:13.0 PCIEXP: tunning PCI: 02:13.1 PCIEXP: tunning PCI: 02:14.0 PCIEXP: tunning PCI: 02:14.1 PCIEXP: tunning PCI: 02:15.0 PCIEXP: tunning PCI: 02:15.1 PCIEXP: tunning PCI: 02:16.0 PCIEXP: tunning PCI: 02:16.1 PCIEXP: tunning PCI: 02:17.0 PCIEXP: tunning PCI: 02:17.1 PCIEXP: tunning PCI: 02:18.0 PCIEXP: tunning PCI: 02:18.1 PCIEXP: tunning PCI: 02:19.0 PCIEXP: tunning PCI: 02:19.1 PCIEXP: tunning PCI: 02:1a.0 PCIEXP: tunning PCI: 02:1a.1 PCIEXP: tunning PCI: 02:1b.0 PCIEXP: tunning PCI: 02:1b.1 PCIEXP: tunning PCI: 02:1c.0 PCIEXP: tunning PCI: 02:1c.1 PCIEXP: tunning PCI: 02:1d.0 PCIEXP: tunning PCI: 02:1d.1 PCIEXP: tunning PCI: 02:1e.0 PCIEXP: tunning PCI: 02:1e.1 PCIEXP: tunning PCI: 02:1f.0 PCIEXP: tunning PCI: 02:1f.1 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [11ab/4362] enabled PCI: 05:01.0 [11ab/4362] enabled PCI: 05:02.0 [11ab/4362] enabled PCI: 05:03.0 [11ab/4362] enabled PCI: 05:04.0 [11ab/4362] enabled PCI: 05:05.0 [11ab/4362] enabled PCI: 05:06.0 [11ab/4362] enabled PCI: 05:07.0 [11ab/4362] enabled PCI: 05:08.0 [11ab/4362] enabled PCI: 05:09.0 [11ab/4362] enabled PCI: 05:0a.0 [11ab/4362] enabled PCI: 05:0b.0 [11ab/4362] enabled PCI: 05:0c.0 [11ab/4362] enabled PCI: 05:0d.0 [11ab/4362] enabled PCI: 05:0e.0 [11ab/4362] enabled PCI: 05:0f.0 [11ab/4362] enabled PCI: 05:10.0 [11ab/4362] enabled PCI: 05:11.0 [11ab/4362] enabled PCI: 05:12.0 [11ab/4362] enabled PCI: 05:13.0 [11ab/4362] enabled PCI: 05:14.0 [11ab/4362] enabled PCI: 05:15.0 [11ab/4362] enabled PCI: 05:16.0 [11ab/4362] enabled PCI: 05:17.0 [11ab/4362] enabled PCI: 05:18.0 [11ab/4362] enabled PCI: 05:19.0 [11ab/4362] enabled PCI: 05:1a.0 [11ab/4362] enabled PCI: 05:1b.0 [11ab/4362] enabled PCI: 05:1c.0 [11ab/4362] enabled PCI: 05:1d.0 [11ab/4362] enabled PCI: 05:1e.0 [11ab/4362] enabled PCI: 05:1f.0 [11ab/4362] enabled PCI: pci_scan_bus returning with max=005 PCIEXP: tunning PCI: 05:00.0 PCIEXP: tunning PCI: 05:01.0 PCIEXP: tunning PCI: 05:02.0 PCIEXP: tunning PCI: 05:03.0 PCIEXP: tunning PCI: 05:04.0 PCIEXP: tunning PCI: 05:05.0 PCIEXP: tunning PCI: 05:06.0 PCIEXP: tunning PCI: 05:07.0 PCIEXP: tunning PCI: 05:08.0 PCIEXP: tunning PCI: 05:09.0 PCIEXP: tunning PCI: 05:0a.0 PCIEXP: tunning PCI: 05:0b.0 PCIEXP: tunning PCI: 05:0c.0 PCIEXP: tunning PCI: 05:0d.0 PCIEXP: tunning PCI: 05:0e.0 PCIEXP: tunning PCI: 05:0f.0 PCIEXP: tunning PCI: 05:10.0 PCIEXP: tunning PCI: 05:11.0 PCIEXP: tunning PCI: 05:12.0 PCIEXP: tunning PCI: 05:13.0 PCIEXP: tunning PCI: 05:14.0 PCIEXP: tunning PCI: 05:15.0 PCIEXP: tunning PCI: 05:16.0 PCIEXP: tunning PCI: 05:17.0 PCIEXP: tunning PCI: 05:18.0 PCIEXP: tunning PCI: 05:19.0 PCIEXP: tunning PCI: 05:1a.0 PCIEXP: tunning PCI: 05:1b.0 PCIEXP: tunning PCI: 05:1c.0 PCIEXP: tunning PCI: 05:1d.0 PCIEXP: tunning PCI: 05:1e.0 PCIEXP: tunning PCI: 05:1f.0 PCI: pci_scan_bus for bus 06 PCI: pci_scan_bus returning with max=006 PCI: pci_scan_bus returning with max=006 PCI: pci_scan_bus returning with max=006 done Allocating resources... Reading resources... PCI: 00:01.0 1c <- [0x000000f000 - 0x000000efff] bus 01 io PCI: 00:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem PCI: 00:01.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 01 mem PCI: 00:03.0 1c <- [0x000000f000 - 0x000000efff] bus 03 io PCI: 00:03.0 24 <- [0x0ffff00000 - 0x0fffefffff] bus 03 prefmem PCI: 00:03.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 03 mem PCI: 00:03.1 1c <- [0x000000f000 - 0x000000efff] bus 04 io PCI: 00:03.1 24 <- [0x0ffff00000 - 0x0fffefffff] bus 04 prefmem PCI: 00:03.1 20 <- [0x00fff00000 - 0x00ffefffff] bus 04 mem PCI: 00:03.2 24 <- [0x0ffff00000 - 0x0fffefffff] bus 05 prefmem PCI: 00:03.3 1c <- [0x000000f000 - 0x000000efff] bus 06 io PCI: 00:03.3 24 <- [0x0ffff00000 - 0x0fffefffff] bus 06 prefmem PCI: 00:03.3 20 <- [0x00fff00000 - 0x00ffefffff] bus 06 mem Done reading resources. Allocating VGA resource PCI: 02:1f.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 1b0 <- [0x00f0000000 - 0x00f7ffffff] prefmem <node 0 link 0> PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fcdfffff] mem <node 0 link 0> PCI: 00:00.0 10 <- [0x00f0000000 - 0x00f7ffffff] prefmem PCI: 00:02.0 1c <- [0x0000000000 - 0x0000007fff] bus 02 io ERROR: PCI: 00:02.0 24 prefmem size: 0x0100000000 not assigned PCI: 00:02.0 20 <- [0x00fc000000 - 0x00fc7fffff] bus 02 mem PCI: 02:00.0 10 <- [0x0000000000 - 0x0007ffffff] prefmem PCI: 02:00.0 14 <- [0x0000000000 - 0x00000000ff] io PCI: 02:00.0 18 <- [0x00fc400000 - 0x00fc40ffff] mem PCI: 02:00.0 30 <- [0x00fc000000 - 0x00fc01ffff] romem PCI: 02:00.1 10 <- [0x00fc410000 - 0x00fc41ffff] mem PCI: 02:01.0 10 <- [0x0008000000 - 0x000fffffff] prefmem PCI: 02:01.0 14 <- [0x0000000400 - 0x00000004ff] io PCI: 02:01.0 18 <- [0x00fc420000 - 0x00fc42ffff] mem PCI: 02:01.0 30 <- [0x00fc020000 - 0x00fc03ffff] romem PCI: 02:01.1 10 <- [0x00fc430000 - 0x00fc43ffff] mem PCI: 02:02.0 10 <- [0x0010000000 - 0x0017ffffff] prefmem PCI: 02:02.0 14 <- [0x0000000800 - 0x00000008ff] io PCI: 02:02.0 18 <- [0x00fc440000 - 0x00fc44ffff] mem PCI: 02:02.0 30 <- [0x00fc040000 - 0x00fc05ffff] romem PCI: 02:02.1 10 <- [0x00fc450000 - 0x00fc45ffff] mem PCI: 02:03.0 10 <- [0x0018000000 - 0x001fffffff] prefmem PCI: 02:03.0 14 <- [0x0000000c00 - 0x0000000cff] io PCI: 02:03.0 18 <- [0x00fc460000 - 0x00fc46ffff] mem PCI: 02:03.0 30 <- [0x00fc060000 - 0x00fc07ffff] romem PCI: 02:03.1 10 <- [0x00fc470000 - 0x00fc47ffff] mem PCI: 02:04.0 10 <- [0x0020000000 - 0x0027ffffff] prefmem PCI: 02:04.0 14 <- [0x0000001000 - 0x00000010ff] io PCI: 02:04.0 18 <- [0x00fc480000 - 0x00fc48ffff] mem PCI: 02:04.0 30 <- [0x00fc080000 - 0x00fc09ffff] romem PCI: 02:04.1 10 <- [0x00fc490000 - 0x00fc49ffff] mem PCI: 02:05.0 10 <- [0x0028000000 - 0x002fffffff] prefmem PCI: 02:05.0 14 <- [0x0000001400 - 0x00000014ff] io PCI: 02:05.0 18 <- [0x00fc4a0000 - 0x00fc4affff] mem PCI: 02:05.0 30 <- [0x00fc0a0000 - 0x00fc0bffff] romem PCI: 02:05.1 10 <- [0x00fc4b0000 - 0x00fc4bffff] mem PCI: 02:06.0 10 <- [0x0030000000 - 0x0037ffffff] prefmem PCI: 02:06.0 14 <- [0x0000001800 - 0x00000018ff] io PCI: 02:06.0 18 <- [0x00fc4c0000 - 0x00fc4cffff] mem PCI: 02:06.0 30 <- [0x00fc0c0000 - 0x00fc0dffff] romem PCI: 02:06.1 10 <- [0x00fc4d0000 - 0x00fc4dffff] mem PCI: 02:07.0 10 <- [0x0038000000 - 0x003fffffff] prefmem PCI: 02:07.0 14 <- [0x0000001c00 - 0x0000001cff] io PCI: 02:07.0 18 <- [0x00fc4e0000 - 0x00fc4effff] mem PCI: 02:07.0 30 <- [0x00fc0e0000 - 0x00fc0fffff] romem PCI: 02:07.1 10 <- [0x00fc4f0000 - 0x00fc4fffff] mem PCI: 02:08.0 10 <- [0x0040000000 - 0x0047ffffff] prefmem PCI: 02:08.0 14 <- [0x0000002000 - 0x00000020ff] io PCI: 02:08.0 18 <- [0x00fc500000 - 0x00fc50ffff] mem PCI: 02:08.0 30 <- [0x00fc100000 - 0x00fc11ffff] romem PCI: 02:08.1 10 <- [0x00fc510000 - 0x00fc51ffff] mem PCI: 02:09.0 10 <- [0x0048000000 - 0x004fffffff] prefmem PCI: 02:09.0 14 <- [0x0000002400 - 0x00000024ff] io PCI: 02:09.0 18 <- [0x00fc520000 - 0x00fc52ffff] mem PCI: 02:09.0 30 <- [0x00fc120000 - 0x00fc13ffff] romem PCI: 02:09.1 10 <- [0x00fc530000 - 0x00fc53ffff] mem PCI: 02:0a.0 10 <- [0x0050000000 - 0x0057ffffff] prefmem PCI: 02:0a.0 14 <- [0x0000002800 - 0x00000028ff] io PCI: 02:0a.0 18 <- [0x00fc540000 - 0x00fc54ffff] mem PCI: 02:0a.0 30 <- [0x00fc140000 - 0x00fc15ffff] romem PCI: 02:0a.1 10 <- [0x00fc550000 - 0x00fc55ffff] mem PCI: 02:0b.0 10 <- [0x0058000000 - 0x005fffffff] prefmem PCI: 02:0b.0 14 <- [0x0000002c00 - 0x0000002cff] io PCI: 02:0b.0 18 <- [0x00fc560000 - 0x00fc56ffff] mem PCI: 02:0b.0 30 <- [0x00fc160000 - 0x00fc17ffff] romem PCI: 02:0b.1 10 <- [0x00fc570000 - 0x00fc57ffff] mem PCI: 02:0c.0 10 <- [0x0060000000 - 0x0067ffffff] prefmem PCI: 02:0c.0 14 <- [0x0000003000 - 0x00000030ff] io PCI: 02:0c.0 18 <- [0x00fc580000 - 0x00fc58ffff] mem PCI: 02:0c.0 30 <- [0x00fc180000 - 0x00fc19ffff] romem PCI: 02:0c.1 10 <- [0x00fc590000 - 0x00fc59ffff] mem PCI: 02:0d.0 10 <- [0x0068000000 - 0x006fffffff] prefmem PCI: 02:0d.0 14 <- [0x0000003400 - 0x00000034ff] io PCI: 02:0d.0 18 <- [0x00fc5a0000 - 0x00fc5affff] mem PCI: 02:0d.0 30 <- [0x00fc1a0000 - 0x00fc1bffff] romem PCI: 02:0d.1 10 <- [0x00fc5b0000 - 0x00fc5bffff] mem PCI: 02:0e.0 10 <- [0x0070000000 - 0x0077ffffff] prefmem PCI: 02:0e.0 14 <- [0x0000003800 - 0x00000038ff] io PCI: 02:0e.0 18 <- [0x00fc5c0000 - 0x00fc5cffff] mem PCI: 02:0e.0 30 <- [0x00fc1c0000 - 0x00fc1dffff] romem PCI: 02:0e.1 10 <- [0x00fc5d0000 - 0x00fc5dffff] mem PCI: 02:0f.0 10 <- [0x0078000000 - 0x007fffffff] prefmem PCI: 02:0f.0 14 <- [0x0000003c00 - 0x0000003cff] io PCI: 02:0f.0 18 <- [0x00fc5e0000 - 0x00fc5effff] mem PCI: 02:0f.0 30 <- [0x00fc1e0000 - 0x00fc1fffff] romem PCI: 02:0f.1 10 <- [0x00fc5f0000 - 0x00fc5fffff] mem PCI: 02:10.0 10 <- [0x0080000000 - 0x0087ffffff] prefmem PCI: 02:10.0 14 <- [0x0000004000 - 0x00000040ff] io PCI: 02:10.0 18 <- [0x00fc600000 - 0x00fc60ffff] mem PCI: 02:10.0 30 <- [0x00fc200000 - 0x00fc21ffff] romem PCI: 02:10.1 10 <- [0x00fc610000 - 0x00fc61ffff] mem PCI: 02:11.0 10 <- [0x0088000000 - 0x008fffffff] prefmem PCI: 02:11.0 14 <- [0x0000004400 - 0x00000044ff] io PCI: 02:11.0 18 <- [0x00fc620000 - 0x00fc62ffff] mem PCI: 02:11.0 30 <- [0x00fc220000 - 0x00fc23ffff] romem PCI: 02:11.1 10 <- [0x00fc630000 - 0x00fc63ffff] mem PCI: 02:12.0 10 <- [0x0090000000 - 0x0097ffffff] prefmem PCI: 02:12.0 14 <- [0x0000004800 - 0x00000048ff] io PCI: 02:12.0 18 <- [0x00fc640000 - 0x00fc64ffff] mem PCI: 02:12.0 30 <- [0x00fc240000 - 0x00fc25ffff] romem PCI: 02:12.1 10 <- [0x00fc650000 - 0x00fc65ffff] mem PCI: 02:13.0 10 <- [0x0098000000 - 0x009fffffff] prefmem PCI: 02:13.0 14 <- [0x0000004c00 - 0x0000004cff] io PCI: 02:13.0 18 <- [0x00fc660000 - 0x00fc66ffff] mem PCI: 02:13.0 30 <- [0x00fc260000 - 0x00fc27ffff] romem PCI: 02:13.1 10 <- [0x00fc670000 - 0x00fc67ffff] mem PCI: 02:14.0 10 <- [0x00a0000000 - 0x00a7ffffff] prefmem PCI: 02:14.0 14 <- [0x0000005000 - 0x00000050ff] io PCI: 02:14.0 18 <- [0x00fc680000 - 0x00fc68ffff] mem PCI: 02:14.0 30 <- [0x00fc280000 - 0x00fc29ffff] romem PCI: 02:14.1 10 <- [0x00fc690000 - 0x00fc69ffff] mem PCI: 02:15.0 10 <- [0x00a8000000 - 0x00afffffff] prefmem PCI: 02:15.0 14 <- [0x0000005400 - 0x00000054ff] io PCI: 02:15.0 18 <- [0x00fc6a0000 - 0x00fc6affff] mem PCI: 02:15.0 30 <- [0x00fc2a0000 - 0x00fc2bffff] romem PCI: 02:15.1 10 <- [0x00fc6b0000 - 0x00fc6bffff] mem PCI: 02:16.0 10 <- [0x00b0000000 - 0x00b7ffffff] prefmem PCI: 02:16.0 14 <- [0x0000005800 - 0x00000058ff] io PCI: 02:16.0 18 <- [0x00fc6c0000 - 0x00fc6cffff] mem PCI: 02:16.0 30 <- [0x00fc2c0000 - 0x00fc2dffff] romem PCI: 02:16.1 10 <- [0x00fc6d0000 - 0x00fc6dffff] mem PCI: 02:17.0 10 <- [0x00b8000000 - 0x00bfffffff] prefmem PCI: 02:17.0 14 <- [0x0000005c00 - 0x0000005cff] io PCI: 02:17.0 18 <- [0x00fc6e0000 - 0x00fc6effff] mem PCI: 02:17.0 30 <- [0x00fc2e0000 - 0x00fc2fffff] romem PCI: 02:17.1 10 <- [0x00fc6f0000 - 0x00fc6fffff] mem PCI: 02:18.0 10 <- [0x00c0000000 - 0x00c7ffffff] prefmem PCI: 02:18.0 14 <- [0x0000006000 - 0x00000060ff] io PCI: 02:18.0 18 <- [0x00fc700000 - 0x00fc70ffff] mem PCI: 02:18.0 30 <- [0x00fc300000 - 0x00fc31ffff] romem PCI: 02:18.1 10 <- [0x00fc710000 - 0x00fc71ffff] mem PCI: 02:19.0 10 <- [0x00c8000000 - 0x00cfffffff] prefmem PCI: 02:19.0 14 <- [0x0000006400 - 0x00000064ff] io PCI: 02:19.0 18 <- [0x00fc720000 - 0x00fc72ffff] mem PCI: 02:19.0 30 <- [0x00fc320000 - 0x00fc33ffff] romem PCI: 02:19.1 10 <- [0x00fc730000 - 0x00fc73ffff] mem PCI: 02:1a.0 10 <- [0x00d0000000 - 0x00d7ffffff] prefmem PCI: 02:1a.0 14 <- [0x0000006800 - 0x00000068ff] io PCI: 02:1a.0 18 <- [0x00fc740000 - 0x00fc74ffff] mem PCI: 02:1a.0 30 <- [0x00fc340000 - 0x00fc35ffff] romem PCI: 02:1a.1 10 <- [0x00fc750000 - 0x00fc75ffff] mem PCI: 02:1b.0 10 <- [0x00d8000000 - 0x00dfffffff] prefmem PCI: 02:1b.0 14 <- [0x0000006c00 - 0x0000006cff] io PCI: 02:1b.0 18 <- [0x00fc760000 - 0x00fc76ffff] mem PCI: 02:1b.0 30 <- [0x00fc360000 - 0x00fc37ffff] romem PCI: 02:1b.1 10 <- [0x00fc770000 - 0x00fc77ffff] mem PCI: 02:1c.0 10 <- [0x00e0000000 - 0x00e7ffffff] prefmem PCI: 02:1c.0 14 <- [0x0000007000 - 0x00000070ff] io PCI: 02:1c.0 18 <- [0x00fc780000 - 0x00fc78ffff] mem PCI: 02:1c.0 30 <- [0x00fc380000 - 0x00fc39ffff] romem PCI: 02:1c.1 10 <- [0x00fc790000 - 0x00fc79ffff] mem PCI: 02:1d.0 10 <- [0x00e8000000 - 0x00efffffff] prefmem PCI: 02:1d.0 14 <- [0x0000007400 - 0x00000074ff] io PCI: 02:1d.0 18 <- [0x00fc7a0000 - 0x00fc7affff] mem PCI: 02:1d.0 30 <- [0x00fc3a0000 - 0x00fc3bffff] romem PCI: 02:1d.1 10 <- [0x00fc7b0000 - 0x00fc7bffff] mem PCI: 02:1e.0 10 <- [0x00f0000000 - 0x00f7ffffff] prefmem PCI: 02:1e.0 14 <- [0x0000007800 - 0x00000078ff] io PCI: 02:1e.0 18 <- [0x00fc7c0000 - 0x00fc7cffff] mem PCI: 02:1e.0 30 <- [0x00fc3c0000 - 0x00fc3dffff] romem PCI: 02:1e.1 10 <- [0x00fc7d0000 - 0x00fc7dffff] mem PCI: 02:1f.0 10 <- [0x00f8000000 - 0x00ffffffff] prefmem PCI: 02:1f.0 14 <- [0x0000007c00 - 0x0000007cff] io PCI: 02:1f.0 18 <- [0x00fc7e0000 - 0x00fc7effff] mem PCI: 02:1f.0 30 <- [0x00fc3e0000 - 0x00fc3fffff] romem PCI: 02:1f.1 10 <- [0x00fc7f0000 - 0x00fc7fffff] mem PCI: 00:03.2 1c <- [0x0000008000 - 0x000000ffff] bus 05 io PCI: 00:03.2 20 <- [0x00fc800000 - 0x00fccfffff] bus 05 mem PCI: 05:00.0 10 <- [0x00fcc00000 - 0x00fcc03fff] mem64 PCI: 05:00.0 18 <- [0x0000008000 - 0x00000080ff] io PCI: 05:00.0 30 <- [0x00fc800000 - 0x00fc81ffff] romem PCI: 05:01.0 10 <- [0x00fcc04000 - 0x00fcc07fff] mem64 PCI: 05:01.0 18 <- [0x0000008400 - 0x00000084ff] io PCI: 05:01.0 30 <- [0x00fc820000 - 0x00fc83ffff] romem PCI: 05:02.0 10 <- [0x00fcc08000 - 0x00fcc0bfff] mem64 PCI: 05:02.0 18 <- [0x0000008800 - 0x00000088ff] io PCI: 05:02.0 30 <- [0x00fc840000 - 0x00fc85ffff] romem PCI: 05:03.0 10 <- [0x00fcc0c000 - 0x00fcc0ffff] mem64 PCI: 05:03.0 18 <- [0x0000008c00 - 0x0000008cff] io PCI: 05:03.0 30 <- [0x00fc860000 - 0x00fc87ffff] romem PCI: 05:04.0 10 <- [0x00fcc10000 - 0x00fcc13fff] mem64 PCI: 05:04.0 18 <- [0x0000009000 - 0x00000090ff] io PCI: 05:04.0 30 <- [0x00fc880000 - 0x00fc89ffff] romem PCI: 05:05.0 10 <- [0x00fcc14000 - 0x00fcc17fff] mem64 PCI: 05:05.0 18 <- [0x0000009400 - 0x00000094ff] io PCI: 05:05.0 30 <- [0x00fc8a0000 - 0x00fc8bffff] romem PCI: 05:06.0 10 <- [0x00fcc18000 - 0x00fcc1bfff] mem64 PCI: 05:06.0 18 <- [0x0000009800 - 0x00000098ff] io PCI: 05:06.0 30 <- [0x00fc8c0000 - 0x00fc8dffff] romem PCI: 05:07.0 10 <- [0x00fcc1c000 - 0x00fcc1ffff] mem64 PCI: 05:07.0 18 <- [0x0000009c00 - 0x0000009cff] io PCI: 05:07.0 30 <- [0x00fc8e0000 - 0x00fc8fffff] romem PCI: 05:08.0 10 <- [0x00fcc20000 - 0x00fcc23fff] mem64 PCI: 05:08.0 18 <- [0x000000a000 - 0x000000a0ff] io PCI: 05:08.0 30 <- [0x00fc900000 - 0x00fc91ffff] romem PCI: 05:09.0 10 <- [0x00fcc24000 - 0x00fcc27fff] mem64 PCI: 05:09.0 18 <- [0x000000a400 - 0x000000a4ff] io PCI: 05:09.0 30 <- [0x00fc920000 - 0x00fc93ffff] romem PCI: 05:0a.0 10 <- [0x00fcc28000 - 0x00fcc2bfff] mem64 PCI: 05:0a.0 18 <- [0x000000a800 - 0x000000a8ff] io PCI: 05:0a.0 30 <- [0x00fc940000 - 0x00fc95ffff] romem PCI: 05:0b.0 10 <- [0x00fcc2c000 - 0x00fcc2ffff] mem64 PCI: 05:0b.0 18 <- [0x000000ac00 - 0x000000acff] io PCI: 05:0b.0 30 <- [0x00fc960000 - 0x00fc97ffff] romem PCI: 05:0c.0 10 <- [0x00fcc30000 - 0x00fcc33fff] mem64 PCI: 05:0c.0 18 <- [0x000000b000 - 0x000000b0ff] io PCI: 05:0c.0 30 <- [0x00fc980000 - 0x00fc99ffff] romem PCI: 05:0d.0 10 <- [0x00fcc34000 - 0x00fcc37fff] mem64 PCI: 05:0d.0 18 <- [0x000000b400 - 0x000000b4ff] io PCI: 05:0d.0 30 <- [0x00fc9a0000 - 0x00fc9bffff] romem PCI: 05:0e.0 10 <- [0x00fcc38000 - 0x00fcc3bfff] mem64 PCI: 05:0e.0 18 <- [0x000000b800 - 0x000000b8ff] io PCI: 05:0e.0 30 <- [0x00fc9c0000 - 0x00fc9dffff] romem PCI: 05:0f.0 10 <- [0x00fcc3c000 - 0x00fcc3ffff] mem64 PCI: 05:0f.0 18 <- [0x000000bc00 - 0x000000bcff] io PCI: 05:0f.0 30 <- [0x00fc9e0000 - 0x00fc9fffff] romem PCI: 05:10.0 10 <- [0x00fcc40000 - 0x00fcc43fff] mem64 PCI: 05:10.0 18 <- [0x000000c000 - 0x000000c0ff] io PCI: 05:10.0 30 <- [0x00fca00000 - 0x00fca1ffff] romem PCI: 05:11.0 10 <- [0x00fcc44000 - 0x00fcc47fff] mem64 PCI: 05:11.0 18 <- [0x000000c400 - 0x000000c4ff] io PCI: 05:11.0 30 <- [0x00fca20000 - 0x00fca3ffff] romem PCI: 05:12.0 10 <- [0x00fcc48000 - 0x00fcc4bfff] mem64 PCI: 05:12.0 18 <- [0x000000c800 - 0x000000c8ff] io PCI: 05:12.0 30 <- [0x00fca40000 - 0x00fca5ffff] romem PCI: 05:13.0 10 <- [0x00fcc4c000 - 0x00fcc4ffff] mem64 PCI: 05:13.0 18 <- [0x000000cc00 - 0x000000ccff] io PCI: 05:13.0 30 <- [0x00fca60000 - 0x00fca7ffff] romem PCI: 05:14.0 10 <- [0x00fcc50000 - 0x00fcc53fff] mem64 PCI: 05:14.0 18 <- [0x000000d000 - 0x000000d0ff] io PCI: 05:14.0 30 <- [0x00fca80000 - 0x00fca9ffff] romem PCI: 05:15.0 10 <- [0x00fcc54000 - 0x00fcc57fff] mem64 PCI: 05:15.0 18 <- [0x000000d400 - 0x000000d4ff] io PCI: 05:15.0 30 <- [0x00fcaa0000 - 0x00fcabffff] romem PCI: 05:16.0 10 <- [0x00fcc58000 - 0x00fcc5bfff] mem64 PCI: 05:16.0 18 <- [0x000000d800 - 0x000000d8ff] io PCI: 05:16.0 30 <- [0x00fcac0000 - 0x00fcadffff] romem PCI: 05:17.0 10 <- [0x00fcc5c000 - 0x00fcc5ffff] mem64 PCI: 05:17.0 18 <- [0x000000dc00 - 0x000000dcff] io PCI: 05:17.0 30 <- [0x00fcae0000 - 0x00fcafffff] romem PCI: 05:18.0 10 <- [0x00fcc60000 - 0x00fcc63fff] mem64 PCI: 05:18.0 18 <- [0x000000e000 - 0x000000e0ff] io PCI: 05:18.0 30 <- [0x00fcb00000 - 0x00fcb1ffff] romem PCI: 05:19.0 10 <- [0x00fcc64000 - 0x00fcc67fff] mem64 PCI: 05:19.0 18 <- [0x000000e400 - 0x000000e4ff] io PCI: 05:19.0 30 <- [0x00fcb20000 - 0x00fcb3ffff] romem PCI: 05:1a.0 10 <- [0x00fcc68000 - 0x00fcc6bfff] mem64 PCI: 05:1a.0 18 <- [0x000000e800 - 0x000000e8ff] io PCI: 05:1a.0 30 <- [0x00fcb40000 - 0x00fcb5ffff] romem PCI: 05:1b.0 10 <- [0x00fcc6c000 - 0x00fcc6ffff] mem64 PCI: 05:1b.0 18 <- [0x000000ec00 - 0x000000ecff] io PCI: 05:1b.0 30 <- [0x00fcb60000 - 0x00fcb7ffff] romem PCI: 05:1c.0 10 <- [0x00fcc70000 - 0x00fcc73fff] mem64 PCI: 05:1c.0 18 <- [0x000000f000 - 0x000000f0ff] io PCI: 05:1c.0 30 <- [0x00fcb80000 - 0x00fcb9ffff] romem PCI: 05:1d.0 10 <- [0x00fcc74000 - 0x00fcc77fff] mem64 PCI: 05:1d.0 18 <- [0x000000f400 - 0x000000f4ff] io PCI: 05:1d.0 30 <- [0x00fcba0000 - 0x00fcbbffff] romem PCI: 05:1e.0 10 <- [0x00fcc78000 - 0x00fcc7bfff] mem64 PCI: 05:1e.0 18 <- [0x000000f800 - 0x000000f8ff] io PCI: 05:1e.0 30 <- [0x00fcbc0000 - 0x00fcbdffff] romem PCI: 05:1f.0 10 <- [0x00fcc7c000 - 0x00fcc7ffff] mem64 PCI: 05:1f.0 18 <- [0x000000fc00 - 0x000000fcff] io PCI: 05:1f.0 30 <- [0x00fcbe0000 - 0x00fcbfffff] romem ERROR: PCI: 00:0b.0 10 io size: 0x0000000100 not assigned PCI: 00:0b.0 14 <- [0x00fcd10000 - 0x00fcd100ff] mem PCI: 00:0b.0 30 <- [0x00fcd00000 - 0x00fcd0ffff] romem ERROR: PCI: 00:0f.0 10 io size: 0x0000000008 not assigned ERROR: PCI: 00:0f.0 14 io size: 0x0000000004 not assigned ERROR: PCI: 00:0f.0 18 io size: 0x0000000008 not assigned ERROR: PCI: 00:0f.0 1c io size: 0x0000000004 not assigned ERROR: PCI: 00:0f.0 20 io size: 0x0000000010 not assigned ERROR: PCI: 00:0f.0 24 io size: 0x0000000100 not assigned ERROR: PCI: 00:0f.1 20 io size: 0x0000000010 not assigned ERROR: PCI: 00:10.0 20 io size: 0x0000000020 not assigned ERROR: PCI: 00:10.1 20 io size: 0x0000000020 not assigned ERROR: PCI: 00:10.2 20 io size: 0x0000000020 not assigned ERROR: PCI: 00:10.3 20 io size: 0x0000000020 not assigned PCI: 00:10.4 10 <- [0x00fcd11000 - 0x00fcd110ff] mem PCI: 00:10.5 10 <- [0x00fcd12000 - 0x00fcd120ff] mem ERROR: PCI: 00:11.5 10 io size: 0x0000000100 not assigned ERROR: PCI: 00:11.6 10 io size: 0x0000000100 not assigned ERROR: PCI: 00:12.0 10 io size: 0x0000000100 not assigned PCI: 00:12.0 14 <- [0x00fcd13000 - 0x00fcd130ff] mem PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] mem <gart> Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 140 PCI: 00:00.0 subsystem <- 1462/9282 PCI: 00:00.0 cmd <- 146 PCI: 00:00.1 cmd <- 146 PCI: 00:00.2 cmd <- 146 PCI: 00:00.3 cmd <- 146 PCI: 00:00.4 cmd <- 146 PCI: 00:00.5 cmd <- 146 PCI: 00:00.7 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 147 PCI: 00:02.0 bridge ctrl <- 000b PCI: 00:02.0 cmd <- 147

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coreboot April 2007