Hello all,
Flashrom works. Thanks to Corey SMBus code, I managed to go quite far away
ending with:
Unbuffered Dimms not supported on Opteron
I have Opteron 144 in 939. Edgecase told me to continue with just one DIMM, so I
moved on. Now I'm struggling with Config.lb
Left over static devices Check your config.lb
I really don't know what should I put in. I'm attaching a Config.lb lspci and
capture from Linuxbios output. Most recent capture in done with attached
Config.lb. Second back is with most commented back in.
Any pointers what above message means and how to fix it are really appreciated.
Thanks,
Rudolf
##
## This file is part of the LinuxBIOS project.
##
## Copyright (C) 2006 AMD
## Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD.
##
## Copyright (C) 2006 MSI
## Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/ati/ragexl
#needed by irq_tables and mptable and acpi_tables
##if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
##
##mainboardinit southbridge/nvidia/mcp55/id.inc
##ldscript /southbridge/via/vt8237/id.lds
##
## ROMSTRAP table for MCP55
##
##if USE_FALLBACK_IMAGE
## mainboardinit southbridge/nvidia/mcp55/romstrap.inc
## ldscript /southbridge/nvidia/mcp55/romstrap.lds
##end
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_939
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/via/vt8237r
register "enable_native_ide" = "0"
#device pci 0.0 on end # HT
#device pci 0.1 on end # ??
#device pci 0.2 on end # ??
#device pci 0.3 on end # ??
#device pci 0.4 on end # ??
#device pci 0.5 on end # APIC
#device pci 0.6 off end # ??
#device pci 0.7 on end # ??
#device pci 1.0 on end # VT8237 PCI bridge [K8T800/K8T890 South]
#device pci 2.0 on end # K8T890 PCI to PCI Bridge Controller PCI-X 16?
#device pci 3.0 on end # Bridge to 03-03
#device pci 3.1 on end # Bridge to 04-04
## device pci 3.2 on
## device pci 0.0 on #onboard Marwell
## end
##
## end # Bridge to 05-05
#device pci 3.3 on end # Bridge to 06-06
#device pci f.0 on end # SATA
device pci f.1 on end # IDE
#device pci 10.0 on end # USB
#device pci 10.1 on end # USB
#device pci 10.2 on end # USB
#device pci 10.4 on end # USB 2.0
#device pci 10.5 on end # USB 2.0
device pci 11.0 on # LPC
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end
end
chip superio/winbond/w83627ehg
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 off #keyb OFF
end
device pnp 2e.6 off # SERIAL_FALSH
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
# io 0x60 = 0x220
# io 0x62 = 0x300
# irq 0x70 = a
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 0x30 0x9
#GPIO 5 and 2 active????
#0xe0 = de
#0xe1 = 01
#0xe2 = 00
#0xe3 = 03
#0xe4 = a4
#0xe5 = 00
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 0
end
end #end SIO
end
#device pci 11.5 on end # AC97
#device pci 11.6 on end # AC97 modem
#device pci 12.0 off # VIA LAN
end
end # device pci 18.0
device pci 18.0 on end # Link 1
# device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end #mc0
end # pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end
# device pnp 0.1 off end
# device pnp 0.2 off end
# device pnp 0.3 off end
# device pnp 0.4 off end
# device pnp 0.5 on end
# end
end # root_complex
00:00.0 Host bridge: VIA Technologies, Inc. K8T890 Host Bridge
00:00.1 Host bridge: VIA Technologies, Inc. K8T890 Host Bridge
00:00.2 Host bridge: VIA Technologies, Inc. K8T890 Host Bridge
00:00.3 Host bridge: VIA Technologies, Inc. K8T890 Host Bridge
00:00.4 Host bridge: VIA Technologies, Inc. K8T890 Host Bridge
00:00.5 PIC: VIA Technologies, Inc. K8T890 I/O APIC Interrupt Controller
00:00.7 Host bridge: VIA Technologies, Inc. K8T890 Host Bridge
00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI bridge [K8T800/K8T890 South]
00:02.0 PCI bridge: VIA Technologies, Inc. K8T890 PCI to PCI Bridge Controller
00:03.0 PCI bridge: VIA Technologies, Inc. K8T890 PCI to PCI Bridge Controller
00:03.1 PCI bridge: VIA Technologies, Inc. K8T890 PCI to PCI Bridge Controller
00:03.2 PCI bridge: VIA Technologies, Inc. K8T890 PCI to PCI Bridge Controller
00:03.3 PCI bridge: VIA Technologies, Inc. K8T890 PCI to PCI Bridge Controller
00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
00:0f.0 RAID bus controller: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller (rev 80)
00:0f.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81)
00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81)
00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81)
00:10.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81)
00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86)
00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South]
00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller (rev 60)
00:11.6 Communication controller: VIA Technologies, Inc. AC'97 Modem Controller (rev 80)
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control
02:00.0 VGA compatible controller: ATI Technologies Inc RV370 5B60 [Radeon X300 (PCIE)]
02:00.1 Display controller: ATI Technologies Inc RV370 [Radeon X300SE]
05:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8053 PCI-E Gigabit Ethernet Controller (rev 19)
