coreboot March 2007

coreboot@coreboot.org

118 participants
226 discussions

[LinuxBIOS] PLCC clip on base
by Stefan Reinauer 14 Mar '07

14 Mar '07

Ironwood Electronics has these nice parts. Not sure which one is suited best for a "remote bios flasher". http://www.ironwoodelectronics.com/catalog/Content/Drawings/CL-PLCC32-M-01D… http://www.ironwoodelectronics.com/catalog/Content/Drawings/CL-PLCC32-S-01D… http://www.ironwoodelectronics.com/catalog/Content/Drawings/CL-PLCC032-T-01… Can they be used at all? Or will applying power to the pins do weird things to the board (missing pull up resistors or something?) -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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[LinuxBIOS] Please explain why is some hardware not supported even though it runs fine in linux
by Michal Pomorski 14 Mar '07

14 Mar '07

Take for instance nForce2 chipset and please correct me if i am wrong. Linux have full hardware support for it right ? (it should since i use one) Linux doesnt use bios functions because it controlls all the hardware on the motherboard right? So if there is a way for linux to controll the hardware why is it impossible to implement it in a free bios? What is so special about linux bios that needs special vendor support that linux os doesnt?

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[LinuxBIOS] 5 Euro flash hardware
by Quux 14 Mar '07

14 Mar '07

Ward Vandewege schrieb: > A proper programmer would be useful, but only if it can be used with free > software. There's also this rom-emulator: > > http://www.tech-tools.com/er3.htm > > Richard Smith told me that the dos-based cli software works under wine, but > it's still a proprietary thing. > http://www.loet.de/index.html > this flasher can be homebrewed at 5 euro component cost and free linux flash software is available. you can also buy a ready-made flasher. it hooks to the IDE 40-pin port. afaik the cheapest solution available w/ 32 pin plcc --Q

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[LinuxBIOS] Where to begin?
by Richard Wilson 14 Mar '07

14 Mar '07

I recently was reminded of LinuxBIOS by that /. article, and remembered how I thought it rocked back in v1 days, when I was a penniless student. Now I have a job, which equals paychecks, and more free time. I'd love to be able to contribute something to the project. Unfortunately, I'm a sysadmin, not a programmer, and barring snippets of perl to automate system tasks, I can't code for toffee. :-( Guess I'll just have to buy some hardware and be a testing monkey then :-) At the moment at work we have a Via PD10000, which we use for a bunch of quite mission-critical things. We can reboot it as often as we like, but at the moment, doing so is a PITA because it takes so long. Hmm. Wouldn't it be nice if I could boot LinuxBIOS on it... So here I am, bidding on another one on eBay, so that we can have a spare in case our mission-crit one dies. But it would be a shame for the spare to sit around doing nothing... Its worth saying at this point that I don't want to divert anyone coding actually /useful/ things, so if I have to wait around for someone to have a spare moment to give me a hand, thats fine. I'm happy to go get a chip puller, some spare bios chips, a chip programmer, etc. Just tell me where to get the right ones. If anyone wants to tell me I'm not going to do much good, that's okay. I'm buying the board as a spare anyway. If I can do some good by helping get it working under LinuxBIOS, well then that's great and where do I start... So, my question is this: Shall I go and get a POST card, a chip flasher and some spare lumps of silicon, or should I not bother? Here's hoping I can make a contribution, Dave, Sysadmin, Senokian Solutions

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[LinuxBIOS] Linux Bios
by laurent choblet 13 Mar '07

13 Mar '07

hi good work with this linux bios it's really an interresting alternative and open new perspectives on computer capacity and show that you don't need a 8gB system tu run a graphical interface Congratulation and go on Laurent CHOBLET

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[LinuxBIOS] Programming i2c
by joe＠smittys.pointclark.net 13 Mar '07

13 Mar '07

Hello, I have a question. I see in the sources there are drivers for i2c devices. What I am thinking is to write a driver to program and initialize the tv-out chip through the i2c (smbus). The tv-out chip is embedded in the board and programable through i2c. If this is possible I would need to know at what point the video bios gets initialized. And I would want to load this driver right after video bios gets initialized correct? Thoughts? Thanks - Joe

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[LinuxBIOS] Halt after entering protected mode
by Corey Osgood 13 Mar '07

13 Mar '07

This is a repost, I'm hoping some folks missed it since the last time I posted it in a patch thread. I'm having problems getting the tyan s2507 to boot into linuxbios, it's hanging with a post code of 0x10, which according to POSTCODES is after it enters protected mode. I've used outb() to determine that it's hanging before it ever gets to the cpu or mainboard initialization, but I'm having trouble tracing it back any further, because the inner workings of LB have me very much lost. I should probably mention that this is a dual p3 board, I don't know if cpu/intel/model_6xx was ever inteded to be used for SMP. I've tried this with and without smp, and even pulled one of the CPUs, and it still hangs. I've also tried with and without APIC, with no luck. I've attached my latest Config.lb and Options.lb from my s2507 folder. Please post back with any suggestions! Thanks, Corey -Corey ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = 0 end ## ## Compute the start location and size size of ## The linuxBIOS bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) ## ## Compute where this copy of linuxBIOS will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up linuxBIOS, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture ## arch i386 end ## ## Build the objects we have code for in this directory. ## driver mainboard.o #if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./failover.inc depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./auto.E depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end makerule ./auto.inc depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end ### ### O.k. We aren't just an intermediary anymore! ### ## ## Setup RAM ## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc ## ## Include the secondary Configuration files ## dir /pc80 config chip.h chip northbridge/via/vt694 device pci_domain 0 on end device apic_cluster 0 on chip cpu/intel/model_6xx device apic 0 on end end chip cpu/intel/model_6xx device apic 1 on end end end end uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER uses LINUXBIOS_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE uses HEAP_SIZE uses ROM_SIZE uses ROM_SECTION_SIZE uses ROM_IMAGE_SIZE uses ROM_SECTION_SIZE uses ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses PAYLOAD_SIZE uses _ROMBASE uses _RAMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE uses HAVE_MP_TABLE uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses SERIAL_CPU_INIT uses FAKE_SPDROM ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 ### ### Build options ### default FAKE_SPDROM=1 ## ## SMP and CPU stuffs ## default CONFIG_SMP=1 default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0 default CONFIG_IOAPIC=1 default SERIAL_CPU_INIT=0 ## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 ## ## no MP table ## default HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from linuxBIOS ## default HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=0 default IRQ_SLOT_COUNT=4 #object irq_tables.o ## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=0 ### ### LinuxBIOS layout values ### ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. default ROM_IMAGE_SIZE = 65536 #default FALLBACK_SIZE = 131072 default FALLBACK_SIZE = 262144 ## ## Use a small 8K stack ## default STACK_SIZE=0x2000 ## ## Use a small 16K heap ## default HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0 default _RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## default CROSS_COMPILE="" default CC="$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" default HOSTCC="gcc -fno-stack-protector" ## ## The Serial Console ## # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate default TTYS0_BAUD=115200 #default TTYS0_BAUD=57600 #default TTYS0_BAUD=38400 #default TTYS0_BAUD=19200 #default TTYS0_BAUD=9600 #default TTYS0_BAUD=4800 #default TTYS0_BAUD=2400 #default TTYS0_BAUD=1200 # Select the serial console base port default TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity default TTYS0_LCS=0x3 ## ### Select the linuxBIOS loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately ## CRIT 3 critical conditions ## ERR 4 error conditions ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational ## DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging default MAXIMUM_CONSOLE_LOGLEVEL=9 default CONFIG_UDELAY_TSC=1 end

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Re: [LinuxBIOS] trying to boot gigabyte m57sli-s4 / abit kn9 ultra]
by Karl Erik Asbjørnsen 12 Mar '07

12 Mar '07

I had the same noapic-problem with my abit kn9 ultra after upgrading the bios from 1.4 to 1.5 (or something like that). A few bioses later, that problem was fixed. The changelist for bios version 1.8 said "Enhanced compatibility with Linux", and after that i did'nt need the noapic parameter anymore. Anyway, I've just ordered a bios savior, so when that one arrives I could try to make linuxbios work on my board. The problem is I don't have a serial out on my computer, so how do I debug? lspci -vv attached. Superio is a Winbond W83627EHG. Flashrom seems ok after uwe added additional PCI IDs for MCP55: [root@silver flashrom]# ./flashrom Calibrating delay loop... ok No LinuxBIOS table found. Enabling flash write on NVIDIA MCP55...OK SST49LF040 found at physical address: 0xfff80000 Flash part is SST49LF040 (512 KB) OK, only ENABLING flash write, but NOT FLASHING. Karl Erik Ward Vandewege wrote: > On Mon, Mar 12, 2007 at 04:47:19PM -0400, Ward Vandewege wrote: > >> On Mon, Mar 12, 2007 at 09:42:59PM +0100, ST wrote: >> >>> Thanks for your quick answer. >>> >>>> Booting 2.6.20.1 with noapic works for me: >>>> >>> yah, but i'd really like to use both processors of this X2 ... >>> So am i right that you can't boot without the "noapic" line? >>> >> Uhm - no? >> > > Sorry, I meant 'no' to the 'use both processors' bit. > > As for booting without the noapic option, that seems to work with > 2.6.21-rc3 but not 2.6.20.1. > > Thanks, > Ward. > > 00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a1) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] #00 [fee0] 00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a2) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a2) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at fc00 [size=64] Region 4: I/O ports at 1c00 [size=64] Region 5: I/O ports at 1c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:01.2 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a2) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) (prog-if 10 [OHCI]) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at fe02f000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) (prog-if 20 [EHCI]) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 22 Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Region 4: I/O ports at f000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) (prog-if 85 [Master SecO PriO]) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 21 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at dc00 [size=16] Region 5: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) (prog-if 85 [Master SecO PriO]) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 20 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at c800 [size=16] Region 5: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00:05.2 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) (prog-if 85 [Master SecO PriO]) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin C routed to IRQ 23 Region 0: I/O ports at c400 [size=8] Region 1: I/O ports at c000 [size=4] Region 2: I/O ports at bc00 [size=8] Region 3: I/O ports at b800 [size=4] Region 4: I/O ports at b400 [size=16] Region 5: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 00009000-00009fff Memory behind bridge: fde00000-fdefffff Prefetchable memory behind bridge: ec000000-efffffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [b8] #0d [0000] Capabilities: [8c] HyperTransport: MSI Mapping 00:08.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 22 Region 0: Memory at fe02a000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b000 [size=8] Region 2: Memory at fe029000 (32-bit, non-prefetchable) [size=256] Region 3: Memory at fe028000 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Vector table: BAR=2 offset=00000000 PBA: BAR=3 offset=00000000 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [6c] HyperTransport: MSI Mapping 00:09.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) Subsystem: ABIT Computer Corp. Unknown device 1c24 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 21 Region 0: Memory at fe027000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at ac00 [size=8] Region 2: Memory at fe026000 (32-bit, non-prefetchable) [size=256] Region 3: Memory at fe025000 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Vector table: BAR=2 offset=00000000 PBA: BAR=3 offset=00000000 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [6c] HyperTransport: MSI Mapping 00:0c.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00008000-00008fff Memory behind bridge: fdd00000-fddfffff Prefetchable memory behind bridge: 00000000fdc00000-00000000fdc00000 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Address: 00000000fee00000 Data: 4039 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 256 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 3 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x4 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- Capabilities: [100] Virtual Channel 00:0d.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00007000-00007fff Memory behind bridge: fdb00000-fdbfffff Prefetchable memory behind bridge: 00000000fda00000-00000000fda00000 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Address: 00000000fee00000 Data: 4041 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 256 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 2 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x4 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- Capabilities: [100] Virtual Channel 00:0e.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 00006000-00006fff Memory behind bridge: fd900000-fd9fffff Prefetchable memory behind bridge: 00000000fd800000-00000000fd800000 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Address: 00000000fee00000 Data: 4049 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 256 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 1 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x8 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- Capabilities: [100] Virtual Channel 00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 00005000-00005fff Memory behind bridge: fa000000-fcffffff Prefetchable memory behind bridge: 00000000d0000000-00000000dff00000 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Address: 00000000fee00000 Data: 4051 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 256 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x16, ASPM L0s L1, Port 0 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk+ ExtSynch- Link: Speed 2.5Gb/s, Width x16 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- Capabilities: [100] Virtual Channel 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [f0] #0f [0010] 01:08.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) (prog-if 10 [OHCI]) Subsystem: ABIT Computer Corp. Unknown device 1c20 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (500ns min, 1000ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at fdeff000 (32-bit, non-prefetchable) [size=2K] Region 1: Memory at fdef8000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 01:09.0 Multimedia video controller: Internext Compression Inc iTVC15 MPEG-2 Encoder (rev 01) Subsystem: Hauppauge computer works Inc. WinTV PVR-350 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 128 (32000ns min, 2000ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at ec000000 (32-bit, prefetchable) [size=64M] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 05:00.0 VGA compatible controller: nVidia Corporation G70 [GeForce 7600 GS] (rev a1) (prog-if 00 [VGA]) Subsystem: Micro-Star International Co., Ltd. NX7600GS-T2D256EH Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at fa000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at fb000000 (64-bit, non-prefetchable) [size=16M] Region 5: I/O ports at 5c00 [size=128] [virtual] Expansion ROM at fc000000 [disabled] [size=128K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [78] Express Endpoint IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <256ns, L1 <4us Device: AtnBtn- AtnInd- PwrInd- Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported- Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x16, ASPM L0s L1, Port 0 Link: Latency L0s <256ns, L1 <4us Link: ASPM Disabled RCB 128 bytes CommClk+ ExtSynch- Link: Speed 2.5Gb/s, Width x16 Capabilities: [100] Virtual Channel Capabilities: [128] Power Budgeting

1 0

[LinuxBIOS] NMI debugging tool ?
by Quux 12 Mar '07

12 Mar '07

Yo! http://www.pcisig.com/reflector/msg03869.html I was thinking the same ... even though I am aware of the fact that ROM debugging is hardly possible in an early state (no RAM set up yet) I still wonder about the feasibility of a debugger in ROM. or does it not help much more than a regular Linux debugging kernel and is thus hardly worth the effort ?

2 1

[LinuxBIOS] LinuxBIOS, VMWare & CMOS
by Joe Pub 12 Mar '07

12 Mar '07

Hi All, I am getting closer to having VMWare working with a LinuxBIOS BIOS. I had an issue which I was unsure of, where certain compile options would just not work with VMWare. I have finnaly figured out why that is. By enabling CONFIG_PCI_ROM_RUN for instance, includes extra object files within the resulting binary, hence making the used part of the ROM image greater. Here lies my problem. VMWare seems to load the LinuxBIOS rom, but then overwrite the address at 0xFA000 with 8K of NVRAM data, basically overwriting portions of the LinuxBIOS code. So what I was wondering, what would be the best approach to reserve that area of memory to that it does not corrupt any of the LinuxBIOS code. Thanks guys.

5 4

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coreboot March 2007