coreboot March 2007

coreboot@coreboot.org

118 participants
226 discussions

[LinuxBIOS] setting up linuxbios?
by Craig Bane 08 Mar '07

08 Mar '07

Hi just want to clear a few things up before I try to install linuxbios onto my ecs a754 motherboard. I've done a lspci heres the output: virogenesis@localhost:~$ lspci 00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a2) 00:01.0 ISA bridge: nVidia Corporation CK804 ISA Bridge (rev a2) 00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) 00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) 00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) 00:04.0 Multimedia audio controller: nVidia Corporation CK804 AC'97 Audio Controller (rev a2) 00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2) 00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a2) 00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a2) 00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2) 00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a2) 00:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) 00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) 00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) 00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:08.0 SCSI storage controller: Adaptec AIC-7892A U160/m (rev 02) 05:00.0 VGA compatible controller: nVidia Corporation NV43 [GeForce 6600 GT] (rev a2) After linuxbios is compiled and my bios is flashed what will I need to do in order to boot a single linux distro. Thank you in advance.

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[LinuxBIOS] next meeting
by ron minnich 08 Mar '07

08 Mar '07

We talked about having the next meeting in Taiwan, but there were a number of issues. So we thought about california. I am partial to CA as I am moving there in a few weeks. I would like to propose this place: http://en.wikipedia.org/wiki/Marin_Headlands Why: it is a stunningly beatiful area, it is really hard to get it across in pictures. There is a conference center: http://www.yni.org/hi/conference/rates.php It is just north of the golden gate bridge, so it is easy to get to SF; we could have some fun excursions to SF and sausalito there is a youth hostel there, for poor students: http://www.norcalhostels.org/marin/index.html (I got the youth hostel idea from FOSDEM) If you don't like dorm accomodations, there are hotels not too far away AMD and other local employees can just drive up each day if they want So I am curious: if we have such a meeting, say, sep. 7 or so, who is interested? thanks ron

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[LinuxBIOS] Additional PCI device id's from USB Controller with Debug port capability (ICH8)
by Jochem Pouw 08 Mar '07

08 Mar '07

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 These ones i found on my "Asus P5B Deluxe WiFi/AP" Could anyone please add them to the wiki? sideshowmel:~# lspci -vs 00:1a.7 00:1a.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI #2 (rev 02) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. Unknown device 81ec Flags: bus master, medium devsel, latency 0, IRQ 18 Memory at febff400 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port sideshowmel:~# lspci -ns 00:1a.7 00:1a.7 0c03: 8086:283a (rev 02) And: sideshowmel:~# lspci -vs 00:1d.7 00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI #1 (rev 02) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. Unknown device 81ec Flags: bus master, medium devsel, latency 0, IRQ 19 Memory at febff000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port sideshowmel:~# lspci -ns 00:1d.7 00:1d.7 0c03: 8086:2836 (rev 02) Jochem Pouw ... and now with the correct sender address -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFF8D9f7C+nAGUe1kkRCM5bAKDrNmxYFTgLYxeMMJ6IBV1vvOQ0DwCeKmkS BLtlpZr4fgiZ2PiQxmuShmk= =Avlr -----END PGP SIGNATURE-----

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[LinuxBIOS] Info on my mobo
by The Digital Pioneer 08 Mar '07

08 Mar '07

Hi. The folks over at #openbios told me to send a lspci -vv and dmidecode output on here, so here I am. :) I _THINK_ I have a giovanni2 mobo (or something of that sort) but I'm not really sure. I tried to find out once, and came up with that. No clue whether it's correct or not. Feel free to ask any questions. http://thedigitalpioneer.5u.com/mobo.html -- Thanks, The Digital Pioneer

1 0

[LinuxBIOS] [PATCH] flashrom: Fix wrong VT8235 flash enable failed warning.
by Luc Verhaegen 08 Mar '07

08 Mar '07

This fixes the warning that's present for all VT8235 southbridges: ... Enabling flash write on VT8235...tried to set 0x4 to 0x14 on VT8235 failed (WARNING ONLY) ... It's bourne from misinterpreting the return value of pci_write_byte, which peculiarly returns 1 for success. Luc Verhaegen.

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[LinuxBIOS] crashfree , virtual dual BIOS - PCI expansion ROM
by Quux 07 Mar '07

07 Mar '07

my favourite has always been Elitegroup "top hat flash" - a bios saviour lookalike w/o the switch. Does it make sense to put Linux BIOS on a Ethernet NIC to avoid that soldering stuff ? take out the card and fall back to standard BIOS ? max 128 KByte possible. greetinx ! Q

3 3

[LinuxBIOS] LinuxBIOS with X Server Inside
by Alan Carvalho de Assis 07 Mar '07

07 Mar '07

Hi guys, there is LinuxBIOS running with graphic mode: http://www.youtube.com/watch?v=nuzRsXKm_NQ Thanks my friends Marcelo Barros and Fred Schaf to make the video. Dave, I will supply the video in ogg theora with better resolution after. I hope everybody enjoy it. Best regards, Alan

4 6

[LinuxBIOS] Problems with compile
by Joe Pub 07 Mar '07

07 Mar '07

Hi All, I have an issue when trying to enable the CONFIG_PCI_ROM_RUN option. The linuxrom that results when I use this option seems to be incorrect. The JMP instruction at 0xfff0 jmps to a address that has no executable machine code, just endless amounts of 0xff. If I disable CONFIG_PCI_ROM_RUN and recompile, the first JMP instruction jumps to valid code (entry16.inc). Is there something else I must do other than enable CONFIG_PCI_ROM_RUN to support running PCI option ROM's. Thanks

1 0

Re: [LinuxBIOS] Problems on Compilation with abuild
by ccases＠navista.fr 07 Mar '07

07 Mar '07

> * ccases(a)navista.fr <ccases(a)navista.fr> [070307 14:20]: >> option ROM_SIZE=(256*1024)-(128*1024)-(32*1024) >> option ROM_IMAGE_SIZE=64*1024 >> option FALLBACK_SIZE = ROM_SIZE > > This looks odd. You are trying to build an image of > 256-128-32 = 96 kb size and try to store 2 sub images of 64k each in there. I think this can't work. > > Stefan > > -- > coresystems GmbH â¢ Brahmsstr. 16 â¢ D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 â¢ Fax: +49 761 7664613 > Email: info(a)coresystems.de â¢ http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg â¢ HRB 7656 > GeschÃ¤ftsfÃ¼hrer: Stefan Reinauer â¢ Ust-IdNr.: DE245674866 > One more question: How to choose the ROM_IMAGE_SIZE ? thank's by advance Ccases

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[LinuxBIOS] ATI RS480 Support
by Guido Loupias 07 Mar '07

07 Mar '07

I have read in the archive that someone was working on ATI RS480 support for linuxbios. How is the progress on that going? Guido

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coreboot March 2007