coreboot March 2007

coreboot@coreboot.org

118 participants
226 discussions

[LinuxBIOS] trying to boot gigabyte m57sli-s4
by Ward Vandewege 19 Mar '07

19 Mar '07

Hi YH and list, I've been trying to get the the gigabyte m57sli-s4 to boot, using the code that YH sent to the list on January 19th (the code in the v2 tree does not compile yet), but I'm having some IRQ problems it seems. I see things like this in the boot log: [ 81.290497] PCI: Probing PCI hardware [ 81.295506] PCI: Unable to handle 64-bit address space for bridge 0000:00:0b.0 [ 81.303828] PCI: Unable to handle 64-bit address space for bridge 0000:00:0c.0 [ 81.312150] PCI: Unable to handle 64-bit address space for bridge 0000:00:0d.0 [ 81.320479] PCI: Unable to handle 64-bit address space for bridge 0000:00:0e.0 [ 81.328817] PCI: Unable to handle 64-bit address space for bridge 0000:00:0f.0 [ 81.337596] PCI: Using IRQ router default [10de/0370] at 0000:00:06.0 [ 81.345008] PCI: IRQ 0 for device 0000:00:06.1 doesn't match PIRQ mask - try pci=usepirqmask And a bit further: [ 81.526599] pcie_portdrv_probe->Dev[0376:10de] has invalid IRQ. Check vendor BIOS [ 81.535189] assign_interrupt_mode Found MSI capability [ 81.541136] pcie_portdrv_probe->Dev[0374:10de] has invalid IRQ. Check vendor BIOS [ 81.549747] assign_interrupt_mode Found MSI capability [ 81.555689] pcie_portdrv_probe->Dev[0374:10de] has invalid IRQ. Check vendor BIOS [ 81.564285] assign_interrupt_mode Found MSI capability [ 81.570227] pcie_portdrv_probe->Dev[0378:10de] has invalid IRQ. Check vendor BIOS [ 81.578857] assign_interrupt_mode Found MSI capability [ 81.584806] pcie_portdrv_probe->Dev[0375:10de] has invalid IRQ. Check vendor BIOS [ 81.593409] assign_interrupt_mode Found MSI capability [ 81.599350] pcie_portdrv_probe->Dev[0377:10de] has invalid IRQ. Check vendor BIOS [ 81.607949] assign_interrupt_mode Found MSI capability The interesting thing is that those pci ids don't exist on the board. The boot fails with a kernel panic: [ 82.619607] SCSI subsystem initialized [ 82.625477] PCI: No IRQ known for interrupt pin A of device 0000:00:05.0. Please try using pci=biosirq. [ 82.636355] ata1: SATA max UDMA/133 cmd 0x3000 ctl 0x3072 bmdma 0x2CD0 irq 0 [ 82.644455] ata2: SATA max UDMA/133 cmd 0x3010 ctl 0x3082 bmdma 0x2CD8 irq 0 [ 82.652544] Unable to handle kernel NULL pointer dereference at virtual address 00000000 I've tried 2 different (32 bit) kernels: the 2.6.15 one that comes with Gnewsense, and a stock 2.6.20.1 from kernel.org. I've attached both boot logs - the 2.6.15 one is called minicom-gb-20070306-04.cap, and the 2.6.20.1 is called minicom-gb-20070306-07.cap. I have not tried a 64 bit kernel yet. Any suggestions as to what is going on here? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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[LinuxBIOS] biossavior RD1-PMC4 not compatible with gigabyte m57sli-s4
by Ward Vandewege 19 Mar '07

19 Mar '07

For the record, the Biossavior RD1-PMC4 is not compatible with the Gigabyte M57SLI-S4 board. It simply won't boot from it, and flashrom doesn't see the built-in rom chip (but it works fine when you plug the original rom chip in there, of course. The original rom chip (soldered onto the board) is an SST49LF040B, which is not listed anywhere on the Biossavior compatibility list http://www.ioss.com.tw/web/English/RD1BIOSSavior/SelectionSheet.html Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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[LinuxBIOS] Is my hardware supported?
by Eki Fa-Clang Shabazz 19 Mar '07

19 Mar '07

Hello there, I'm looking to install linuxbios on my box here, as is a friend of mine. I was wondering how I am to know if my hardware is supported. Someone has suggested mailing hardware details to the list. Will an lspci or lshw work? Cheers.

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[LinuxBIOS] Flashrom and AM29LV040B flash chip
by Priit Laes 18 Mar '07

18 Mar '07

Hey, How well does Flashrom work with AM29LV040B [1] flash chip? I took apart my old Dell Latitude C600 laptop with thoughts that I could maybe get it working with LinuxBIOS, but well, chip itself is soldered on the motherboard [2] (16 pins inside 8 millimeters) so I would first have to figure out how to implement the hotswapping. Also, does anyone have ideas where to order these flash chips (PLCC) in Europe, preferably Finland? [1] Datasheets: http://www.spansion.com/products/Am29LV040B.html [2] http://plaes.org/files/2007-Q1/2007-03-18-latitude-c600-bios.jpg Cheers, Priit :)

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[LinuxBIOS] new: hello ?! recommendation and question
by C.-Valentin Schmitt 18 Mar '07

18 Mar '07

Hello dear Linuxbioxers, first this question: how do I reach the floppy-device for a bios-flash ??? It does not work here. I performed a new platform-independent bios-update. Its of course property of Free Software Foundation and of www.gnu.org, else of gnu-public-license from 1.0 to 2.0. It must NOT be used for malicious purpose and of course NOT for commmercial purpose. New bios-update runs really between geniousity and madness. Its really not insane. I name it simply "ga-ga-biox version 0.01". Its written in paranoian-modus and its really strange. I still dont know, why it works And of course the inventor of unix was a woman. But I dont know her, and I dont know, if she still is alive. Please reply, if line is ok. I answer not today ! here already strange things happen. take care. best regards to the tux-community. V. _______________________________________________________________________ Viren-Scan für Ihren PC! Jetzt für jeden. Sofort, online und kostenlos. Gleich testen! http://www.pc-sicherheit.web.de/freescan/?mc=022222

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[LinuxBIOS] [PATCH] Add initial serial output for Via vt82c686
by Corey Osgood 18 Mar '07

18 Mar '07

This patch is just for initial serial output for the Via vt82c686(a/b) southbridge, no more and no less. SMBus and the rest of the SuperI/O functions are yet to be written. I've confirmed that this works on Tyan S2507 (vt686b), and it should also work fine on vt686a. This is based rather loosely on Uwe's code for the SMSC FDC37M60x. Signed-off-by: Corey Osgood <corey_osgood(a)verizon.net>

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[LinuxBIOS] r2571 build service
by LinuxBIOS information 17 Mar '07

17 Mar '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2571 to the LinuxBIOS source repository and caused the following changes: Change Log: Add initial pre-RAM serial output support for the VIA VT82C686(A/B) southbridge (with integrated Super-I/O). Signed-off-by: Corey Osgood <corey_osgood(a)verizon.net> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood(a)verizon.net> Build Log: Compilation of gigabyte:m57sli is still broken Configuration of msi:ms9282 is still broken Compilation of nvidia:l1_2pvv is still broken Compilation of supermicro:h8dmr is still broken Compilation of tyan:s2912 is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2571 - in trunk/LinuxBIOSv2/src/southbridge/via: . vt82c686
by svn＠openbios.org 17 Mar '07

17 Mar '07

Author: uwe Date: 2007-03-17 15:00:23 +0100 (Sat, 17 Mar 2007) New Revision: 2571 Added: trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/ trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/Config.lb trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/chip.h trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686.h trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686_early_serial.c Log: Add initial pre-RAM serial output support for the VIA VT82C686(A/B) southbridge (with integrated Super-I/O). Signed-off-by: Corey Osgood <corey_osgood(a)verizon.net> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood(a)verizon.net> Added: trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/Config.lb 2007-03-17 14:00:23 UTC (rev 2571) @@ -0,0 +1,22 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h + Added: trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/chip.h 2007-03-17 14:00:23 UTC (rev 2571) @@ -0,0 +1,35 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SUPERIO_VIA_VT82C686 +#define _SUPERIO_VIA_VT82C686 + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_via_vt82c686_ops; + +struct superio_via_vt82c686_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; + +#endif /* _SUPERIO_VIA_VT82C686 */ Added: trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686.h 2007-03-17 14:00:23 UTC (rev 2571) @@ -0,0 +1,56 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets: + * Name: VT82C686A "Super South" South Bridge + * Link: http://www.datasheets.org.uk/datasheet.php?article=3510260 + * Name: VT82C686B "Super South" South Bridge + * Link: http://www.datasheet4u.com/html/V/T/8/VT82C686B_VIA.pdf.html + */ + +/* Super I/0 Configuration Registers. */ +/* Any registers not listed here are reserved. */ +#define VT82C686_SIO_DEV_ID 0xe0 /* Super-I/O Device ID */ +#define VT82C686_SIO_REV 0xe1 /* Super-I/O Device Revision */ +#define VT82C686_FS 0xe2 /* Function Select */ +#define VT82C686_FDC 0xe3 /* Floppy */ +#define VT82C686_PP 0xe6 /* Parallel Port */ +#define VT82C686_SP1 0xe7 /* Serial Port 1 */ +#define VT82C686_SP2 0xe8 /* Serial Port 2 */ +#define VT82C686_SP_CFG 0xee /* Serial Port Configuration */ +#define VT82C686_POWER 0xef /* Power Down Control */ +#define VT82C686_PP_CTRL 0xf0 /* Parallel Port Control */ +#define VT82C686_SP_CTRL 0xf1 /* Serial Port Control */ +#define VT82C686_FDC_CFG 0xf6 /* Floppy Controller Configuration */ +#define VT82C686_FDC_DC 0xf8 /* Floppy Drive Control */ +#define VT82C686_GPIO 0xfc /* General Purpose I/O */ + +/* For reference, used PCI IDs and their names in pci_ids.h: */ +/* +PCI_VENDOR_ID_VIA 0x1106 +PCI_DEVICE_ID_VIA_82C686 0x0686 // Function 0, PCI Config +PCI_DEVICE_ID_VIA_82C586_1 0x0571 // Function 1, IDE Controller +PCI_DEVICE_ID_VIA_82C586_2 0x3038 // Functions 2 & 3, USB Ports 0-1 & 2-3 +PCI_DEVICE_ID_VIA_82C586_3 0x3040 // Possible 2nd USB Controller? +PCI_DEVICE_ID_VIA_82C686_4 0x3057 // Function 4, Power Management +PCI_DEVICE_ID_VIA_82C686_5 0x3058 // Function 5, AC'97 Codec +PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec +*/ + Added: trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686_early_serial.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt82c686/vt82c686_early_serial.c 2007-03-17 14:00:23 UTC (rev 2571) @@ -0,0 +1,92 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006-2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x + * by Corey Osgood. See vt82c686.h for more information. */ + +#include <arch/romcc_io.h> +#include <device/pci_ids.h> +#include "vt82c686.h" + +#define SIO_INDEX 0x3f0 +#define SIO_DATA 0x3f1 + +/** + * Configure the chip by writing the byte 'value' into the register + * specified by 'index'. + * + * @param index The index of the register to modify. + * @param value The value to write into the register. + */ +static void vt82c686_sio_write(uint8_t index, uint8_t value) +{ + outb(index, SIO_INDEX); + outb(value, SIO_DATA); +} + +/** + * Enable the serial port(s) of the VT82C686(A/B) Super I/O chip. + * + * @param dev TODO + * @param iobase TODO + */ +static void vt82c686_enable_serial(device_t dev, unsigned iobase) +{ + uint8_t reg; + device_t sbdev; + + /* TODO: Use info from 'dev' and 'iobase'. */ + /* TODO: Only enable one serial port (depending on config) or both? */ + + /* (1) Enter configuration mode (set Function 0 Rx85[1] = 1). */ + + /* Find the southbridge. Die upon error. */ + sbdev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_82C686), 0); + // sbdev = PCI_DEV(0, 7, 0); + if (sbdev == PCI_DEV_INVALID) { + /* Serial output is not yet working at this point, but + * die() emits the POST code 0xff and halts the CPU, too. */ + die("Southbridge not found.\r\n"); + } + + /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ + reg = pci_read_config8(sbdev, 0x85); + pci_write_config8(sbdev, 0x85, reg | 0x3); /* Set bits 0 and 1. */ + + /* (2) Configure the chip. */ + + /* Enable serial port 1 (set bit 2) and 2 (set bit 3). */ + vt82c686_sio_write(VT82C686_FS, 0xf); + + // vt82c686_sio_write(VT82C686_POWER, 0x00); /* No powerdown */ + // vt82c686_sio_write(VT82C686_SP_CTRL, 0x00); /* Normal operation */ + vt82c686_sio_write(VT82C686_SP1, 0xfe); /* SP1: 0x3f8 */ + vt82c686_sio_write(VT82C686_SP2, 0xbe); /* SP2: 0x2f8 */ + + /* Enable high speed on serial port 1 (set bit 6) and 2 (set bit 7). */ + vt82c686_sio_write(VT82C686_SP_CFG, 0xc0); + + /* (3) Exit configuration mode (set Function 0 Rx85[1] = 0). */ + reg = pci_read_config8(sbdev, 0x85); + pci_write_config8(sbdev, 0x85, reg & 0xfd); /* Clear bit 1. */ +} +

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[LinuxBIOS] Via vt82c694 (vt694) in LBv1 - working?
by Corey Osgood 16 Mar '07

16 Mar '07

I've been trying for days to get this chipset to pass a ram test, and nothing seems to work. So far, I've tried programming the registers in the order they're programmed in v1, both from raminit.inc and raminitspd.inc. I'm assuming that since there _IS_ a raminit using spd, that the raminit without spd works, or did work at some point. Is that a valid assumption, or should I be starting from scratch? In the comments, there are also notes about register orders that were tried, and notes when it failed, but doesn't say that it ever worked. I've also tried using the ordering from vt8601, which seems to be very similar. I've been using values from LBv1, values from my lspci, and values that I've come up with from the datasheets. The ram seems to be initializing (checking 16mb takes roughly 20 minutes), but it never passes. Depending on what I use, it either spurts out random values, 0xffffffff, or alternates between that and 0xffffff80. I've also tried it both with the dimm writes in vt8601 and vt694 from v1 and without. I've also noticed something a bit weird. Rx78[0] controls CKE, and setting it to 1 enables it, according to the docs. lspci reports that it's set to 0, I might be wrong but that doesn't seem quite right. Should I be trusting lspci, and disabling CKE, or writing that off as an error on lspci's part? Thanks, Corey

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[LinuxBIOS] Google Summer of Code(tm) 2007
by Stefan Reinauer 16 Mar '07

16 Mar '07

Hi, we have successfully applied for Google Summer of Code(tm) 2007. >From the GSoC-FAQ: > Google Summer of Code(tm) is a program that offers student developers > stipends to write code for various open source projects. Google will > be working with a several open source, free software and > technology-related groups to identify and fund several projects over a > three month period. Historically, the program has brought together > over 1,000 students with over 100 open source projects, to create > hundreds of thousands of lines of code. Find more information at http://code.google.com/soc/ We also started setting up a list of ideas for student projects. http://linuxbios.org/GSoC If you wish to participate, and take one of the projects, or have another idea for a project, please contact me via email or apply via the Google GSoC page. Have fun! Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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coreboot March 2007