coreboot March 2007

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[LinuxBIOS] r2572 - trunk/LinuxBIOSv2/src/mainboard/agami/aruma
by svn＠openbios.org 20 Mar '07

20 Mar '07

Author: stepan Date: 2007-03-20 14:43:50 +0100 (Tue, 20 Mar 2007) New Revision: 2572 Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c Log: fix a stupid cut and paste error. This is pretty trivial, as it was correct in the original non-CAR code. Suddently, CAR works nicely. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c 2007-03-17 14:00:23 UTC (rev 2571) +++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c 2007-03-20 13:43:50 UTC (rev 2572) @@ -64,24 +64,26 @@ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); } +/* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), + SMBUS_IO_BASE + 0xc0 + 29); } static void memreset(int controllers, const struct mem_controller *ctrl) { - if (is_cpu_pre_c0()) { - udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); - } + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), + SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } } static inline void activate_spd_rom(const struct mem_controller *ctrl)

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Re: [LinuxBIOS] linuxbios Digest, Vol 25, Issue 79
by C.-Valentin Schmitt 20 Mar '07

20 Mar '07

looks like symbiotic bios - stuff . . . my recommendation: $hithappen$ > -----Ursprüngliche Nachricht----- > Von: linuxbios(a)linuxbios.org > Gesendet: 20.03.07 12:15:48 > An: linuxbios(a)linuxbios.org > Betreff: linuxbios Digest, Vol 25, Issue 79 > Send linuxbios mailing list submissions to > linuxbios(a)linuxbios.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.linuxbios.org/mailman/listinfo/linuxbios > or, via email, send a message with subject or body 'help' to > linuxbios-request(a)linuxbios.org > > You can reach the person managing the list at > linuxbios-owner(a)linuxbios.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of linuxbios digest..." > > > Today's Topics: > > 1. Re: how flashrom works (Stefan Reinauer) > 2. Re: usage of pci_write_config32()? (Corey Osgood) > 3. Re: linuxbios Digest, Vol 25, Issue 71 (C.-Valentin Schmitt) > 4. microcode updates on amd64 (Stefan Reinauer) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 20 Mar 2007 09:52:16 +0100 > From: Stefan Reinauer <stepan(a)coresystems.de> > Subject: Re: [LinuxBIOS] how flashrom works > To: Anton <anton.borisov(a)gmail.com> > Cc: linuxbios(a)linuxbios.org > Message-ID: <20070320085216.GA23927(a)coresystems.de> > Content-Type: text/plain; charset=utf-8 > > * Anton <anton.borisov(a)gmail.com> [070320 09:31]: > > Can someone give me a pointer on flashrom programming? > > I look into sst28sf040.h, there are 3 functions available: probe(), > > erase(), write(). How the read() from chip is implemented? > > The area is mmap'ed and then just read as normal memory. > If you do -r, it uses memcpy, flash_rom.c:325 > > Stefan > > -- > coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 ? Fax: +49 761 7664613 > Email: info(a)coresystems.de ? http://www.coresystems.de/ > > > > ------------------------------ > > Message: 2 > Date: Tue, 20 Mar 2007 05:30:25 -0400 > From: Corey Osgood <corey_osgood(a)verizon.net> > Subject: Re: [LinuxBIOS] usage of pci_write_config32()? > To: Stefan Reinauer <stepan(a)coresystems.de> > Cc: ron minnich <rminnich(a)gmail.com>, LinuxBIOS Mailing List > <linuxbios(a)linuxbios.org> > Message-ID: <45FFA9B1.7070609(a)verizon.net> > Content-Type: text/plain; charset=UTF-8 > > Stefan Reinauer wrote: > > * Corey Osgood <corey_osgood(a)verizon.net> [070320 05:45]: > >> It's raminit.c from LBv1's src/northbridge/440gx/, it addresses the > >> first register for a 32-bit write to 0x50-0x53, then the second for a > >> 16-bit write later on, can't see at the moment which it was. I'm working > >> on trying to port that up to v2, to see if it'll work on a 440zx, since > >> nothing else I've done seems to be working. > > > > Note that on some systems, a 32bit write is very different from 4 8bit > > writes. If it is a 32bit register, you should always read/write all 32 > > bits. > > > > Stefan > > > > Yes, but on 440bx doesn't seem to matter, LBv1 uses 8-bit writes all > over the place on it. And yes, it was 0x44332211, written to the last > reg in the set, I've fixed my code accordingly (not that it works, but > at least correct now on that part). > > -Corey > > > > ------------------------------ > > Message: 3 > Date: Tue, 20 Mar 2007 10:56:41 +0100 > From: "C.-Valentin Schmitt" <c-v.schmitt(a)web.de> > Subject: Re: [LinuxBIOS] linuxbios Digest, Vol 25, Issue 71 > To: linuxbios(a)linuxbios.org > Message-ID: <275643733(a)web.de> > Content-Type: text/plain; charset=iso-8859-15 > > > > I dont know ! I have no clue ! > > misco ??? > kingston ??? > > > > -----Urspr?ngliche Nachricht----- > > Von: linuxbios(a)linuxbios.org > > Gesendet: 19.03.07 09:47:00 > > An: linuxbios(a)linuxbios.org > > Betreff: linuxbios Digest, Vol 25, Issue 71 > > > > Send linuxbios mailing list submissions to > > linuxbios(a)linuxbios.org > > > > To subscribe or unsubscribe via the World Wide Web, visit > > http://www.linuxbios.org/mailman/listinfo/linuxbios > > or, via email, send a message with subject or body 'help' to > > linuxbios-request(a)linuxbios.org > > > > You can reach the person managing the list at > > linuxbios-owner(a)linuxbios.org > > > > When replying, please edit your Subject line so it is more specific > > than "Re: Contents of linuxbios digest..." > > > > > > Today's Topics: > > > > 1. Re: Flashrom and AM29LV040B flash chip (Peter Stuge) > > 2. Re: filo ide speedup patch? (Peter Stuge) > > 3. Re: linuxbios + xf86-video-unichrome: no VGA BIOS needed. > > (Peter Stuge) > > 4. Re: filo ide speedup patch? (Peter Stuge) > > 5. Getting Friendly with Flashrom (David H. Barr) > > 6. Re: Getting Friendly with Flashrom (Peter Stuge) > > 7. Re: Is my hardware supported? (Corey Osgood) > > 8. Re: northbridge docs (joe(a)smittys.pointclark.net) > > 9. Re: northbridge docs (Corey Osgood) > > > > > > ---------------------------------------------------------------------- > > > > Message: 1 > > Date: Mon, 19 Mar 2007 01:08:37 +0100 > > From: Peter Stuge <stuge-linuxbios(a)cdy.org> > > Subject: Re: [LinuxBIOS] Flashrom and AM29LV040B flash chip > > To: linuxbios(a)linuxbios.org > > Message-ID: <20070319000837.5522.qmail(a)cdy.org> > > Content-Type: text/plain; charset=us-ascii > > > > On Sun, Mar 18, 2007 at 05:46:34PM +0200, Priit Laes wrote: > > > How well does Flashrom work with AM29LV040B [1] flash chip? > > > > It should work out of the box, if not it will be trivial to add. > > > > > > > I took apart my old Dell Latitude C600 laptop with thoughts that I could > > > maybe get it working with LinuxBIOS, but well, chip itself is soldered > > > on the motherboard [2] (16 pins inside 8 millimeters) so I would first > > > have to figure out how to implement the hotswapping. > > > > Emulation Technology have a TSOP prototyping socket that you could > > solder on to the board instead of the TSOP chip. Then have a few TSOP > > chips to swap between. > > > > http://www.emulation.com/catalog/off-the-shelf_solutions/sockets/tsop/ > > > > Note that these sockets are rated for a minimum of 50 insert/remove > > cycles. > > > > > > > Also, does anyone have ideas where to order these flash chips > > > (PLCC) in Europe, preferably Finland? > > > > On the picture is a TSOP chip. Either way, I think Farnell or maybe > > Avnet are good sources for single quantity chips. > > > > > > > [2] http://plaes.org/files/2007-Q1/2007-03-18-latitude-c600-bios.jpg > > > > There are pads for a PLCC chip on the board. PLCC is much easier to > > work with so I would go for that instead of the TSOP. (Maybe that was > > your thought too.) You would have to scrape off the green lacquer to > > expose the pads but if done carefully with a steady hand and a sharp > > knife (or fibre glass brush) that's fairly easy. > > > > > > //Peter > > > > > > > > ------------------------------ > > > > Message: 2 > > Date: Mon, 19 Mar 2007 01:20:53 +0100 > > From: Peter Stuge <stuge-linuxbios(a)cdy.org> > > Subject: Re: [LinuxBIOS] filo ide speedup patch? > > To: linuxbios(a)linuxbios.org > > Message-ID: <20070319002053.7138.qmail(a)cdy.org> > > Content-Type: text/plain; charset="us-ascii" > > > > On Sun, Mar 18, 2007 at 06:36:44PM +0100, Stefan Reinauer wrote: > > > > Find attached a patch for timer2 and hard reset. I'm looking at > > > > FILO right now. > > > > > > The below patch works fine on my system, but some older versions of > > > the C3 lack support for the rdtsc command. (Nehemiah has it) > > > > > > Whereas the Centaur/Wincore is said to not have rdtsc. > > > > Aha! > > > > > > > I would assume the patch is wrong for the epia and right for the > > > epia-m. > > > > > > Do you mind dropping the epia part? > > > > Not at all, we should have working defaults, but I'll add a note to > > the wiki for people to enable it if they have Nehemiah. > > > > Can CONFIG_UDELAY_TSC=1 in targets/via/epia/Config.lb also > > automatically set CONFIG_UDELAY_IO=0 ? > > > > > > //Peter > >

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[LinuxBIOS] microcode updates on amd64
by Stefan Reinauer 20 Mar '07

20 Mar '07

Hi, There seem to be no microcode updates for K8 C0 CPUs. Can any of the available microcode updates be used on the C0? Any chance to get them supported? Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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Re: [LinuxBIOS] linuxbios Digest, Vol 25, Issue 71
by C.-Valentin Schmitt 20 Mar '07

20 Mar '07

I dont know ! I have no clue ! misco ??? kingston ??? > -----Ursprüngliche Nachricht----- > Von: linuxbios(a)linuxbios.org > Gesendet: 19.03.07 09:47:00 > An: linuxbios(a)linuxbios.org > Betreff: linuxbios Digest, Vol 25, Issue 71 > Send linuxbios mailing list submissions to > linuxbios(a)linuxbios.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.linuxbios.org/mailman/listinfo/linuxbios > or, via email, send a message with subject or body 'help' to > linuxbios-request(a)linuxbios.org > > You can reach the person managing the list at > linuxbios-owner(a)linuxbios.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of linuxbios digest..." > > > Today's Topics: > > 1. Re: Flashrom and AM29LV040B flash chip (Peter Stuge) > 2. Re: filo ide speedup patch? (Peter Stuge) > 3. Re: linuxbios + xf86-video-unichrome: no VGA BIOS needed. > (Peter Stuge) > 4. Re: filo ide speedup patch? (Peter Stuge) > 5. Getting Friendly with Flashrom (David H. Barr) > 6. Re: Getting Friendly with Flashrom (Peter Stuge) > 7. Re: Is my hardware supported? (Corey Osgood) > 8. Re: northbridge docs (joe(a)smittys.pointclark.net) > 9. Re: northbridge docs (Corey Osgood) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Mon, 19 Mar 2007 01:08:37 +0100 > From: Peter Stuge <stuge-linuxbios(a)cdy.org> > Subject: Re: [LinuxBIOS] Flashrom and AM29LV040B flash chip > To: linuxbios(a)linuxbios.org > Message-ID: <20070319000837.5522.qmail(a)cdy.org> > Content-Type: text/plain; charset=us-ascii > > On Sun, Mar 18, 2007 at 05:46:34PM +0200, Priit Laes wrote: > > How well does Flashrom work with AM29LV040B [1] flash chip? > > It should work out of the box, if not it will be trivial to add. > > > > I took apart my old Dell Latitude C600 laptop with thoughts that I could > > maybe get it working with LinuxBIOS, but well, chip itself is soldered > > on the motherboard [2] (16 pins inside 8 millimeters) so I would first > > have to figure out how to implement the hotswapping. > > Emulation Technology have a TSOP prototyping socket that you could > solder on to the board instead of the TSOP chip. Then have a few TSOP > chips to swap between. > > http://www.emulation.com/catalog/off-the-shelf_solutions/sockets/tsop/ > > Note that these sockets are rated for a minimum of 50 insert/remove > cycles. > > > > Also, does anyone have ideas where to order these flash chips > > (PLCC) in Europe, preferably Finland? > > On the picture is a TSOP chip. Either way, I think Farnell or maybe > Avnet are good sources for single quantity chips. > > > > [2] http://plaes.org/files/2007-Q1/2007-03-18-latitude-c600-bios.jpg > > There are pads for a PLCC chip on the board. PLCC is much easier to > work with so I would go for that instead of the TSOP. (Maybe that was > your thought too.) You would have to scrape off the green lacquer to > expose the pads but if done carefully with a steady hand and a sharp > knife (or fibre glass brush) that's fairly easy. > > > //Peter > > > > ------------------------------ > > Message: 2 > Date: Mon, 19 Mar 2007 01:20:53 +0100 > From: Peter Stuge <stuge-linuxbios(a)cdy.org> > Subject: Re: [LinuxBIOS] filo ide speedup patch? > To: linuxbios(a)linuxbios.org > Message-ID: <20070319002053.7138.qmail(a)cdy.org> > Content-Type: text/plain; charset="us-ascii" > > On Sun, Mar 18, 2007 at 06:36:44PM +0100, Stefan Reinauer wrote: > > > Find attached a patch for timer2 and hard reset. I'm looking at > > > FILO right now. > > > > The below patch works fine on my system, but some older versions of > > the C3 lack support for the rdtsc command. (Nehemiah has it) > > > > Whereas the Centaur/Wincore is said to not have rdtsc. > > Aha! > > > > I would assume the patch is wrong for the epia and right for the > > epia-m. > > > > Do you mind dropping the epia part? > > Not at all, we should have working defaults, but I'll add a note to > the wiki for people to enable it if they have Nehemiah. > > Can CONFIG_UDELAY_TSC=1 in targets/via/epia/Config.lb also > automatically set CONFIG_UDELAY_IO=0 ? > > > //Peter >

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[LinuxBIOS] usage of pci_write_config32()?
by Corey Osgood 20 Mar '07

20 Mar '07

With pci_write_config32 (or pci_write_config16), do you send the value to the first or the last register in the set? In other words, if it's a range of 0x50-0x53, where should it be sent to? And if you were looking to set it like this: 0x50 -> 0x11 0x51 -> 0x22 0x52 -> 0x33 0x53 -> 0x44 it should be set as 0x11223344, correct? I'm looking at two different files, and their usage conflicts, I'd like to know which is right. Thanks, Corey

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[LinuxBIOS] how flashrom works
by Anton 20 Mar '07

20 Mar '07

Can someone give me a pointer on flashrom programming? I look into sst28sf040.h, there are 3 functions available: probe(), erase(), write(). How the read() from chip is implemented? Thanks.

2 1

[LinuxBIOS] Userspace boot manager stored in ROM
by Vlad 20 Mar '07

20 Mar '07

Hi, I noticed that there is a proposed Google Summer of Code project (http://linuxbios.org/GSoC) to fork IDE drivers from the Linux kernel and port them to Linux-independent boot managers like GRUB2. I dont think this is a good design choice or a sustainable solution. There are many different IDE controllers, each with its own peculiarities that must be taken into account by the drivers. The volume on the Linux-IDE mailing list (http://marc.info/?l=linux-ide) can reach more than 1,000 messages a month, and critical fixes to the drivers are made daily. Who is going to make sure that all these fixes are ported to the boot manager on a regular basis? I think a more sustainable solution is to write a userspace boot manager that harnesses the kernels I/O facilities. LinuxBIOS, the Linux kernel (payload) and the userspace boot manager would all be stored in the ROM. The userspace boot manager would mount devices in a pre-defined order (configurable by the user) and search for a file named grub.cfg on that device. This file is used to specify the pathname of the kernel(s) stored on the device, the parameters to pass to the kernel(s), and the descriptions of various boot options. The userspace boot manager would then display these options to the user and let him/her choose (a timeout is normally specified in the grub.cfg file, after which the default option is automatically chosen). The userspace boot manager then kexecs the chosen operating system from the device. Here are the foreseen advantages and disadvantages of a userspace boot manager: Advantages: 1)No need to port drivers for IDE, VGA, keyboard, and mouse from the Linux kernel to the boot manager. 2)Bug fixes to the drivers are automatically included in new Linux kernel releases. 3)Because the Linux kernel payload is flashed to the motherboards ROM and will run only on that motherboard, it is possible to do a thorough testing of how well the kernels IDE driver works with the motherboards IDE controller. Contrast this to a scenario where GRUB2 is distributed on installation CDs and must recognize any IDE controller that is thrown at it. 4)Many more types of devices become bootable by merely enabling support for them when compiling the kernel. Examples include FireWire disks, ZIP disks, USB flash keys, SD/MMC cards, network locations (via ethernet, wireless, dialup modem, bluetooth) as well as the more traditional media such as CD/DVDs, floppies, and hard drives. 5)Bootable media can be encoded in any filesystem recognized by Linux (FAT, ReiserFS, EXT2/3, NTFS, XFS, JFS, etc). 6)The userspace boot manager would contain relatively little code that mostly deals with presentation (ncurses or X.org-based). 7)The hardware interface that the Linux kernel exposes to userspace apps is very stable, and HAL (http://hal.freedesktop.org) can be used to make hardware discovery even simpler. Disadvantages: 1) Distributions would have to follow a well-defined standard for formatting their grub.cfg file. But this shouldnt be a problem because grub.cfg comes from GRUB and should therefore already be the standard. And even if the grub.cfg file is completely left out of the installation media, the userspace boot manager could still be configured to let the user type the pathname where the kernel is found on the device (like FILO does it). So, what do you guys think about a userspace boot manager stored in the ROM? Thanks, Vlad ____________________________________________________________________________________ Don't pick lemons. See all the new 2007 cars at Yahoo! Autos. http://autos.yahoo.com/new_cars.html

3 3

[LinuxBIOS] register_values question
by joe＠smittys.pointclark.net 20 Mar '07

20 Mar '07

This may sound like a dumb question but I am wondering. In this statment from raminit.c in the sdram_set_registers function: --------------------------------------------------------------- static const unsigned int register_values[] = { /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, }; --------------------------------------------------------------- It is setting the register PCI_ADDR(0, 0x00, 0, CKDIS) from 0xffff0000 to 0x0000ffff correct?? But what if I just want it use it's default register setting do I need to specify it?? If so, would it look something like this?? ------------------------------------------------------ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0xffff0000, ------------------------------------------------------ Thanks - Joe

1 0

[LinuxBIOS] PCI_ADDR
by joe＠smittys.pointclark.net 19 Mar '07

19 Mar '07

Does anyone know where (waht file) PCI_ADDR is defined? Thanks - Joe

2 1

[LinuxBIOS] m57sli-s4 build tutorial
by Ward Vandewege 19 Mar '07

19 Mar '07

I've put up a build tutorial for the m57sli-s4 at http://linuxbios.org/M57SLI-S4_Build_Tutorial It's still based off of YH's big patch, but if Ed's patch from today gets merged, I will update the tutorial to use the v2 tree. Remaining issues are ACPI support, and the mac address changes (but Stefan might have a way to fix that). Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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coreboot March 2007