coreboot September 2006

coreboot@coreboot.org

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173 discussions

[LinuxBIOS] Desktop computer use?
by Bario 20 Sep '06

20 Sep '06

Hi, I'm curious about a few things about LinuxBIOS. First off, is LinuxBIOS usable (or intended to be) in a standard desktop environment, or aimed solely at embedded/cluster application? If the answer to that question is the latter, ignore the rest of this post. I'm looking to use linuxbios on an intel bi440zx, a P3 mobo with a 440zx chipset. I'm wondering if anyone has worked on support for this motherboard, or even this chipset, or if the code for the 440BX chipset works as a drop-in replacement. Info as requested in FAQ: CPU: I'm currently using this mobo with a 466MHz Celeron (Mendocino core) due to BIOS limitations. The chipset (440zx) supports 100MHz FSB, and I have a P3 1.0GHz (133*7.5), would it be possible to use this chip with linuxbios and run it at 750MHz (100*7.5)? The current BIOS doesn't allow this. This is one of my main reasons for looking at linuxbios, the other being that it will be a fileserver, and the faster the boot time the better. Other: 40gb hard drive and ATAPI cdrom connected to built-in IDE, and possibly a PCI IDE controller with a 250GB hard drive (this wouldn't matter at boot time, only after the kernel loads). Computer will most likely be controlled mainly through ssh once it's completely set up. ISA support is not needed, nor is the built-in ES1371 audio controller. root[~]# lspci -v 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) Subsystem: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge Flags: bus master, medium devsel, latency 64 Memory at f0000000 (32-bit, prefetchable) [size=64M] Capabilities: [a0] AGP version 1.0 00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) (prog-if 00 [Normal decode]) Flags: bus master, 66MHz, medium devsel, latency 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: f6a00000-f6afffff Prefetchable memory behind bridge: dc800000-de8fffff 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) Flags: bus master, medium devsel, latency 0 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) (prog-if 80 [Master]) Flags: bus master, medium devsel, latency 64 I/O ports at ffa0 [size=16] 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) (prog-if 00 [UHCI]) Flags: bus master, medium devsel, latency 64, IRQ 10 I/O ports at ef80 [size=32] 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) Flags: medium devsel, IRQ 9 00:0c.0 Multimedia audio controller: Ensoniq ES1371 [AudioPCI-97] (rev 04) Subsystem: Intel Corporation ES1371, ES1373 AudioPCI On Motherboard BI440ZX Flags: bus master, slow devsel, latency 64, IRQ 11 I/O ports at ef00 [size=64] Capabilities: [dc] Power Management version 1 00:0e.0 VGA compatible controller: 3Dfx Interactive, Inc. Voodoo 4 / Voodoo 5 (rev 01) (prog-if 00 [VGA]) Subsystem: 3Dfx Interactive, Inc. Voodoo5 AGP 5500/6000 Flags: 66MHz, fast devsel, IRQ 11 Memory at f8000000 (32-bit, non-prefetchable) [size=64M] Memory at e8000000 (32-bit, prefetchable) [size=128M] I/O ports at e800 [size=256] Expansion ROM at febf0000 [disabled] [size=64K] Capabilities: [60] Power Management version 2 00:10.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RT8139 Flags: bus master, medium devsel, latency 64, IRQ 10 I/O ports at e400 [size=256] Memory at febefc00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 01:00.0 VGA compatible controller: ATI Technologies Inc 3D Rage Pro AGP 1X/2X (rev 5c) (prog-if 00 [VGA]) Subsystem: ATI Technologies Inc Rage Pro Turbo AGP 2X Flags: stepping, medium devsel Memory at dd000000 (32-bit, prefetchable) [disabled] [size=16M] I/O ports at d000 [disabled] [size=256] Memory at f6a00000 (32-bit, non-prefetchable) [disabled] [size=4K] Expansion ROM at dc800000 [disabled] [size=128K] Capabilities: [50] AGP version 1.0 If either the Rage or the Voodoo work, I'm happy, but I have no need for both, I just installed had to flash the voodoo's bios to get it working, and haven't removed the rage yet. Super I/O: I think this is the right chip: SMSC FDC37B807 BIOS info: Intel E28F200 2Mbit Flash bios (info in mobo docs) Online documentation: Motherboard: http://www.intel.com/support/motherboards/desktop/bi440zx/ Northbridge: http://www.intel.com/design/chipsets/440zx/ Southbridge (although this appears to be already supported): http://www.intel.com/design/intarch/datashts/290562.htm Thanks for any help you can offer in giving this old system a new life ;) __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

4 4

[LinuxBIOS] r2428 - trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 21:30:11 +0200 (Tue, 19 Sep 2006) New Revision: 2428 Modified: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/auto.c trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c Log: commit moire changes Modified: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb 2006-09-19 17:38:57 UTC (rev 2427) +++ trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb 2006-09-19 19:30:11 UTC (rev 2428) @@ -125,32 +125,69 @@ chip northbridge/amd/lx register "irqmap" = "0xcba5" - register "setupflash" = "1" device apic_cluster 0 on chip cpu/amd/model_lx device apic 0 on end end end device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536_lx - register "enable_gpio0_inta" = "1" - register "enable_ide_nand_flash" = "1" - register "enable_uarta" = "1" - register "audio_irq" = "11" - register "usbf4_irq" = "5" - register "usbf5_irq" = "5" - register "usbf6_irq" = "5" - register "usbf7_irq" = "5" - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio + + device pci 1.0 on end # Host Bridge + + chip drivers/pci/realmode + device pci 1.1 on end # VGA + register "rom_address" = "0xfffc0000" # at the beginning of 256k + end + + device pci 1.2 off end # AES + chip southbridge/amd/cs5536_lx + register "enable_ide_nand_flash" = "0" + + register "isa_irq" = "0" + #register "flash_irq" = "14" + + ## IDE IRQ + register "enable_ide_irq" = "0" + + register "audio_irq" = "5" + register "usb_irq" = "7" + + register "uart0_irq" = "0" + register "uart1_irq" = "4" + + ## PCI INTA ... INTD and their GPIO pins + ## int==0: disable + register "pci_int[0]" = "0" + register "pci_int[1]" = "10" + register "pci_int[2]" = "0" + register "pci_int[3]" = "0" + register "pci_int_pin[0]" = "0" + register "pci_int_pin[1]" = "7" + register "pci_int_pin[2]" = "0" + register "pci_int_pin[3]" = "0" + + + # Keyboard Emulation Logic IRQs + # Enable keyboard IRQ2 + register "enable_kel_keyb_irq" = "0" + # Enable mouse IRQ12 + register "enable_kel_mouse_irq" = "0" + # Configure KEL Emulation IRQ, 0 to disable + register "kel_emul_irq" = "0" + + device pci f.0 on end # ISA Bridge + device pci f.1 on end # Flash controller + device pci f.2 off end # IDE controller + device pci f.3 on end # Audio device pci f.4 on end # OHCI device pci f.5 on end # EHCI - register "unwanted_vpci[0]" = "0" # End of list has a zero - end - end + device pci f.6 off end # UDC controller + device pci f.7 off end # OTG controller + end + chip drivers/pci/rtl8139 + device pci d.0 on end # Realtek LAN + register "nic_irq" = "10" + end + end end Modified: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb 2006-09-19 17:38:57 UTC (rev 2427) +++ trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb 2006-09-19 19:30:11 UTC (rev 2428) @@ -40,6 +40,9 @@ uses TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses VIDEO_MB ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 @@ -47,6 +50,9 @@ ### ### Build options ### +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=0 +default VIDEO_MB=8 ## ## Build code for the fallback boot Modified: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/auto.c 2006-09-19 17:38:57 UTC (rev 2427) +++ trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/auto.c 2006-09-19 19:30:11 UTC (rev 2428) @@ -37,24 +37,6 @@ return r; } - - - -/* sdram parameters for OLPC: - row address = 13 - col address = 9 - banks = 4 - dimm0size=128MB - d0_MB=1 (module banks) - d0_cb=4 (component banks) - do_psz=4KB (page size) - Trc=10 (clocks) (ref2act) - Tras=7 (act2pre) - Trcd=3 (act2cmd) - Trp=3 (pre2act) - Trrd=2 (act2act) - Tref=17.8ms - */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * @@ -65,50 +47,9 @@ msr_t msr; unsigned char module_banks, val; + msr.hi = 0x10075012; + msr.lo = 0x00000040; -#if 0 //GX3 - msr = rdmsr(MC_CF07_DATA); - - /* get module banks (sides) per dimm, SPD byte 5 */ - module_banks = 1; - module_banks >>= 1; - msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); - msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); - - /* get component banks per module bank, SPD byte 17 */ - val = 4; - val >>= 2; - msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); - - /* get the module bank density, SPD byte 31 */ - /* this is multiples of 8 MB */ - /* actually it is 2^x*4, where x is the value you put in */ - /* for OLPC, set default size */ - /* dimm size - hardcoded 128Mb */ - val = 5; - msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT); - - /* page size = 2^col address */ - val = 2; /* 4096 bytes */ - msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); - - print_debug("computed msr.hi "); - print_debug_hex32(msr.hi); - print_debug("\r\n"); - - /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ - /* well, it may be close. It's about 200,000 ticks */ - msr.lo = 0x00003000; - wrmsr(MC_CF07_DATA, msr); - -#endif - - msr.hi = 0x00005012; - msr.lo = 0x05000040; - wrmsr(MC_CF07_DATA, msr); //GX3 /* timing and mode ... */ @@ -140,17 +81,17 @@ #include "northbridge/amd/lx/raminit.c" #include "sdram/generic_sdram.c" -#define PLLMSRhi 0x00001490 -#define PLLMSRlo 0x02000030 -#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) -#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) +/* CPU and GLIU mult/div */ +#define PLLMSRhi 0x0000039C +/* Hold Count - how long we will sit in reset */ +#define PLLMSRlo 0x00DE0000 + #include "northbridge/amd/lx/pll_reset.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c" + static void msr_init(void) { - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); Modified: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c 2006-09-19 17:38:57 UTC (rev 2427) +++ trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c 2006-09-19 19:30:11 UTC (rev 2428) @@ -4,36 +4,32 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> #include "chip.h" +#define DIVIL_LBAR_GPIO 0x5140000c -static void init(struct device *dev) +static void init_gpio() { - unsigned bus = 0; - unsigned devNic = PCI_DEVFN(0xd, 0); - unsigned devUsb = PCI_DEVFN(0xf, 4); - device_t usb = NULL, nic = NULL; - unsigned char irqUsb = 0xa, irqNic = 0xb; + msr_t msr; + printk_debug("Initializing GPIO module...\n"); + // initialize the GPIO LBAR + msr.lo = GPIO_BASE; + msr.hi = 0x0000f001; + wrmsr(DIVIL_LBAR_GPIO, msr); + msr = rdmsr(DIVIL_LBAR_GPIO); + printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo); +} + +static void init(struct device *dev) +{ + // BOARD-SPECIFIC INIT printk_debug("ARTECGROUP DBE61 ENTER %s\n", __FUNCTION__); - // FIXME: do we need to initialize USB OHCI this way? - printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n", - __FUNCTION__, bus, devUsb, irqUsb); + init_gpio(); - // initialize the USB controller - usb = dev_find_slot(bus, devUsb); - if (!usb) printk_err("Could not find USB\n"); - else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb); - - printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n", - __FUNCTION__, bus, devNic, irqNic); - - // initialize the Realtek NIC - nic = dev_find_slot(bus, devNic); - if (!nic) printk_err("Could not find USB\n"); - else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic); - printk_debug("ARTECGROUP DBE61 EXIT %s\n", __FUNCTION__); }

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[LinuxBIOS] PATCH: abuild manpage and small fixes.
by Uwe Hermann 19 Sep '06

19 Sep '06

Hi, here's a manpage for abuild, as well as some small fixes for the romcc and flashrom manpages, plus license clarifications. HTH, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org

1 0

[LinuxBIOS] r2427 - in trunk/LinuxBIOSv2/targets/digitallogic: . msm800sev
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 19:38:57 +0200 (Tue, 19 Sep 2006) New Revision: 2427 Added: trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/ trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb Log: add target Added: trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb 2006-09-19 17:38:57 UTC (rev 2427) @@ -0,0 +1,27 @@ +# Config file for the digitallogic msm800sev + +target msm800sev +mainboard digitallogic/msm800sev + +option CONFIG_COMPRESSED_ROM_STREAM_NRV2B=0 + +## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## (normal AND fallback images and payloads). +## leave 64k for vsa and 32K for video ROM +option ROM_SIZE = 1024*256 - 64*1024 - 32 * 1024 + +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +## not including any payload. +option ROM_IMAGE_SIZE=64*1024 + +option FALLBACK_SIZE = ROM_SIZE + +option DEFAULT_CONSOLE_LOGLEVEL = 11 +option MAXIMUM_CONSOLE_LOGLEVEL = 11 +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback"

1 0

[LinuxBIOS] r2426 - in trunk/LinuxBIOSv2/src/mainboard: artecgroup/dbe61 digitallogic digitallogic/msm800sev
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 19:37:32 +0200 (Tue, 19 Sep 2006) New Revision: 2426 Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Config.lb trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Options.lb trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/auto.c trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/chip.h trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/cmos.layout trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/debug.c trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/failover.c trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/mainboard.c trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/reset.c Removed: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/cs5536_usb.c Log: add the msm800srv ; put the usb in the right place. Deleted: trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/cs5536_usb.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/cs5536_usb.c 2006-09-19 16:44:14 UTC (rev 2425) +++ trunk/LinuxBIOSv2/src/mainboard/artecgroup/dbe61/cs5536_usb.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -1,95 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -#include <cpu/amd/lxdef.h> -#include <cpu/x86/msr.h> - -#include "cs5536.h" - -#define GLIU2_P2D_BM_1 0x51010021 // southbridge GLIU P2D base mask descriptor -#define USBMSRUOCB 0x5120000b // USB option controller base address register -#define UOCMUX (USBOC_BASE_ADDRESS + 4) // option controller native multiplex register - -#define USBOC_BASE_ADDRESS 0xe1017000 // USB option contoller base address, used only here -#define USBOC_PORT4_FUNCTION 2 // USB port 4 desired function (0 = disabled, 2 = host, 3 = device) - -static void ohci_init(struct device *dev) -{ - uint32_t n; - msr_t msr; - - printk_debug("USB: Setting up OHCI controller... "); - - // enable controller bus mastering - n = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - n | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - // set the USB option controller base address - msr.hi = 0x0000000a; - msr.lo = USBOC_BASE_ADDRESS; - wrmsr(USBMSRUOCB, msr); - - // create the GLIU memory mapping - msr.hi = 0x40000000 | ((USBOC_BASE_ADDRESS >> 24) & 0x000000ff); - msr.lo = ((USBOC_BASE_ADDRESS << 8) & 0xfff00000) | 0x000fffff; - wrmsr(GLIU2_P2D_BM_1, msr); - - // set the multiplex register with port 4 function - *((uint32_t*)UOCMUX) = USBOC_PORT4_FUNCTION; - - // finally, disable the USB option controller memory mapping - msr.hi = 0x000000ff; - msr.lo = 0xfff00000; - wrmsr(GLIU2_P2D_BM_1, msr); - - printk_debug("done.\n"); -} - -static void ehci_init(struct device *dev) -{ - uint32_t cmd; - printk_debug("USB: Setting up EHCI controller... "); - - // enable controller bus mastering - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - printk_debug("done.\n"); -} - -static struct device_operations ohci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ohci_init, - .scan_bus = 0, - .enable = southbridge_enable, -}; - -static struct device_operations ehci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = southbridge_enable, -}; - -static struct pci_driver cs5536_usb1_driver __pci_driver = { - .ops = &ohci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_OHCI -}; - -static struct pci_driver cs5536_usb2_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_EHCI -}; Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Config.lb 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,157 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/amd/lx + # they keep changing this. 0:f.0 5c.w to see where it is + register "irqmap" = "0xbaba" + register "setupflash" = "1" + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536_lx + register "enable_gpio0_inta" = "1" + register "enable_ide_nand_flash" = "0" + register "enable_uarta" = "1" + register "audio_irq" = "11" + register "usbf4_irq" = "11" + register "usbf11_irq" = "11" + register "usbf6_irq" = "11" + register "usbf7_irq" = "11" + device pci d.0 on end # EEPRO 1000 + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0" # End of list has a zero + end + end +end + Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/Options.lb 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,162 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_STREAM +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM_START +uses CONFIG_COMPRESSED_ROM_STREAM_NRV2B +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=0 +default IRQ_SLOT_COUNT=6 + +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_STREAM = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end + Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/auto.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,193 @@ +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +//#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> + +//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/lx/raminit.h" + +static inline unsigned int fls(unsigned int x) +{ + int r; + + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; +} + + + + +/* sdram parameters for OLPC: + row address = 13 + col address = 9 + banks = 4 + dimm0size=128MB + d0_MB=1 (module banks) + d0_cb=4 (component banks) + do_psz=4KB (page size) + Trc=10 (clocks) (ref2act) + Tras=7 (act2pre) + Trcd=3 (act2cmd) + Trp=3 (pre2act) + Trrd=2 (act2act) + Tref=17.8ms + */ +static void sdram_set_spd_registers(const struct mem_controller *ctrl) +{ + /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * + * component Banks (byte 17) * module banks, side (byte 5) * + * width in bits (byte 6,7) + * = Density per side (byte 31) * number of sides (byte 5) */ + /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ + msr_t msr; + unsigned char module_banks, val; + + +#if 0 //GX3 + msr = rdmsr(MC_CF07_DATA); + + /* get module banks (sides) per dimm, SPD byte 5 */ + module_banks = 1; + module_banks >>= 1; + msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); + msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); + + /* get component banks per module bank, SPD byte 17 */ + val = 4; + val >>= 2; + msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); + + /* get the module bank density, SPD byte 31 */ + /* this is multiples of 8 MB */ + /* actually it is 2^x*4, where x is the value you put in */ + /* for OLPC, set default size */ + /* dimm size - hardcoded 128Mb */ + val = 5; + msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT); + + /* page size = 2^col address */ + val = 2; /* 4096 bytes */ + msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); + + print_debug("computed msr.hi "); + print_debug_hex32(msr.hi); + print_debug("\r\n"); + + /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ + /* well, it may be close. It's about 200,000 ticks */ + msr.lo = 0x00003000; + wrmsr(MC_CF07_DATA, msr); + +#endif + + msr.hi = 0x00005012; + msr.lo = 0x05000040; + + wrmsr(MC_CF07_DATA, msr); //GX3 + + /* timing and mode ... */ + + //msr = rdmsr(0x20000019); + + /* per standard bios settings */ +/* + msr.hi = 0x18000108; + msr.lo = + (6<<28) | // cas_lat + (10<<24)| // ref2act + (7<<20)| // act2pre + (3<<16)| // pre2act + (3<<12)| // act2cmd + (2<<8)| // act2act + (2<<6)| // dplwr + (2<<4)| // dplrd + (3); // dal + * the msr value reported by quanta is very, very different. + * we will go with that value for now. + * + //msr.lo = 0x286332a3; +*/ + //wrmsr(0x20000019, msr); //GX3 + +} + +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" + +#define PLLMSRhi 0x00001490 +#define PLLMSRlo 0x02000030 +#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) +#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) +#include "northbridge/amd/lx/pll_reset.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" +static void msr_init(void) +{ + __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); + + __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); + + __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); +} + + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl [] = { + {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + }; + + SystemPreInit(); //GX3 OK + + msr_init(); //GX3 OK + + cs5536_early_setup(); //GX3 OK + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536 + */ + cs5536_setup_onchipuart(); //GX3 OK + + uart_init(); //GX3 OK + console_init(); //GX3 OK + + pll_reset(); //GX3 OK + + cpuRegInit(); //GX3 OK + + print_err("done cpuRegInit\n"); + + sdram_initialize(1, memctrl); //GX3 OK almost + + /* Check all of memory */ + //ram_check(0x00000000, 640*1024); +} Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/chip.h 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_digitallogic_msm800sev_ops; + +struct mainboard_digitallogic_msm800sev_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/cmos.layout 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/debug.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/debug.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,66 @@ + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/failover.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,60 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include <arch/pirq_routing.h> + +#define ID_SLOT_PCI_NET 1 // ThinCan ethernet +#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1 +#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2 +#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3 +#define ID_EMBED_PCI 0xff // onboard PCI device + +// CS5535 PCI INT[A-D] Interrupt Routing lines. +#define NO_CONNECT 0 // not used +#define CS_PCI_INTA 1 // PCI INTA +#define CS_PCI_INTB 2 // PCI INTB +#define CS_PCI_INTC 3 // PCI INTC +#define CS_PCI_INTD 4 // PCI INTD + +// IRQ bitmap reference line FEDCBA9876543210 +// 0000110000100000b +#define PCI_IRQ 0xc20 // PCI allowed IRQs here + +const struct irq_routing_table intel_irq_routing_table = +{ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*6, /* there can be total 2 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0x0800, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x208f, /* Device */ + 0x00000000, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + // Geode GX3 Host Bridge and VGA Graphics + {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, + // Realtek RTL8100/8139 Network Controller + {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0}, + // Reserved for future extensions + {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0}, + // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio. + {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, + // Reserved for future extensions + {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0}, + // Reserved for future extensions + {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0} + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/mainboard.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,49 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "chip.h" + + +static void init(struct device *dev) +{ + unsigned bus = 0; + unsigned devNic = PCI_DEVFN(0xd, 0); + unsigned devUsb = PCI_DEVFN(0xf, 4); + device_t usb = NULL, nic = NULL; + unsigned char irqUsb = 0xa, irqNic = 0xb; + + printk_debug("DIGITALLOGIC MSM800SSEV ENTER %s\n", __FUNCTION__); + + // FIXME: do we need to initialize USB OHCI this way? + printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n", + __FUNCTION__, bus, devUsb, irqUsb); + + // initialize the USB controller + usb = dev_find_slot(bus, devUsb); + if (!usb) printk_err("Could not find USB\n"); + else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb); + + printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n", + __FUNCTION__, bus, devNic, irqNic); + + // initialize theEEPRO 100 + nic = dev_find_slot(bus, devNic); + if (!nic) printk_err("Could not find USB\n"); + else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic); + + printk_debug("DIGITALLOGIC MSM800SSEV EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_digitallogic_msm800sev_ops = { + CHIP_NAME("digitallogip msm800sev mainboard ") + .enable_dev = enable_dev, + +}; Added: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/reset.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/reset.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/reset.c 2006-09-19 17:37:32 UTC (rev 2426) @@ -0,0 +1,43 @@ +#if 0 +//#include "arch/romcc_io.h" +#include <arch/io.h> + +typedef unsigned device_t; + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFF) << 16) | \ + (((DEV) & 0x1f) << 11) | \ + (((FN) & 0x7) << 8)) + +static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); +} +#endif

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[LinuxBIOS] r2425 - trunk/LinuxBIOSv2/src/southbridge/amd/cs5536_lx
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 18:44:14 +0200 (Tue, 19 Sep 2006) New Revision: 2425 Added: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536_lx/cs5536_usb.c Log: put this in the right place. Added: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536_lx/cs5536_usb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536_lx/cs5536_usb.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536_lx/cs5536_usb.c 2006-09-19 16:44:14 UTC (rev 2425) @@ -0,0 +1,95 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +#include <cpu/amd/lxdef.h> +#include <cpu/x86/msr.h> + +#include "cs5536.h" + +#define GLIU2_P2D_BM_1 0x51010021 // southbridge GLIU P2D base mask descriptor +#define USBMSRUOCB 0x5120000b // USB option controller base address register +#define UOCMUX (USBOC_BASE_ADDRESS + 4) // option controller native multiplex register + +#define USBOC_BASE_ADDRESS 0xe1017000 // USB option contoller base address, used only here +#define USBOC_PORT4_FUNCTION 2 // USB port 4 desired function (0 = disabled, 2 = host, 3 = device) + +static void ohci_init(struct device *dev) +{ + uint32_t n; + msr_t msr; + + printk_debug("USB: Setting up OHCI controller... "); + + // enable controller bus mastering + n = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, + n | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + + // set the USB option controller base address + msr.hi = 0x0000000a; + msr.lo = USBOC_BASE_ADDRESS; + wrmsr(USBMSRUOCB, msr); + + // create the GLIU memory mapping + msr.hi = 0x40000000 | ((USBOC_BASE_ADDRESS >> 24) & 0x000000ff); + msr.lo = ((USBOC_BASE_ADDRESS << 8) & 0xfff00000) | 0x000fffff; + wrmsr(GLIU2_P2D_BM_1, msr); + + // set the multiplex register with port 4 function + *((uint32_t*)UOCMUX) = USBOC_PORT4_FUNCTION; + + // finally, disable the USB option controller memory mapping + msr.hi = 0x000000ff; + msr.lo = 0xfff00000; + wrmsr(GLIU2_P2D_BM_1, msr); + + printk_debug("done.\n"); +} + +static void ehci_init(struct device *dev) +{ + uint32_t cmd; + printk_debug("USB: Setting up EHCI controller... "); + + // enable controller bus mastering + cmd = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + + printk_debug("done.\n"); +} + +static struct device_operations ohci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ohci_init, + .scan_bus = 0, + .enable = southbridge_enable, +}; + +static struct device_operations ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ehci_init, + .scan_bus = 0, + .enable = southbridge_enable, +}; + +static struct pci_driver cs5536_usb1_driver __pci_driver = { + .ops = &ohci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_OHCI +}; + +static struct pci_driver cs5536_usb2_driver __pci_driver = { + .ops = &ehci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_EHCI +};

1 0

[LinuxBIOS] qemu and OLPC
by ron minnich 19 Sep '06

19 Sep '06

I almost have this going, needs some smart people to take a look. To use it, follow the qemu tutorial for getting and patching qemu. For the bios, ignore the instuctions. Do this: git-clone git://dev.laptop.org/users/jcrouse/buildrom cd buildrom Now you need to set things up so that you get a linuxbios for qemu. replace the Config.mk with the one I am attaching. not type make. After some time, you will have a deploy/linuxbios.rom to use as a bios. cp it to some directory, say your home dir. Now get an OLPC image, go to wiki.laptop.org and grab (e.g.) the build81 ext3 image. bunzip2 that image. Now do as the tutorial says: qemu -L ~ -hda1 blahblah.ext3 --nographic, e.g. /opt/qemu-0.8.2/bin/qemu -L ~ -hda roots/olpc-stream-development-81-20060831_1548-ext3.img -nographic and watch it boot up: LinuxBIOS-2.0.0-OpenBIOS Mon Sep 18 22:07:06 MDT 2006 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0-OpenBIOS Mon Sep 18 22:07:06 MDT 2006 booting... Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 0 set_pci_ops: seeking driver for 8086:1237 class 60000 PCI: 00:00.0 [8086/1237] enabled set_pci_ops: seeking driver for 8086:7000 class 60100 PCI: 00:01.0 [8086/7000] enabled set_pci_ops: seeking driver for 8086:7010 class 10180 PCI: 00:01.1 [8086/7010] enabled set_pci_ops: seeking driver for 8086:7113 class 68000 PCI: 00:01.3 [8086/7113] enabled set_pci_ops: seeking driver for 1013:b8 class 30000 PCI: 00:02.0 [1013/00b8] enabled set_pci_ops: seeking driver for 10ec:8029 class 20000 PCI: 00:03.0 [10ec/8029] enabled PCI: pci_scan_bus returning with max=00 done Allocating resources... Reading resources... Done reading resources. Setting resources... I would set ram size to 0x20000 Kbytes PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] prefmem PCI: 00:02.0 14 <- [0x00fe000000 - 0x00fe000fff] mem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] io Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 00/00 PCI: 00:00.0 cmd <- 140 PCI: 00:01.0 subsystem <- 00/00 PCI: 00:01.0 cmd <- 147 PCI: 00:01.1 cmd <- 141 PCI: 00:01.3 cmd <- 140 PCI: 00:02.0 cmd <- 143 PCI: 00:03.0 cmd <- 141 done. Initializing devices... Root Device init PCI: 00:00.0 init PCI: 00:01.0 init PCI: 00:01.1 init PCI: 00:01.3 init PCI: 00:02.0 init PCI: 00:03.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000b64 checksum 5dad Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfff20000 - 0xfffeffff Uncompressing to RAM 0x01000000 olen = 0x000c995e done. Found ELF candiate at offset 0 Dropping non PT_LOAD segment New segment addr 0x10000 size 0x1ab24 offset 0x168 filesize 0x561c (cleaned up) New segment addr 0x10000 size 0x1ab24 offset 0x168 filesize 0x561c New segment addr 0x91000 size 0x70 offset 0x5784 filesize 0x0 (cleaned up) New segment addr 0x91000 size 0x70 offset 0x5784 filesize 0x0 New segment addr 0x100000 size 0x700000 offset 0x5784 filesize 0x907c9 (cleaned up) New segment addr 0x100000 size 0x700000 offset 0x5784 filesize 0x907c9 New segment addr 0x800000 size 0x33a11 offset 0x95f4d filesize 0x33a11 (cleaned up) New segment addr 0x800000 size 0x33a11 offset 0x95f4d filesize 0x33a11 Loading Segment: addr: 0x0000000007fe8000 memsz: 0x0000000000006000 filesz: 0x000000000000561c Clearing Segment: addr: 0x0000000007fed61c memsz: 0x00000000000009e4 Loading Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070 filesz: 0x0000000000000000 Clearing Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000700000 filesz: 0x00000000000907c9 Clearing Segment: addr: 0x00000000001907c9 memsz: 0x000000000066f837 Loading Segment: addr: 0x0000000000016000 memsz: 0x0000000000014b24 filesz: 0x0000000000000000 Clearing Segment: addr: 0x0000000000016000 memsz: 0x0000000000014b24 Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000033a11 filesz: 0x0000000000033a11 120:stream_skip() - overflowed source buffer Jumping to boot code at 0x10000 Firmware type: LinuxBIOS Linux version 2.6.18-rc4jhc (rminnich(a)q.ccstar.lanl.gov) (gcc version 4.0.220051125 (Red Hat 4.0.2-8)) #1 Mon Sep 18 22:04:13 MDT 2006 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000bd0 (reserved) BIOS-e820: 0000000000000bd0 - 00000000000a0000 (usable) BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved) BIOS-e820: 0000000000100000 - 0000000008000000 (usable) user-defined physical RAM map: user: 0000000000000000 - 0000000000000bd0 (reserved) user: 0000000000000bd0 - 00000000000a0000 (usable) user: 00000000000f0000 - 00000000000f0400 (reserved) user: 0000000000100000 - 0000000007700000 (usable) 119MB LOWMEM available. DMI not present or invalid. Allocating PCI resources starting at 10000000 (gap: 07700000:f8900000) Detected 1694.659 MHz processor. Built 1 zonelists. Total pages: 30464 Kernel command line: console=ttyS0,115200 video=gxfb:1024x768 mem=119m rdinit=/linuxrc Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 PID hash table entries: 512 (order: 9, 2048 bytes) Console: colour dummy device 80x25 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 118932k/121856k available (780k kernel code, 2456k reserved, 191k data, 108k init, 0k highmem) Checking if this processor honours the WP bit even in supervisor mode... Ok. Calibrating delay using timer specific routine.. 3094.78 BogoMIPS (lpj=15473942) Mount-cache hash table entries: 512 CPU: L1 I cache: 8K CPU: L2 cache: 128K CPU: Intel Pentium II (Klamath) stepping 03 Checking 'hlt' instruction... OK. Unpacking initramfs... done Freeing initrd memory: 206k freed PCI: Using configuration type 1 Setting up standard PCI resources SCSI subsystem initialized usbcore: registered new driver usbfs usbcore: registered new driver hub PCI: Probing PCI hardware PCI quirk: region b000-b03f claimed by PIIX4 ACPI PCI: Using IRQ router PIIX/ICH [8086/7000] at 0000:00:01.0 PCI: Found IRQ 11 for device 0000:00:03.0 PCI: Ignore bogus resource 6 [0:0] of 0000:00:02.0 JFFS2 version 2.2. (NAND) (SUMMARY) (C) 2001-2006 Red Hat, Inc. io scheduler noop registered (default) Limiting direct PCI/PCI transfers. PCI: PIIX3: Enabling Passive Release on 0000:00:01.0 Activating ISA DMA hang workarounds. Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16450 Initializing USB Mass Storage driver... usbcore: registered new driver usb-storage USB Mass Storage support registered. usbcore: registered new driver usbhid drivers/usb/input/hid-core.c: v2.6:USB HID core driver serio: i8042 AUX port at 0x60,0x64 irq 12 serio: i8042 KBD port at 0x60,0x64 irq 1 Using IPI Shortcut mode Time: tsc clocksource has been installed. Freeing unused kernel memory: 108k freed input: AT Raw Set 2 keyboard as /class/input/input0 OLPC ROM rev_a_20060913-2 Build timestamp: 20060918 22:06:37 Starting bootmenu. Couldn't open /dev/fb0 NOTICE: Starting the shell... # TSC appears to be running slowly. Marking it as unstable Time: pit clocksource has been installed. # so you have a root prompt. But getting to graphics is another matter. ron

2 1

[LinuxBIOS] r2424 - trunk/LinuxBIOSv2/targets/emulation/qemu-i386
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 06:03:40 +0200 (Tue, 19 Sep 2006) New Revision: 2424 Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb Log: resize OLPC flash Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb 2006-09-19 03:47:35 UTC (rev 2423) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb 2006-09-19 04:03:40 UTC (rev 2424) @@ -3,7 +3,7 @@ target qemu-i386-OLPC mainboard emulation/qemu-i386 -option ROM_SIZE=1024*1024 +option ROM_SIZE=1024*1024 - (128 * 1024) option CONFIG_COMPRESSED_ROM_STREAM_LZMA=1 option CONFIG_PRECOMPRESSED_ROM_STREAM=0

1 0

[LinuxBIOS] r2423 - trunk/LinuxBIOSv2/targets/emulation/qemu-i386
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 05:47:35 +0200 (Tue, 19 Sep 2006) New Revision: 2423 Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb Log: Fix the name for buildrom script Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb 2006-09-19 03:43:30 UTC (rev 2422) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb 2006-09-19 03:47:35 UTC (rev 2423) @@ -18,5 +18,5 @@ payload /tmp/olpcpayload.elf end -buildrom ./qemu-bios-OLPC.rom ROM_SIZE "image" +buildrom ./linuxbios.rom ROM_SIZE "image"

1 0

[LinuxBIOS] r2422 - in trunk/LinuxBIOSv2: src/mainboard/emulation/qemu-i386 targets/emulation/qemu-i386
by svn＠openbios.org 19 Sep '06

19 Sep '06

Author: rminnich Date: 2006-09-19 05:43:30 +0200 (Tue, 19 Sep 2006) New Revision: 2422 Added: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Options.lb Log: add an OLPC target for qemu Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Options.lb 2006-09-18 22:52:24 UTC (rev 2421) +++ trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Options.lb 2006-09-19 03:43:30 UTC (rev 2422) @@ -6,6 +6,9 @@ uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_COMPRESS +uses CONFIG_COMPRESSED_ROM_STREAM_NRV2B +uses CONFIG_COMPRESSED_ROM_STREAM_LZMA +uses CONFIG_PRECOMPRESSED_ROM_STREAM uses CONFIG_ROM_STREAM uses IRQ_SLOT_COUNT uses MAINBOARD Added: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.OLPC.lb 2006-09-19 03:43:30 UTC (rev 2422) @@ -0,0 +1,22 @@ +# This will make a target directory of ./emulation_qemu-i386 + +target qemu-i386-OLPC +mainboard emulation/qemu-i386 + +option ROM_SIZE=1024*1024 +option CONFIG_COMPRESSED_ROM_STREAM_LZMA=1 +option CONFIG_PRECOMPRESSED_ROM_STREAM=0 + +option CC="gcc -m32" + +option HAVE_PIRQ_TABLE=1 +option IRQ_SLOT_COUNT=6 + +romimage "image" + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION="-OpenBIOS" + payload /tmp/olpcpayload.elf +end + +buildrom ./qemu-bios-OLPC.rom ROM_SIZE "image" +

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coreboot September 2006