coreboot September 2006

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[LinuxBIOS] r2407 - trunk/LinuxBIOSv2/src/mainboard/via/epia-m
by svn＠openbios.org 13 Sep '06

13 Sep '06

Author: stepan Date: 2006-09-13 09:52:41 +0200 (Wed, 13 Sep 2006) New Revision: 2407 Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Config.lb trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb trunk/LinuxBIOSv2/src/mainboard/via/epia-m/auto.c trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.asl trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.c Log: - fix irq routing for epia-mii cardbus slot. (signed off by Nick Barker) - some minor cleanups Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Config.lb 2006-09-13 04:33:07 UTC (rev 2406) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Config.lb 2006-09-13 07:52:41 UTC (rev 2407) @@ -132,6 +132,13 @@ config chip.h chip northbridge/via/vt8623 + + device apic_cluster 0 on + chip cpu/via/model_centaur + device apic 0 on end + end + end + device pci_domain 0 on chip southbridge/via/vt8235 @@ -180,10 +187,4 @@ device pci 0a.1 on end end end - - device apic_cluster 0 on - chip cpu/via/model_centaur - device apic 0 on end - end - end end Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb 2006-09-13 04:33:07 UTC (rev 2406) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb 2006-09-13 07:52:41 UTC (rev 2407) @@ -21,6 +21,7 @@ uses ROM_SECTION_SIZE uses ROM_SECTION_OFFSET uses CONFIG_ROM_STREAM_START +uses CONFIG_COMPRESSED_ROM_STREAM uses PAYLOAD_SIZE uses _ROMBASE uses _RAMBASE Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/auto.c 2006-09-13 04:33:07 UTC (rev 2406) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/auto.c 2006-09-13 07:52:41 UTC (rev 2407) @@ -32,17 +32,11 @@ #include "southbridge/via/vt8235/vt8235_early_smbus.c" - #include "southbridge/via/vt8235/vt8235_early_serial.c" static void memreset_setup(void) { } -/* - static void memreset(int controllers, const struct mem_controller *ctrl) - { - } -*/ static inline int spd_read_byte(unsigned device, unsigned address) { unsigned char c; @@ -50,12 +44,7 @@ return c; } - - #include "northbridge/via/vt8623/raminit.c" -/* - #include "sdram/generic_sdram.c" -*/ static void enable_mainboard_devices(void) { @@ -71,12 +60,11 @@ pci_write_config8(dev, 0x51, 0x1f); #if 0 // This early setup switches IDE into compatibility mode before PCI gets - // // a chance to assign I/Os - // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax - // // movb $0x09, %dl - // movb $0x00, %dl - // PCI_WRITE_CONFIG_BYTE - // + // a chance to assign I/Os + // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax + // // movb $0x09, %dl + // movb $0x00, %dl + // PCI_WRITE_CONFIG_BYTE #endif /* we do this here as in V2, we can not yet do raw operations * to pci! @@ -132,7 +120,7 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* init_timer();*/ + // init_timer(); outb(5, 0x80); @@ -170,5 +158,7 @@ early_mtrr_init(); } + //dump_pci_devices(); + print_spew("Leaving auto.c:main()\r\n"); } Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.asl 2006-09-13 04:33:07 UTC (rev 2406) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.asl 2006-09-13 07:52:41 UTC (rev 2407) @@ -205,10 +205,11 @@ /* PCI Routing Table */ Name (_PRT, Package () { - Package () {0x000AFFFF, 0x00, LNKD, 0x00}, // Cardbus Link D - Package () {0x000AFFFF, 0x01, LNKA, 0x00}, // Cardbus Link A - Package () {0x000AFFFF, 0x02, LNKB, 0x00}, // Cardbus Link B - Package () {0x000AFFFF, 0x03, LNKC, 0x00}, // Cardbus Link C + /* Epia-MII 6000e cardbus: */ + Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A + Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B + Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C + Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.c 2006-09-13 04:33:07 UTC (rev 2406) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.c 2006-09-13 07:52:41 UTC (rev 2407) @@ -1,22 +1,22 @@ /* * * Intel ACPI Component Architecture - * ASL Optimizing Compiler / AML Disassembler version 20040715 [Aug 16 2004] - * Copyright (C) 2000 - 2004 Intel Corporation - * Supports ACPI Specification Revision 2.0c + * ASL Optimizing Compiler version 20060127 [Apr 23 2006] + * Copyright (C) 2000 - 2006 Intel Corporation + * Supports ACPI Specification Revision 3.0a * - * Compilation of "dsdt.asl" - Thu Oct 27 09:25:57 2005 + * Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006 * * C source code output * */ -unsigned char AmlCode[] = +unsigned char AmlCode[] = { 0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00, /* 00000000 "DSDT...." */ - 0x01,0x11,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */ + 0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */ 0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */ 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ - 0x15,0x07,0x04,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "... .._P" */ + 0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "'.. .._P" */ 0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */ 0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08, /* 00000030 "0......." */ 0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00, /* 00000038 "_S0_...." */ @@ -81,13 +81,13 @@ 0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08, /* 00000210 ".._BBN.." */ 0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20, /* 00000218 "_PRT.C. " */ 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00, /* 00000220 "........" */ - 0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 00000228 ".LNKD..." */ + 0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000228 ".LNKA..." */ 0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C, /* 00000230 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKA....." */ + 0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKB....." */ 0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E, /* 00000240 "......LN" */ - 0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KB......" */ + 0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KC......" */ 0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000250 ".....LNK" */ - 0x43,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "C......." */ + 0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "D......." */ 0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00, /* 00000260 "...LNKB." */ 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00, /* 00000268 "........" */ 0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E, /* 00000270 ".LNKC..." */

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Re: [LinuxBIOS] DK8-HTX hangs on boot
by Chris Stillo 13 Sep '06

13 Sep '06

Hi Ron, We added ram_check(0x100000,0x400000) to auto.c and it passed. Looking at crt0.S.lb, it looks like when it executes it is taking the path for CONFIG_COMPRESS true, and getting hung up there. We never get the CONSOLE_DEBUG_TX_STRING($str_pre_main) message. Any ideas? Thanks, Chris PS I changed email addresses to get away from MS Outlook... as you probably know it is not friendly w/ Mailman. Hopefully my replies will start going onto the previous thread now, instead of starting a new one. > ------------------------------------------------------------------------ > *From:* ron minnich [mailto:rminnich@gmail.com] > *Sent:* Tuesday, September 12, 2006 8:55 AM > *To:* Chris Stillo > *Cc:* linuxbios(a)linuxbios.org > *Subject:* Re: [LinuxBIOS] DK8-HTX hangs on boot > > > > On 9/11/06, *Chris Stillo* <Chris.Stillo(a)celoxica.com > <mailto:Chris.Stillo@celoxica.com>> wrote: > > > Here's the detailed dump... Dies at "Copying LinuxBIOS to ram. " > > > > > It's memory.When it fails here, it is memory about 99.99999% of the > time :-) > > Which is odd, this is a very vanilla chipset. What's your memory? > > ron

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[LinuxBIOS] r2406 - trunk/LinuxBIOSv2/src/northbridge/amd/gx2
by svn＠openbios.org 13 Sep '06

13 Sep '06

Author: rminnich Date: 2006-09-13 06:33:07 +0200 (Wed, 13 Sep 2006) New Revision: 2406 Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c Log: Slow down the clock, per Tom Sylla Signed-off-by: Ronald G. Minnich Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c 2006-09-13 04:12:35 UTC (rev 2405) +++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c 2006-09-13 04:33:07 UTC (rev 2406) @@ -126,7 +126,7 @@ #define DEFAULT_MDIV 3 #define DEFAULT_VDIV 2 -#define DEFAULT_FBDIV 24 // 400/266 018 ;300/200 +#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 static void pll_reset(void) {

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[LinuxBIOS] r2405 - trunk/LinuxBIOSv2/src/cpu/emulation/qemu-i386
by svn＠openbios.org 13 Sep '06

13 Sep '06

Author: rminnich Date: 2006-09-13 06:12:35 +0200 (Wed, 13 Sep 2006) New Revision: 2405 Modified: trunk/LinuxBIOSv2/src/cpu/emulation/qemu-i386/northbridge.c Log: fix for qemu northbridge, from Ed Swierk Signed-off-by: Ronald G. Minnich Modified: trunk/LinuxBIOSv2/src/cpu/emulation/qemu-i386/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/emulation/qemu-i386/northbridge.c 2006-09-13 01:57:47 UTC (rev 2404) +++ trunk/LinuxBIOSv2/src/cpu/emulation/qemu-i386/northbridge.c 2006-09-13 04:12:35 UTC (rev 2405) @@ -67,16 +67,40 @@ static void pci_domain_set_resources(device_t dev) { + static const uint8_t ramregs[] = { + 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 + }; device_t mc_dev; uint32_t pci_tolm; - uint32_t idx; pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; if (mc_dev) { unsigned long tomk, tolmk; - /* Hard code the Top of memory for now */ - tomk = 65536; + unsigned char rambits; + int i, idx; + + for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + unsigned char reg; + reg = pci_read_config8(mc_dev, ramregs[i]); + /* these are ENDING addresses, not sizes. + * if there is memory in this slot, then reg will be > rambits. + * So we just take the max, that gives us total. + * We take the highest one to cover for once and future linuxbios + * bugs. We warn about bugs. + */ + if (reg > rambits) + rambits = reg; + if (reg < rambits) + printk_err("ERROR! register 0x%x is not set!\n", + ramregs[i]); + } + if (rambits == 0) { + printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n"); + rambits = 8; + } + printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); + tomk = rambits*8*1024; /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { @@ -84,14 +108,9 @@ */ tolmk = tomk; } - /* Report the memory regions */ idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); - if (tomk > 4*1024*1024) { - ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); - } + ram_resource(dev, idx++, 0, tolmk); } assign_resources(&dev->link[0]); }

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[LinuxBIOS] r2404 - in trunk/LinuxBIOSv2/src/northbridge/amd: gx2 lx
by svn＠openbios.org 13 Sep '06

13 Sep '06

Author: rminnich Date: 2006-09-13 03:57:47 +0200 (Wed, 13 Sep 2006) New Revision: 2404 Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c Log: warm boot patch from richard smith. signed-off-by: Ronald G. Minnich Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c 2006-09-13 01:14:45 UTC (rev 2403) +++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c 2006-09-13 01:57:47 UTC (rev 2404) @@ -94,6 +94,17 @@ msr.lo = 0x8ea0ad6a; wrmsr(0x4c00000f, msr); - /* DRAM working now?? */ + /* Fixes from Jordan Crouse of AMD. */ + /* make sure there is nothing stale in the cache */ + __asm__("wbinvd\n"); + + print_debug("RAM DLL lock\r\n"); + /* The RAM dll needs a write to lock on so generate a few dummy writes */ + volatile unsigned long *ptr; + for (i=0;i<5;i++) { + ptr = (void *)i; + *ptr = (unsigned long)i; + } + } Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2006-09-13 01:14:45 UTC (rev 2403) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2006-09-13 01:57:47 UTC (rev 2404) @@ -135,6 +135,17 @@ print_debug("DRAM controller init done.\r\n"); - /* DRAM working now?? */ + /* Fixes from Jordan Crouse of AMD. */ + /* make sure there is nothing stale in the cache */ + __asm__("wbinvd\n"); + + print_debug("RAM DLL lock\r\n"); + /* The RAM dll needs a write to lock on so generate a few dummy writes */ + volatile unsigned long *ptr; + for (i=0;i<5;i++) { + ptr = (void *)i; + *ptr = (unsigned long)i; + } + }

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[LinuxBIOS] r2403 - in trunk/LinuxBIOSv2: src/mainboard/emulation/qemu-i386 targets/emulation/qemu-i386
by svn＠openbios.org 13 Sep '06

13 Sep '06

Author: rminnich Date: 2006-09-13 03:14:45 +0200 (Wed, 13 Sep 2006) New Revision: 2403 Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/irq_tables.c trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb Log: Fix the irq_tables signed-off-by: ronald g. minnich Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/irq_tables.c 2006-09-13 01:10:08 UTC (rev 2402) +++ trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/irq_tables.c 2006-09-13 01:14:45 UTC (rev 2403) @@ -1,33 +1,32 @@ /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*5, /* there can be total 5 devices on the bus */ - 0, /* Where the interrupt router lies (bus) */ - 0x88, /* Where the interrupt router lies (dev) */ - 0x1c20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x8231, /* Device */ - 0, /* Crap (miniport) */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*6, /* there can be total 6 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x01<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* 8231 ethernet */ - {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, - /* 8231 internal */ - {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, - /* PCI slot */ - {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0}, - {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}, - {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0}, + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb 2006-09-13 01:10:08 UTC (rev 2402) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb 2006-09-13 01:14:45 UTC (rev 2403) @@ -7,6 +7,9 @@ option CC="gcc -m32" +option HAVE_PIRQ_TABLE=1 +option IRQ_SLOT_COUNT=6 + romimage "image" option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION="-OpenBIOS"

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[LinuxBIOS] r2402 - in trunk/LinuxBIOSv2: src/mainboard/emulation/qemu-i386 targets/emulation/qemu-i386
by svn＠openbios.org 13 Sep '06

13 Sep '06

Author: rminnich Date: 2006-09-13 03:10:08 +0200 (Wed, 13 Sep 2006) New Revision: 2402 Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb Log: mods for qemu, these build signed-off-by: ronald g. minnich Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb 2006-09-08 17:44:42 UTC (rev 2401) +++ trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb 2006-09-13 01:10:08 UTC (rev 2402) @@ -3,16 +3,9 @@ ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## default ROM_SIZE = 256 * 1024 -default FALLBACK_SIZE = 128*1024 +default ROM_SECTION_SIZE = ROM_SIZE +default ROM_SECTION_OFFSET = 0 -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = 128 * 1024 # FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - ## ## Compute the start location and size size of ## The linuxBIOS bootloader. @@ -82,13 +75,8 @@ ## ## Build our reset vector (This is where linuxBIOS is entered) ## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end +mainboardinit cpu/x86/16bit/reset16.inc +ldscript /cpu/x86/16bit/reset16.lds ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc @@ -100,16 +88,6 @@ ldscript /arch/i386/lib/id.lds ### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### ### O.k. We aren't just an intermediary anymore! ### Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb 2006-09-08 17:44:42 UTC (rev 2401) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb 2006-09-13 01:10:08 UTC (rev 2402) @@ -8,7 +8,6 @@ option CC="gcc -m32" romimage "image" - option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION="-OpenBIOS" payload /home/stepan/openbios.elf

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[LinuxBIOS] [PATCH] Allow setting ROM_SIZE for qemu target
by Ed Swierk 13 Sep '06

13 Sep '06

Currently the qemu target is configured to always use a fallback image, and the size of the image is hardcoded to 128KB. The attached patch allows changing the image size by setting ROM_SIZE in the target Config.lb. It removes all the fallback-related stuff from the qemu mainboard Config.lb, since it wasn't doing anything useful and I couldn't think of a reason to keep it. --Ed

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[LinuxBIOS] PCI IRQ routing issues with qemu
by Ed Swierk 13 Sep '06

13 Sep '06

Hello, I'm having some trouble getting Linux to recognize Ethernet and USB devices when booting with LinuxBIOS on qemu 0.8.2. During boot I see messages like: ne2k-pci.c:v1.03 9/22/2003 D. Becker/P. Gortmaker http://www.scyld.com/network/ne2k-pci.html PCI: No IRQ known for interrupt pin A of device 0000:00:03.0. Please try using pci=biosirq. eth0: RealTek RTL-8029 found at 0x1000, IRQ 0, 52:54:00:12:34:56. and USB Universal Host Controller Interface driver v3.0 PCI: No IRQ known for interrupt pin D of device 0000:00:01.2. Please try using pci=biosirq. uhci_hcd 0000:00:01.2: Found HC with no IRQ. Check BIOS/PCI 0000:00:01.2 setup! uhci_hcd 0000:00:01.2: init 0000:00:01.2 fail, -19 After groveling through the list archive for clues, I used getpir to update irq_tables.c, since it looks like the one in src/mainboard/emulation/qemu-i386 is pretty old. I validated the resulting table with checkpir, and added "option HAVE_PIRQ_TABLE=1" to Config.lb. LinuxBIOS doesn't seem to be able to use the new table, though: Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...failed Any further clues would be appreciated. I've attached my boot log, irq_tables.c, Config.lb, as well as the output of lspci after booting with qemu's standard BIOS. --Ed

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[LinuxBIOS] romcc and epia
by Ben Hewson 12 Sep '06

12 Sep '06

I have been looking through auto.inc and it would be very helpful if besides printing the line no inside auto.c, it would also print the actual C line. Does anyone know how easy this would be to do ? The reason I am asking this is because of the problem I am having with the epia code. There is this bit of C code // SDRAM in all banks pci_write_config8(north, 0x60, 0x3F); // DRAM timing. I'm suspicious of this // This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5. // ras precharge 4T, RAS pulse 5T // cas2 is 0xd6, cas3 is 0xe6 // we're also backing off write pulse width to 2T, so result is 0xee #if DIMM_CL2 pci_write_config8(north, 0x64, 0xd6); pci_write_config8(north, 0x65, 0xd6); pci_write_config8(north, 0x66, 0xd6); #else // CL=3 pci_write_config8(north, 0x64, 0xe6); pci_write_config8(north, 0x65, 0xe6); pci_write_config8(north, 0x66, 0xe6); #endif print_debug_hex8(pci_read_config8(north, 0x64)); print_debug_hex8(pci_read_config8(north, 0x65)); print_debug_hex8(pci_read_config8(north, 0x66)); ok now loking at the serial output I get the following snippet 1106 0601 ece6e6init 1 done the important bit is the ece6e6 Ok now as you can see it is not writing to the register properly. So I am now looking through auto.inc and trying to find the relevant code. While I will be honest and say at the moment I do not 100% understand it, I can never the less find the relevant assembler code. Anyway this is it ********** first bit I think is for this line pci_write_config8(north, 0x60, 0x3F); *********** mov $63 , %al mov $3324 , %dx outb %al, %dx /* ,:0.0 */ /* * pci_write_config8,romcc_io.h:148.38 * sdram_set_registers,raminit.c:164.26 * main,auto.c:107.28 */ /* ,:0.0 */ /* * __builtin_outl,<built-in>:1.0 * outl,io.h:25.23 * pci_write_config8,romcc_io.h:148.13 * sdram_set_registers,raminit.c:164.26 * main,auto.c:107.28 */ mov $-2147483548 , %eax mov $3320 , %dx outl %eax, %dx /* ,:0.0 */ /* * __builtin_outb,<built-in>:1.0 * outb,io.h:15.23 * pci_write_config8,romcc_io.h:149.13 * sdram_set_registers,raminit.c:164.26 * main,auto.c:107.28 */ ********* ok here is 1 write of 0xe6 ********** mov $230 , %al mov $3325 , %dx outb %al, %dx /* ,:0.0 */ /* * pci_write_config8,romcc_io.h:148.38 * sdram_set_registers,raminit.c:165.26 * main,auto.c:107.28 */ /* ,:0.0 */ /* * __builtin_outl,<built-in>:1.0 * outl,io.h:25.23 * pci_write_config8,romcc_io.h:148.13 * sdram_set_registers,raminit.c:165.26 * main,auto.c:107.28 */ mov $-2147483548 , %eax mov $3320 , %dx outl %eax, %dx /* ,:0.0 */ /* * __builtin_outb,<built-in>:1.0 * outb,io.h:15.23 * pci_write_config8,romcc_io.h:149.13 * sdram_set_registers,raminit.c:165.26 * main,auto.c:107.28 */ ********** here is 2nd write of 0xe6 ************ mov $230 , %al mov $3326 , %dx outb %al, %dx /* * pci_read_config8,romcc_io.h:124.38 * sdram_set_registers,raminit.c:169.42 * main,auto.c:107.28 */ /* ,:0.0 */ /* * __builtin_outl,<built-in>:1.0 * outl,io.h:25.23 * pci_read_config8,romcc_io.h:124.13 * sdram_set_registers,raminit.c:169.42 * main,auto.c:107.28 */ mov $-2147483548 , %eax mov $3320 , %dx outl %eax, %dx /* ,:0.0 */ /* ******** now we get to read back the values ready to print ************ * __builtin_inb,<built-in>:1.0 * inb,io.h:31.29 * pci_read_config8,romcc_io.h:125.19 * sdram_set_registers,raminit.c:169.42 * main,auto.c:107.28 Ok now unless I am going crazy there appear to only be 2 writes of 0xe6 !!!! Where is the 3rd one? Also if romcc has missed this out, it is also possible that other bits of code are not getting executed. Ok now maybe I am wrong and not understanding auto.inc but I am pretty sure I am looking at the right bit of code here. What do you think ?

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coreboot September 2006