coreboot April 2006

coreboot@coreboot.org

50 participants
115 discussions

Start a nNew thread

Re: [LinuxBIOS] some more tyan/s2881 questions
by Lu, Yinghai 18 Apr '06

18 Apr '06

Without enabling the ACPI, the power off works? YH

2 1

Re: [LinuxBIOS] broadcom HT1000 SATA PHY initializing
by Lu, Yinghai 17 Apr '06

17 Apr '06

I will test that. Thanks YH -----Original Message----- From: Jia Jianwei [mailto:JJia@Fortinet.com] Sent: Monday, April 17, 2006 11:49 AM To: Lu, Yinghai; linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] broadcom HT1000 SATA PHY initializing Because my BIOS source is different with LinuxBIOS, so I think just replace sata_init() in bcm_5785_sata.c should be working. Do not need a soft_reset.In my BIOS source, I just do it after PCI device enumerate and resource allocation. Regards, Jianwei ----- Original Message ----- From: "Lu, Yinghai" <yinghai.lu(a)amd.com> To: "Jia Jianwei" <JJia(a)Fortinet.com>; <linuxbios(a)linuxbios.org> Sent: Monday, April 17, 2006 11:30 AM Subject: RE: [LinuxBIOS] broadcom HT1000 SATA PHY initializing > Good. > > Where to call it? Auto stage or called by hardwaremain driver? > > Need to be effective after soft_reset? > > YH > > -----Original Message----- > From: Jia Jianwei [mailto:JJia@Fortinet.com] > Sent: Monday, April 17, 2006 11:23 AM > To: Lu, Yinghai; linuxbios(a)linuxbios.org > Subject: Re: [LinuxBIOS] broadcom HT1000 SATA PHY initializing > > > Sata should be working with the following initializing code. (verified > on > two boards). Thanks! > > Jianwei > > > void HT1000_SATA_init( void ) > { > volatile unsigned int *mmio_reg; > unsigned int mmio_base,val32; > int i; > > pcibios_write_config_byte( 1, HT1000_SATA, 0x70, 0x18); > pcibios_write_config_byte( 1, HT1000_SATA, 0x78, 0x04); > > pcibios_read_config_dword (1, HT1000_SATA, 0x24, &mmio_base); > > mmio_base &= 0xfffffffc; > > mmio_reg = (unsigned int *)( mmio_base + 0x10f0 ); > > * mmio_reg = 0x40000001; > > mmio_reg = ( unsigned int *)( mmio_base + 0x8c ); > * mmio_reg = 0x00ff2007; > mdelay( 10 ); > * mmio_reg = 0x78592009; > mdelay( 10 ); > * mmio_reg = 0x00082004; > mdelay( 10 ); > * mmio_reg = 0x00002004; > mdelay( 10 ); > > for( i = 0; i < 4; i ++ ) > { > mmio_reg = ( unsigned int *)( mmio_base + 0x40 + i * 256 > ); > val32 = *mmio_reg ; > if( val32 & 0x4 ) > { > mmio_reg = ( unsigned int *)( mmio_base + 0x48 + > i * > 256); > val32 = *mmio_reg; > val32 |= 1; > *mmio_reg = val32; > mdelay( 10 ); > val32 &= ( ~1 ); > *mmio_reg = val32; > mdelay( 10 ); > } > } > > } > > > > > ----- Original Message ----- > From: "Lu, Yinghai" <yinghai.lu(a)amd.com> > To: "Jia Jianwei" <JJia(a)Fortinet.com>; <linuxbios(a)linuxbios.org> > Sent: Friday, March 31, 2006 11:40 AM > Subject: RE: [LinuxBIOS] broadcom HT1000 SATA PHY initializing > > > > You should be right. > > > > When I was testing that on Broadcom BLAST ref board: STAT and IDE > > doesn't work. > > > > But on another MB (serverworks HT1000 based), IDE is working. > > > > Maybe some magic bit in pci conf space need to set by option rom... > > > > You could compare the pci conf dump between system bios and > LinuxBIOS... > > > > BTW, Can drop your funny signature in LinuxBIOS? > > > > YH > > > > > > > > > > >

1 0

Re: [LinuxBIOS] broadcom HT1000 SATA PHY initializing
by Lu, Yinghai 17 Apr '06

17 Apr '06

Good. Where to call it? Auto stage or called by hardwaremain driver? Need to be effective after soft_reset? YH -----Original Message----- From: Jia Jianwei [mailto:JJia@Fortinet.com] Sent: Monday, April 17, 2006 11:23 AM To: Lu, Yinghai; linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] broadcom HT1000 SATA PHY initializing Sata should be working with the following initializing code. (verified on two boards). Thanks! Jianwei void HT1000_SATA_init( void ) { volatile unsigned int *mmio_reg; unsigned int mmio_base,val32; int i; pcibios_write_config_byte( 1, HT1000_SATA, 0x70, 0x18); pcibios_write_config_byte( 1, HT1000_SATA, 0x78, 0x04); pcibios_read_config_dword (1, HT1000_SATA, 0x24, &mmio_base); mmio_base &= 0xfffffffc; mmio_reg = (unsigned int *)( mmio_base + 0x10f0 ); * mmio_reg = 0x40000001; mmio_reg = ( unsigned int *)( mmio_base + 0x8c ); * mmio_reg = 0x00ff2007; mdelay( 10 ); * mmio_reg = 0x78592009; mdelay( 10 ); * mmio_reg = 0x00082004; mdelay( 10 ); * mmio_reg = 0x00002004; mdelay( 10 ); for( i = 0; i < 4; i ++ ) { mmio_reg = ( unsigned int *)( mmio_base + 0x40 + i * 256 ); val32 = *mmio_reg ; if( val32 & 0x4 ) { mmio_reg = ( unsigned int *)( mmio_base + 0x48 + i * 256); val32 = *mmio_reg; val32 |= 1; *mmio_reg = val32; mdelay( 10 ); val32 &= ( ~1 ); *mmio_reg = val32; mdelay( 10 ); } } } ----- Original Message ----- From: "Lu, Yinghai" <yinghai.lu(a)amd.com> To: "Jia Jianwei" <JJia(a)Fortinet.com>; <linuxbios(a)linuxbios.org> Sent: Friday, March 31, 2006 11:40 AM Subject: RE: [LinuxBIOS] broadcom HT1000 SATA PHY initializing > You should be right. > > When I was testing that on Broadcom BLAST ref board: STAT and IDE > doesn't work. > > But on another MB (serverworks HT1000 based), IDE is working. > > Maybe some magic bit in pci conf space need to set by option rom... > > You could compare the pci conf dump between system bios and LinuxBIOS... > > BTW, Can drop your funny signature in LinuxBIOS? > > YH > > >

2 1

Re: [LinuxBIOS] broadcom HT1000 SATA PHY initializing
by Lu, Yinghai 17 Apr '06

17 Apr '06

You should be right. When I was testing that on Broadcom BLAST ref board: STAT and IDE doesn't work. But on another MB (serverworks HT1000 based), IDE is working. Maybe some magic bit in pci conf space need to set by option rom... You could compare the pci conf dump between system bios and LinuxBIOS... BTW, Can drop your funny signature in LinuxBIOS? YH

2 2

[LinuxBIOS] Intel D865GLC motherboard support?
by Micael Beronius 15 Apr '06

15 Apr '06

Hi all, I have been reading up on Linuxbios, and with 2 motherboards from Intel that I'd like to use for this project, I feel it is time to start up. How complicated is it to adapt Linuxbios to these two boards? Has it been done (did not find any indicatons for this searching the list and reading the doc), and if not, what's missing. These boards uses the 865G chipset with gigabit ethernet through CSA and Intel specifies: 82801EB I/O Controller HUB (ICH5) 82802AB 4Mbit Firmware Hub 82865G Graphics and Memory Controller Hub Analog devices AD1985 Audio codec LPC Bus I/O Controller (both SMSC LPC47M172 and National Semiconductor PC87372 are listen) Gigabit ethernet using Intel 82547EI PLC (over CSA) All according to the documentation ftp://download.intel.com/design/motherbd/lc/C3263401.pdf lspci gives; helium micke # lspci 00:00.0 Host bridge: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface (rev 02) 00:01.0 PCI bridge: Intel Corporation 82865G/PE/P PCI to AGP Controller (rev 02) 00:03.0 PCI bridge: Intel Corporation 82865G/PE/P PCI to CSA Bridge (rev 02) 00:1d.0 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 (rev 02) 00:1d.1 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 (rev 02) 00:1d.2 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 (rev 02) 00:1d.3 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 (rev 02) 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2) 00:1f.0 ISA bridge: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller (rev 02) 00:1f.2 IDE interface: Intel Corporation 82801EB (ICH5) SATA Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller (rev 02) 00:1f.5 Multimedia audio controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller (rev 02) 01:00.0 VGA compatible controller: nVidia Corporation GeForce 6200 (rev a1) 02:01.0 Ethernet controller: Intel Corporation 82547EI Gigabit Ethernet Controller (LOM) Thanks, - Micael

1 0

Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK (and a patch)
by Lu, Yinghai 14 Apr '06

14 Apr '06

Please try another switch In southbridge/amd/amd8111/amd8111_pci.c Line dword |= (1<<27) /* discard Timer */ ===> dword &= ~(1<<27); YH -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Ward Vandewege Sent: Monday, April 10, 2006 7:15 AM To: Alan Mimms Cc: linuxbios(a)linuxbios.org; Lu, Yinghai Subject: Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK (and a patch) On Fri, Apr 07, 2006 at 04:00:28PM -0700, Alan Mimms wrote: > The code should be setting the 1<<4 bit (so as to clear one of the error > bits) instead of 1<<6 (the read only bit that signals end of HT bus > chain). > > After making this change, your board won't hang when the BIOS or Linux > detects a need to reboot due to some fatal error. > > This is a pretty trivial change to an error case that hardly ever occurs > but was crucial for us. I claim this change is safe and correct and > should be merged into the main line code. Yes, please merge that change! Our box now keeps rebooting itself instead of crashing - have a look at the attached boot log. Maybe this will be more of a clue as to what exactly is happening? Anyone got anymore ideas? Thanks, Alan!! Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

5 6

Re: [LinuxBIOS] flash_rom on Nvidia CK804
by Lu, Yinghai 13 Apr '06

13 Apr '06

These should be DMI info ...., You can backup it and restore it late. YH

3 4

[LinuxBIOS] Chipset docs for ITE 8712F missing
by Carl-Daniel Hailfinger 13 Apr '06

13 Apr '06

Hi Ron, iirc you wanted to post the docs for the ITE 8712F SuperIO to the LinuxBIOS website. However, I can't find them with the wiki search. Did I make a mistake? Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

Re: [LinuxBIOS] flash_rom on Nvidia CK804
by Carl-Daniel Hailfinger 13 Apr '06

13 Apr '06

Hi Scott, Scott Leffel schrieb: > > or another of the embedded systems developers I know would have > a little spare time though, so I'll have to see if I can get them > interested in LinuxBIOS. As for That would be cool. > the chipset hurdle, is the CK804 = nForce4? Just trying to gauge > roughly how far along this might already be in terms of progress. Yes. AFAICS you would just need to find someone writing the driver for the SuperIO and a little bit of glue code and you'd be done. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[LinuxBIOS] flash_rom on Nvidia CK804
by Scott Leffel 12 Apr '06

12 Apr '06

When this thread began the other day, I know mention was made of the Asus A8N-SLI Deluxe board. Since (I think) the focus of this discussion has been on making sure it's safe to flash an Asus image back onto the board, I wanted to make sure the inference I'm drawing is correct, namely that this board in fact supports a working build of LinuxBIOS v2.0? One of my main systems is based on that board, and since I've been wanting to dabble in LinuxBIOS for a long time (but, alas, haven't had any supported hardware) I thought this sounded like a good opening. Is CK804 some barely published term for the nForce4 'southbridge'? When I've searched nVidia's own site for the keyword CK804 it's always come up with nothing, so I had no idea that might have been referring to my own chip(set) all along. If this does successfully build, and safely burn to flash, does anybody know if the 4Mib is sufficient for a useful kernel, or would I need to use an EtherBoot payload? Hopefully this isn't too risky; my only other faintly promising prospect - in terms of a board that was ever on the supported hardware list - is with an OLD Tyan "Tsunami" S1846 board! That was merged into FreeBIOS v1.0, oh, it looks like sometime several years ago, and has since been seemingly dumped. Doh! --------------------------------- Love cheap thrills? Enjoy PC-to-Phone calls to 30+ countries for just 2¢/min with Yahoo! Messenger with Voice.

2 1

← Newer
1
...
5
6
7
8
9
10
11
12
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2006